Integrated Magnetic Filter Transformer Design for Grid Connected Single Phase PWM-VSI

Integrated Magnetic Filter Transformer

Design for Grid Connected Single Phase

PWM-VSI

A Project Report

Submitted in Partial Fulfilment of

Requirements for the Degree of

Master of Engineering

in

Electrical Engineering

By

D. Venkatramanan

Department of Electrical Engineering

Indian Institute of Science

Bangalore - 560 012

India

June 2010

Acknowledgements

I am grateful to my guide Dr. Vinod John, for giving me the opportunity to work with him

on a fascinating and challenging problem. I sincerely thank him for his timely suggestions,

brilliant ideas, remarkable patience and constant encouragement. The lively discussions that

I had had with him and the great deal of freedom that I had enjoyed during my work are

deeply acknowledged.

I consider myself fortunate for having been thought by Prof. V. Ramanarayanan. His hyp-

notic lectures made the subject exceedingly simple. I express my heartfelt gratitude to him

for all that I have learnt from him (including power electronics), his invaluable suggestions,

motivation and above all, for the excellent example he has set as a professor. He has through-

out been a strong source of inspiration as a person.

I thank Prof. V. T. Ranganathan for his splendid course on Electric drives. He had given

me a broad perspective on closed loop control through his wonderful (patient) lectures.

I sincerely thank Prof. G. Narayanan and Prof. Udaya Kumar for their extraordinary lectures

on Pulse Width Modulation and Electromagnetics respectively.

It was a privilege for me to be associated with all of them.

I specially thank Anirban da for patiently helping at many critical junctures of my project

work. I also thank all other PhD students of the PEG group viz. Kamalesh Hatua, Amit

Jain, Shivaprasad, Deepankar De, AKP and Pavan Kumar Hari for maintaining an excellent

work culture in the lab and also for helping me in project.

I thank Anand, Manoj Modi, Shan (Reddy) of the Gang for all the technical and non-

technical engagements that we had had during our stay at IISc.

I also thank Vishnu, Tarak, Prakash, Raju, Hedyati Mohammad, Aneesa, Jim, Rajesh, Anil

das, Anil adapa, Srikanth Reddy for helping me in various ways and being very supportive

friends.

i

ii Acknowledgements

Special thanks must go to Anand and Prakash for making the lab (Room 112) environment

amicable and conducive for learning.

I sincerely thank my father for extending his valuable support and encouragement through-

out.

I thank Silvi madam for her kind help and support. I also extend my thanks to Mr D.

M. Channegowda and his team in the EE office for the smooth conduct of administrative

activities. I thank Mr.Ravi and his workshop team for their help during the project. I am

also grateful to IISc administration for providing a very good working environment overall.

Finally I would like to thank God Almighty for making everything go so smoothly.

Abstract

Background

Now a days, several governments and utilities worldwide promote renewable energy sources

such as Photovolaics (PV), Fuel cells, micro-turbines etc for distributed power generation

systems(DGPS), so as to deal with issues like rising prices of energy and environmental

concerns. DGPS are renewable energy sources linked up to the grid at the point of load.

This eliminates losses during transmission and distribution and also improves reliability of

the power supply. However, a DC/AC power converter and a filter are invariably required

for such an interconnection. The power quality of the grid interface is influenced by the

quality of the injected current and the filter here essentially brings down the distortion (in

the sinusoidal current and voltage waveforms) caused by the power converter.

The conventional way of interface is through a simple first order filter, which is bulky,

inefficient and cannot meet the regulatory requirements pertaining to interconnection of

harmonic loads to the grid. Higher order filters are becoming exceedingly popular as they

offer higher attenuation even at lower switching frequency for a similar filter size. Many a

times, a transformer would be necessary after the filter stage to enable grid interface. The

transformer provides galvanic isolation and an extra degree of freedom to adjust the output

voltage level to that of the grid.

Magnetic components often constitute a significant part of the overall size and cost of

the grid connected power system. Hence a compact and inexpensive design is desirable.

The present work is on design of an integrated filter-transformer structure where the

magnetic components of the higher order filter are integrated into the transformer. A three

winding transformer configuration is proposed for such an integration. The single compact

structure would now perform the functions of both the filter and the transformer. This work

iii

iv Abstract

targets single phase applications and hence focus is laid on Proportional-Resonant (PR)

controllers for accurate AC reference tracking in closed loop control. The power converter is

being operated as a STATCOM and as an Active Front End Converter (AFEC) in the grid

interactive mode for performance evaluation.

Organisation of report

Introduction introduces the issues pertaining to grid interface, imparts relevant back-

ground knowledge and finally presents the goal of this work.

Transformer and Magnetic integration discusses about the proposed three winding

configuration for magnetic integration, principle of operation, winding structure, transfer

function analysis, transformer design, and leakage inductance evaluation.

Power circuit for grid interface, sensor and digital controller deals with the

hardware details of the power converter, non-isolated sensor cards and the FPGA based

digital controller; It also explains single phase grid interface scheme, starting procedure, and

digital control implementation.

Single phase closed loop control deals with all the essentials for closing the loop, single

phase resonant PLL design, PR controller design for current control, PI controller design for

DC bus voltage regulation and STATCOM/ AFEC operation of the power converter.

Results and conclusion reports various simulation and experimental results that are

used to verify the performances of integrated filter-transformer, PR/PI controllers, grid

connected power converter etc. and finally concludes the work based on the results.

Contents

Acknowledgements i

Abstract iii

List of Tables viii

List of Figures ix

1 Introduction 1

1.1 Current Scenario . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

1.1.1 Higher order filter design . . . . . . . . . . . . . . . . . . . . . . . . . 2

1.2 Prospects in existing interface scheme . . . . . . . . . . . . . . . . . . . . . . 4

1.3 Project Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2 Magnetic integration and Transformer design 8

2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.2 Proposed multi-winding transformer configuration . . . . . . . . . . . . . . 8

2.2.1 Winding attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.2.2 External capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.3 Equivalent circuit development . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.4 Transfer function analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.5 Core-type and Shell-type Transformers . . . . . . . . . . . . . . . . . . . . . 17

2.5.1 Core-type transformer . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.5.2 Shell type transformer . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.6 Three-winding filter-transformer design . . . . . . . . . . . . . . . . . . . . . 21

v

vi Contents

2.6.1 First pass design procedure . . . . . . . . . . . . . . . . . . . . . . . 26

2.7 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

3 Power circuit for grid interface, sensor and Digital controller 28

3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

3.2 Power Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

3.2.1 Power converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

3.2.2 PWM Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

3.2.3 Power circuit and starting Procedure . . . . . . . . . . . . . . . . . . 32

3.3 Non-isolated Sensor circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

3.3.1 Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

3.3.1.1 Voltage sensor . . . . . . . . . . . . . . . . . . . . . . . . . 33

3.3.1.2 Current sensor . . . . . . . . . . . . . . . . . . . . . . . . . 35

3.4 Digital controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

3.4.1 FPGA board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

3.4.2 ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

3.4.3 DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

3.5 Experimental set-up with digital controller . . . . . . . . . . . . . . . . . . . 38

3.6 Digital implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

3.6.1 Base Values for Various Quantities . . . . . . . . . . . . . . . . . . . 39

3.6.2 Transfer function implementation . . . . . . . . . . . . . . . . . . . . 40

3.6.2.1 Low pass filter . . . . . . . . . . . . . . . . . . . . . . . . . 40

3.6.2.2 PI controller . . . . . . . . . . . . . . . . . . . . . . . . . . 40

3.6.2.3 PR controller . . . . . . . . . . . . . . . . . . . . . . . . . . 41

3.7 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

4 Single phase closed loop control 42

4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

4.2 Grid interactive mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

4.3 Phase Locked Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

4.4 Resonant controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

4.4.1 Proof . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

4.4.2 Testing of resonant controller . . . . . . . . . . . . . . . . . . . . . . 53

Contents vii

4.5 DC bus voltage determination . . . . . . . . . . . . . . . . . . . . . . . . . . 55

4.6 Overall control structure and strategy . . . . . . . . . . . . . . . . . . . . . . 56

4.6.1 Control strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

4.6.1.1 Feed-forward terms . . . . . . . . . . . . . . . . . . . . . . . 58

4.7 Current controller design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

4.8 Voltage controller design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

4.9 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

5 Results and conclusion 61

5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

5.2 Frequency response characteristics . . . . . . . . . . . . . . . . . . . . . . . . 61

5.3 Standalone mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

5.4 Grid interactive mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

5.4.1 Operation as a two-winding transformer . . . . . . . . . . . . . . . . 66

5.4.2 Operation as a three-winding transformer . . . . . . . . . . . . . . . 69

5.5 Harmonic analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

5.6 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

References 83

List of Tables

2.1 Details of core-type test transformer . . . . . . . . . . . . . . . . . . . . . . 18

2.2 Test results of core-type transformer . . . . . . . . . . . . . . . . . . . . . . 20

2.3 Design details of three winding shell-type test transformer . . . . . . . . . . 24

2.4 O.C test results of three winding shell-type transformer . . . . . . . . . . . . 25

2.5 S.C test results of three winding shell-type transformer . . . . . . . . . . . . 25

2.6 Three-winding transformer and its equivalent circuit parameters . . . . . . . 26

2.7 Three-winding transformer and its equivalent circuit parameters . . . . . . . 27

3.1 Details of the Power Converter . . . . . . . . . . . . . . . . . . . . . . . . . . 29

3.2 Design Data for voltage sensor . . . . . . . . . . . . . . . . . . . . . . . . . . 34

3.3 Design Data for current sensor . . . . . . . . . . . . . . . . . . . . . . . . . . 35

3.4 ALTERA FPGA device data . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

3.5 PU values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

3.6 Base values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

4.1 Test system specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

4.2 Rated system specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

4.3 Control loop design data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

5.1 TDD comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

5.2 Comparison of theoretical and practical resonance/anti-resonance frequencies 80

viii

List of Figures

1.1 Typical Grid interface scheme of a Power converter . . . . . . . . . . . . . . 1

1.2 A LCL filter connecting inverter and grid . . . . . . . . . . . . . . . . . . . . 2

1.3 Bode plots for L-filter and LCL filter (with resonance at 1.03kHz) . . . . . . 3

1.4 Control transfer function bode plot (with anti-resonance at 726Hz and reso-

nance at 1.03kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.5 Grid interface through LCL filter and transformer . . . . . . . . . . . . . . . 5

1.6 Integration of L2 into the transformer . . . . . . . . . . . . . . . . . . . . . . 5

1.7 Grid interface through Integrated Magnetic Filter-Transformer . . . . . . . . 6

2.1 Multi-winding transformer configuration . . . . . . . . . . . . . . . . . . . . 9

2.2 Filter-transformer present between inverter and grid . . . . . . . . . . . . . . 9

2.3 Low frequency illustrative equivalent circuit of Filter-transformer . . . . . . 10

2.4 High frequency illustrative equivalent circuit of Filter-transformer . . . . . . 10

2.5 Primary side of non-ideal filter-transformer at high frequencies . . . . . . . . 11

2.6 Equivalent circuit of Two-winding transformer . . . . . . . . . . . . . . . . . 12

2.7 A Three-winding transformer . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.8 Equivalent circuit of Three-winding transformer . . . . . . . . . . . . . . . . 13

2.9 Proposed winding structure of Filter-transformer . . . . . . . . . . . . . . . 14

2.10 Equivalent circuit of Filter-transformer . . . . . . . . . . . . . . . . . . . . . 15

2.11 Equivalent circuit with secondary shorted . . . . . . . . . . . . . . . . . . . . 15

2.12 MagNet simulation of core-type transformer . . . . . . . . . . . . . . . . . . 19

2.13 MagNet simulation of shell-type transformer . . . . . . . . . . . . . . . . . . 19

2.14 Core-type test prototype . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.15 Shell-type test transformer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

ix

x List of Figures

2.16 (a)Leakage field with equivalent height; (b) MMF variation [Ref.[18]] . . . . 22

2.17 3kVA three-winding filter-transformer test prototype . . . . . . . . . . . . . 23

2.18 Filter-transformer geometry . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.1 Carrier and references in unipolar PWM technique . . . . . . . . . . . . . . 29

3.2 Actual output voltage with unipolar switching scheme along with its funda-

mental . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3.3 Actual output voltage with bipolar switching scheme along with its fundamental 30

3.4 DC bus Common-mode voltage with transformer’s primary neutral earthed . 31

3.5 DC bus Common-mode voltage with transformer’s primary neutral unearthed 31

3.6 Actual DC bus voltage and the sensed DC bus voltage . . . . . . . . . . . . 32

3.7 Power Circuit with filter-transformer . . . . . . . . . . . . . . . . . . . . . . 32

3.8 DC bus voltage profile during pre-charging . . . . . . . . . . . . . . . . . . . 33

3.9 Non-isolated voltage sensor circuit . . . . . . . . . . . . . . . . . . . . . . . . 34

3.10 Current sensor circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

3.11 Block diagram of FPGA board . . . . . . . . . . . . . . . . . . . . . . . . . 36

3.12 Experimental set-up with digital controller . . . . . . . . . . . . . . . . . . . 38

3.13 Resonant controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

4.1 Scheme for power transfer between two active sources . . . . . . . . . . . . . 42

4.2 A three phase PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

4.3 Phasor diagram for grid voltage alignment . . . . . . . . . . . . . . . . . . . 45

4.4 A general single phase PLL structure . . . . . . . . . . . . . . . . . . . . . . 46

4.5 Resonant controller based orthogonal vector generation . . . . . . . . . . . . 46

4.6 Bode plot forVph(s)

Vg(s). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

4.7 Bode plot forV′qd(s)

Vg(s). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

4.8 Simulated response of V′qd and Vph for a DC offset in grid voltage . . . . . . . 48

4.9 Grid voltage [CH1(Yellow)] and unit vectors [CH4(Green) and CH3(Pink)]

when PLL is enebled [CH2(Blue)] . . . . . . . . . . . . . . . . . . . . . . . . 49

4.10 Unit vectors [CH4(Green) and CH3(Pink)] and grid voltage [CH1(Yellow)] at

steady state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

4.11 In-phase unit vector [CH4(Green)] when there is a sudden dip in grid voltage

[CH3(Pink)]; CH2(Blue): Enable signal . . . . . . . . . . . . . . . . . . . . . 50

List of Figures xi

4.12 In-phase unit vector [CH4(Green)] with DC offset in grid voltage [CH3(Pink)] 50

4.13 A resonant controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

4.14 Bode plot of resonant controller (with resonance at 50Hz . . . . . . . . . . . 51

4.15 A simple control system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

4.16 Error function comparison for a reference of 10A through simulation . . . . . 54

4.17 Output current[CH3(Pink)] with PR current controller for a reference of 10A;

CH4(Green): Reference; CH3(Blue): Feedback . . . . . . . . . . . . . . . . . 54

4.18 Bode plot for a PR controller set to track 50Hz reference . . . . . . . . . . . 55

4.19 Phasor diagram for DC bus voltage evaluation . . . . . . . . . . . . . . . . . 56

4.20 Overall control structure for single phase AFEC/STATCOM . . . . . . . . . 57

4.21 Current control loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

4.22 Voltage control loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

5.1 Simulated frequency response of O.C secondary voltage (Vs(s)) to primary

voltage (Vi(s)) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

5.2 Measured frequency response for O.C secondary voltage (Vs(s)) to primary

voltage (Vi(s)) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

5.3 Simulated frequency response of injected grig current to inverter voltage ( Ig(s)Vi(s)

)

with Vg = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

5.4 Measured frequency response of injected grig current to inverter voltage ( Ig(s)Vi(s)

)

with Vg = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

5.5 Simulated frequency response of inverter current to inverter voltage ( Ii(s)Vi(s)

)

with Vg = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

5.6 Measured frequency response of inverter current to inverter voltage ( Ii(s)Vi(s)

)

with Vg = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

5.7 CH1(Yellow):Applied primary (inverter) voltage; CH2(Blue): Secondary (out-

put) voltage; Without AW . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

5.8 CH1(Yellow): Primary voltage; CH2(Blue): Secondary voltage; With AW . 65

5.9 CH1(Yellow,1A/div): Grid current; CH2(Blue,0.1A/div): Inverter current;

CH3(Pink): Sensed grid voltage; With control not enabled . . . . . . . . 66

5.10 CH1(Yellow,50V/div): DC bus voltage boost profile; CH2(Blue): Enable signal 67

5.11 CH1(Yellow,2A/div): Grid current; CH2(Blue,5A/div): Inverter current; CH4(Green):

Grid unit vector; with control enabled, 0A reference . . . . . . . . . . . 67

xii List of Figures

5.12 CH2(Blue,5A/div): Inverter current; CH4(Green,2V/div): Grid unit vector;

In STATCOM mode at 90% load . . . . . . . . . . . . . . . . . . . . . . 68

5.13 CH1(Yellow,5A/div): Grid current; CH4(Green,2V/div): Grid unit vector;

In STATCOM mode at 90% load . . . . . . . . . . . . . . . . . . . . . . 68

5.14 CH1(Yellow,50V/div): DC bus voltage boost profile; CH2(Blue): Enable signal 69

5.15 CH1(Yellow,2A/div): Capacitor current; CH2(Blue,2A/div): Inverter cur-

rent; CH3(Pink): Sensed grid voltage; with control enabled, 0A reference 70

5.16 CH1(Yellow,2A/div): Grid current; CH2(Blue,5A/div): Inverter current; CH4(Green):

Grid unit vector; with control enabled, 0A reference . . . . . . . . . . . 70

5.17 CH1(Yellow,50V/div): DC bus voltage ripple; CH2(Blue,5A/div): Grid cur-

rent; CH3(Pink,5A/div): Inverter current; CH4(Green,2V/div): Grid unit

vector; with control enabled, 80 % load . . . . . . . . . . . . . . . . . . 71

5.18 CH1(Yellow,50V/div): DC bus voltage ripple profile; CH3(Pink): Enable sig-

nal for Current reference change from 25% to 90% . . . . . . . . . . . 71


with control enabled, 90% current reference at 0 p.f (leading) . . . . 72


with control enabled, 90% current reference at 0 p.f (leading) . . . . 72


with control enabled, 90% current reference at 0 p.f (lagging) . . . . 73


with control enabled, 90% current reference at 0 p.f (lagging) . . . . 73


with control enabled, AFEC UPF operation . . . . . . . . . . . . . . . 74


with control enabled, AFEC UPF operation . . . . . . . . . . . . . . . 74


with control enabled, AFEC operation with 10% reactive (leading)

current reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75


with control enabled, AFEC operation with 10% reactive (leading) cur-

rent reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

5.27 Inverter current under two-winding operation . . . . . . . . . . . . . . . . . 76

List of Figures xiii

5.28 Inverter current harmonics under two-winding operation . . . . . . . . . . . 77

5.29 Grid current under two-winding operation . . . . . . . . . . . . . . . . . . . 77

5.30 Grid current harmonics under two-winding operation . . . . . . . . . . . . . 78

5.31 Inverter current under three-winding operation . . . . . . . . . . . . . . . . . 78

5.32 Inverter current harmonics under three-winding operation . . . . . . . . . . . 79

5.33 Grid current under three-winding operation . . . . . . . . . . . . . . . . . . 79

5.34 Grid current harmonics under three-winding operation . . . . . . . . . . . . 80

Chapter 1

Introduction

Now a days, several governments and utilities worldwide promote renewable energy sources

such as Photovolaics (PV), Fuel cells, micro-turbines etc for distributed power generation

systems(DGPS), so as to deal with issues like rising prices of energy and environmental

concerns. DGPS are renewable energy sources linked up to the grid at the point of load.

This eliminates losses during transmission and distribution and also improves reliability of

the power supply. However, a DC/AC power converter and a filter are invariably required

for such an interconnection. Fig.1.1 shows a typical interface scheme of a DGPS. The power

quality of the grid interface is influenced by the quality of the injected current and the filter

here essentially brings down the distortion in the sinusoidal current and voltage waveforms

caused by the power converter.

Figure 1.1: Typical Grid interface scheme of a Power converter

1

2 Chapter 1. Introduction

1.1 Current Scenario

The conventional way of interface is through a simple first order L-filter whose design is

merely based on 10% filter drop. But then, it is bulky, inefficient and cannot meet the regu-

latory requirements such as IEEE512-1992 and IEEE1547-2003 pertaining to interconnection

of harmonic loads to the grid. Making it satisfy the standards would render it vast.

Higher order filters (such as LC and LCL filters) are becoming exceedingly popular (es-

pecially at higher power levels) as they offer higher attenuation even at lower switching

frequency for a similar filter size [1]. For a grid application, LC-filter is no better than a

L-filter as the grid which is present across capacitor would make its presence futile [23].

So,third order LCL filter is the next available option.

1.1.1 Higher order filter design

Figure 1.2: A LCL filter connecting inverter and grid

LCL-filter design methodologies have been well reported in the literature. The method

adopted here is based on per-unit values [23]. The transfer function pertinent to our design

procedure is given by,

ig(s)

vi(s)

∣∣∣∣∣vg=0

=1

s(L1 + L2)(s2L1L2

L1+L2C + 1)

(1.1)

It can be seen that the filter has a resonant frequency ωres given by,

ω2res =

1

LpC(1.2)

1.1. Current Scenario 3

where,

Lp =L1L2

L1 + L2

(1.3)

With L = L1 + L2 and aL = L1

L2, Equation1.1 becomes,

ig(s)

vi(s)

∣∣∣∣∣vg=0

=1

sL(s2LpC + 1)(1.4)

Figure 1.3: Bode plots for L-filter and LCL filter (with resonance at 1.03kHz)

On per-unitization with suitable base quantities [23], the resonant frequency becomes,

ω2res(pu) =

1

CpuLpuaL

(aL+1)2

(1.5)

Choice of ωres(pu) is based on the available system bandwidth. To find Lpu and Cpu, Equation.(1.4)

is evaluated (in per unit) at switching frequency fsw.∣∣∣∣∣ ig(jωsw)

vi(jωsw)

∣∣∣∣∣ =1

|−jω3swL1L2C + jωsw(L1 + L2)|

(1.6)

ig(jωsw) is the switching ripple current at the point of common coupling to the grid at

switching frequency. This is guided by the recommendations of IEEE 519-1992 or IEEE

1547.2-2008 standard.


Equation.(1.6) is solved by converting all parameters to per-unit and substituting Equation.(1.5)

in Eq (1.6).

Lpu =1

ωsw(pu)

∣∣∣∣∣ ig(pu)vi(pu)

∣∣∣∣∣1∣∣∣∣∣∣1− ω2sw(pu)

ω2res(pu)

∣∣∣∣∣∣(1.7)

Then, Cpu will be calculated from Equation.1.5.

Another transfer function of interest from control perspective is,

ii(s)

vi(s)

∣∣∣∣∣vg=0

=1

sL

(s2L2C + 1)

(s2LpC + 1)(1.8)

This would be the filter transfer function considered for closed loop controller design and

Figure 1.4: Control transfer function bode plot (with anti-resonance at 726Hz and resonance

at 1.03kHz)

the inverter current ii will be the one to be controlled by the regulator. The issue of res-

onance arising in higher order filters and their damping techniques are not discussed here.

Conventional resistive (passive) damping is employed in this work.

1.2 Prospects in existing interface scheme

Many a times, a transformer would be necessary after the filter stage to enable grid interface.

The transformer provides galvanic isolation and an extra degree of freedom to adjust the

1.2. Prospects in existing interface scheme 5

output voltage level to that of the grid. It must be noted that the copper used in filter as

well as the transformer must be gauged for the rated current. Again, magnetic materials are

to be used in both the filter and the transformer.

Figure 1.5: Grid interface through LCL filter and transformer

Magnetic components often constitute a significant part of the overall size, weight and cost

of the grid connected power system. Hence a compact and inexpensive design is desirable.

Since magnetic components are present in both filter and transformer, there is scope for their

potential integration.

It is quite straight forward to integrate the magnetics of a simple L-filter into the trans-

former. All that is required is to design a transformer with a value of leakage inductance

equal to that of the actual filter inductance. Such a design is relatively simple as the typical

values of leakage inductance and the filter inductance are quite close on a per-unit basis.

Figure 1.6: Integration of L2 into the transformer

While it is not conspicuous to achieve such a magnetic integration in case of higher


order LCL filters. One possible way is integrating only one of the two filter inductances

into the transformer as illustrated in Fig. 1.6. But this does not serve the purpose (of

magnetic integration) entirely. It is required to integrate all the magnetics of the filter

into the transformer.Typical ways entail complicated design procedures with sophisticated

winding and core structures which are hard to procure.

1.3 Project Work

The present work is on design of an integrated filter-transformer structure where the all

magnetic components of the higher order filter are integrated into the transformer. A three

winding transformer configuration is proposed which employs standard core structures for

achieving such an integration. The single compact structure would now perform the functions

of both the filter and the transformer. It will be seen that with a judicious design, the non-

idealities viz. leakage inductances of the transformer can be exploited for our advantage for

the purpose of integration. Such a design economizes both copper and iron, while yielding a

compact design.

Figure 1.7: Grid interface through Integrated Magnetic Filter-Transformer

This work targets single phase applications and control in d-q domain is thus not possible.

This makes the closure of control loop rather tricky. References are no longer DC in nature.

Using a conventional PI controller would result in significant steady state errors depending on

the bandwidth of the system. Hence, focus is laid on Proportional-Resonant (PR) controllers

required for accurate AC reference tracking in closed loop control.

1.4. Conclusion 7

A PI controller’s transfer function is given by:

H(s) = Kp +Ki

s(1.9)

While a PR controller’s transfer function is given by:

H(s) = Kp +Kis

s2 + ω20

(1.10)

As seen from (4.13), a resonant controller is a generalised integrator. PI controller is a special

case of PR controller when ω0 is set to zero. Thus, a PR controller can be suitably set to

track AC signal of any frequency, which is well suited for single phase applications.

The power converter is operated as a single phase STATCOM and as a Active Front End

Converter (AFEC) in the grid interactive mode for performance evaluation. Also, a heat run

test was performed to get a fair idea of the possible temperature rise of core and copper.

1.4 Conclusion

An outline of the project was given in this chapter. A brief description about the about the

intended magnetic integration of filter into the transformer and the complexity in controlling

single phase systems was given.

Chapter 2

Magnetic integration and Transformer

design

2.1 Introduction

In the foregoing chapter, it was seen that magnetic components are present in both filter

and the transformer of the grid interface scheme, and hence there is a possibility to integrate

them. The methods available in literature for integration of LCL filter and transformer

involve cumbersome design procedures with sophisticated core structures [2],[3]. Such un-

conventional core structures are hard to manufacture and procure.

In this work, a multi-winding transformer configuration is proposed that employs con-

ventional C-core structures to achieve the desired integration.

2.2 Proposed multi-winding transformer configuration

The multi-winding structure that is intended to emulate a LCL-filter is depicted in Fig.2.1.

The structure consists of two primary windings and one secondary winding which are mag-

netically coupled by the core. The two primaries are of the same number of turns. One

primary acts as the main winding (MW) and the other is called the auxiliary winding (AW).

A capacitor (C) is externally connected to AW as shown. The primary side will be connected

to the inverter and the secondary winding (SW) will be connected to gird.

It must be noted that the two primaries are wound in opposite sense (opposite dots) over

the core. This is key feature that forms the basis of magnetic integration.

8

2.2. Proposed multi-winding transformer configuration 9

Figure 2.1: Multi-winding transformer configuration

Figure 2.2: Filter-transformer present between inverter and grid

10 Chapter 2. Magnetic integration and Transformer design

Working principle

At low frequencies (including power frequency), the capacitor acts a open circuit due to its

very large impedance. In this situation, the AW is as good as being absent. Now, power

frequency component of the inverter voltage will see only the MW. Subsequently energy

transfer takes place to the secondary and hence to the grid.

Figure 2.3: Low frequency illustrative equivalent circuit of Filter-transformer

At higher frequencies (inclusive of switching frequencies), the capacitor acts as a short

as it going to offer very low impedance. Under this condition, the two primaries work in

conjunction with applied voltage (Vi) being common to both. Due to their opposite sense

of winding, the flux produces by each winding are opposite in direction, hence cancel one

another. So for high frequency components, flux gets completely cancelled in the core. Thus

no energy transfer takes place to the secondary now due to the absence of any magnetic

field in the core. In other words, there is no magnetic coupling between MW and SW at

those frequencies. This would amount to filtering of all high frequency components (which are

responsible for distortion) other than the fundamental, present in the inverter output voltage.

Figure 2.4: High frequency illustrative equivalent circuit of Filter-transformer

2.2. Proposed multi-winding transformer configuration 11

Figure 2.5: Primary side of non-ideal filter-transformer at high frequencies

This phenomenon is referred to as internal differential mode distortion cancellation [7].

But the pitfall here is that the inverter is ideally going to see a dead-short across the primary

side, since due to flux cancellation, no induced emf is produced across the magnetizing

inductance. Fortunately due to non-idealities, leakage inductances are present to limit the

current from the inverter.

2.2.1 Winding attributes

• Main winding (MW):

It works at high frequencies as well as low frequencies and thus carries both fundamental

and switching ripple current. Hence, an appropriate thick gauge is required depending

on the rated fundamental current and desired switching ripple current.

• Secondary winding (SW):

It again works at high frequencies as well as low frequencies but carries fundamental

and the filtered switching ripple current. An appropriate thick gauge is again required.

• Auxiliary winding (AW):

It functions only at high frequencies and thus carries only switching ripple current.

Hence a suitable thin gauge (depending on the desired switching ripple current) would

suffice.


2.2.2 External capacitor

Metallised Polypropylene capacitors are AC capacitors that are especially designed for high

frequency current operation. These capacitors are constructed from polypropylene films on

which an extremely thin metal layer is vaccum deposited. Several such layers are wound

together in a tubular fashion to get higher capacitance.

Metallised film capacitors are characterized by small size, wide operating frequency range,

low losses, low to medium pulse handling capabilities, low parasitic impedances and self-

healing. In regular film-foil capacitors, if the electrode foils of opposite potential are exposed

to each other because of wearing away of the dielectric, the foils will short and the capac-

itor will be destroyed. But in case of metallised polypropylene capacitors, because of the

extremely thin metal layer, the contact points at the fault area are vaporised by the high

energy density, and the insulation between foils is maintained. Due to the above reasons,

these capacitors are perfectly suited for grid connected filter operation [23].

2.3 Equivalent circuit development

Leakage inductance is always defined for a pair of windings [16]. In case of a conventional two-

winding transformer, the meaning of leakage inductance and the corresponding equivalent

circuit are straightforward [17].

Figure 2.6: Equivalent circuit of Two-winding transformer

where, L12 is the total leakage inductance between the two windings. This value can be

experimentally obtained by performing short circuit test. Whereas in case of a multi-winding

transformer, since there are multiple pairs of windings, leakage inductance must be defined

for every pair. Equivalent circuit now would not be as simple as that of a two-winding case.

2.3. Equivalent circuit development 13

Figure 2.7: A Three-winding transformer

Figure 2.8: Equivalent circuit of Three-winding transformer

Fig.2.8 shows the equivalent circuit of a three-winding transformer.

Here, we have a set of three (different) leakage inductances as there are three pairs

of windings. And LI ,LII and LIII shown in Fig.2.8 are composite inductances formed by

linear combinations of different leakage inductances [17]. It is first necessary to evaluate

the composite inductances before we go about analysing the transfer function. A rigorous

derivation for the composite inductances is available in literature [16], [17]. For brevity, end

is result is being used here, which is given by,

LI =L12 + L13 − L23

2(2.1)

LII =L21 + L23 − L13

2(2.2)

LIII =L31 + L32 − L21

2(2.3)


where,

L12 = L21 = leakage inductance of windings 1 and 2 with winding 3 open.



These leakage inductances can be measures by performing multiple short-circuit tests

with pertinent windings. It must be noted that winding resistances have been disregarded

here for simplicity.

2.4 Transfer function analysis

Figure 2.9: Proposed winding structure of Filter-transformer

The proposed structure is shown in Fig.2.9. The corresponding equivalent circuit is

shown in Fig.2.10 This equivalent circuit conveniently models the opposite winding sense

of the auxiliary winding by reversing its applied (inverter) voltage. The voltage across

the magnetizing inductance essentially represents the open circuit voltage produced in the

secondary due to the net flux present in the core. The first transfer function of interest is

that of the secondary voltage e(s) to primary voltage Vi(s) which can be obtained easily

using superposition theorem. Shunt branch consisting of magnetizing impedance of the

transformer (which is very large) can be opened up for simplicity in the analysis.

e(s) = vi(s)

(sLIII + 1

sC

sLI + sLIII + 1sC

)+ (−vi(s))

(sLI

sLI + sLIII + 1sC

)(2.4)

=⇒ e(s)

vi(s)=

(sLIII + 1sC− sLI)

(sLIII + sLI + 1sC

)(2.5)

which yields,e(s)

vi(s)=

(1 + (LIII − LI)Cs2

1 + (LIII + LI)Cs2

)(2.6)

2.4. Transfer function analysis 15

Figure 2.10: Equivalent circuit of Filter-transformer

The next transfer function of interest is that of the shorted circuited secondary current

Is(s) to inverter voltage vi(s). It should be noted that the grid voltage is a short for all

frequency components except the fundamental. So, Is(s) essentially represents the injected

grid current. Once again, superposition theorem can be employed to evaluate short-circuited

secondary current.

Figure 2.11: Equivalent circuit with secondary shorted


Is = Is1 − Is2 (2.7)

From Fig.2.11(b),

Is1(s) =vi(s)(

sLI +sLII(sLIII+ 1

sC )sLII+sLIII+

1sC

) × ( sLIII + 1sC

sLIII + sLII + 1sC

)(2.8)

On simplification,

Is1(s) = vi(s)

1 + LIIICs2

s(LI + LII)[(LILII+LIILIII+LIIILI

LI+LII)Cs2 + 1]

(2.9)

Similarly, from Fig.2.11(c),

Is2 = vi(s)

1

s(LIII + LILII

LI+LII

)+ 1

sC

( LILI + LII

)(2.10)

On simplification,

Is2 = vi(s)

sC LILI+LII

[(LILII+LIILIII+LIIILILI+LII

)Cs2 + 1]

(2.11)

Substituting Equation.2.9 and Equation.2.11 in Equation.2.7, we get,

Is(s) = vi(s)

1 + LIIICs2


LI+LII)Cs2 + 1]

−vi(s)

sC LILI+LII

[(LILII+LIILIII+LIIILILI+LII

)Cs2 + 1]

(2.12)

which yields,

Is(s)

vi(s)=

1

s(LI + LII)

1 + (LIII − LI)Cs2

(LILII + LIILIII + LIIILI

LI + LII)Cs2 + 1

(2.13)

Equation.2.13 is the required transfer function that governs the injected grid current. The

term outside the braces represents the injected grid current transfer function for a conven-

tional two-winding transformer. The term inside the braces represents the correction factor

introduced by the third winding (AW) to the otherwise two-winding transformer.

2.5. Core-type and Shell-type Transformers 17

It can be surmised that the proposed structure cannot emulate a LCL-filter entirely. It

behaves as a LCL-filter until the entry of the zeros, after which it becomes a first order

L-filter.

The final transfer function of interest is that of the inverter current Ii(s) to inverter voltage

vi(s). This is the control transfer function necessary for closed loop control. From Fig.2.11(a),

the actual inverter current is given by,

Ii(s) = Ix(s) + Iy(s) (2.14)

Ix(s) and Iy(s) are readily evaluated using superposition theorem.

Ix(s) = vi(s)

1 + (2LII + LIII)Cs2


LI+LII)Cs2 + 1]

(2.15)

Similarly,

Iy(s) = vi(s)(

LIILI + LII

) sC

(LILII+LIILIII+LIIILILI+LII

)Cs2 + 1

(2.16)

Therefore,

Ii(s) = vi(s)

1 + (2LII + LIII)Cs2 +

(sC + LII

LI+LII

)s(LI + LII)


LI+LII)Cs2 + 1]

(2.17)

which finally yields,

Ii(s)

vi(s)=

1

s(LI + LII)

1 + (LI + 4LII + LIII)Cs

2

(LILII + LIILIII + LIIILI

LI + LII)Cs2 + 1

(2.18)

Equation.2.18 would be the filter-transformer’s transfer function from control perspective.

Here again, the term inside the braces represents the correction factor introduced by the

third winding. It can be seen that without the third winding, the behaviour of the structure

is similar to that of a simple L-filter.

2.5 Core-type and Shell-type Transformers

As seen in the preceding section, leakage inductances of the filter-transformer governed the

nature of the relevant transfer functions. It may so happen that a large value of leakage

inductance is required to get the required attenuation of switching ripple current. So, a

judicious choice on the type of transformer to be used was essential.


2.5.1 Core-type transformer

Core-type transformers are known to have relatively larger leakage inductances as compared

to their shell-type counterparts of similar rating [5]. To verify this, a core-type test trans-

former was built. The core-type test prototype and a shell-type transformer of identical

ITEM SPECIFICATION

VA 600VA

Vp, Vs 120V, 120V

Ip, Is 5A, 5A

Np, Ns 580, 580

Bm 1.5T

J 2.5A/mm2

kw 0.6

f 50Hz

Inter-winding gap (Wg) 1.1 cm

Core Amorphous AMCC367’s

Table 2.1: Details of core-type test transformer

rating were simulated in Infolytica MagNet 6.22.1, so as to have a fair idea of path of leakage

flux flow in either case and to obtain the corresponding leakage inductances. As seen in

from Fig.2.12, leakage flux of a core type transformer exists both inside and outside the

transformer. In contrast, for a shell type, it exists only inside the transformer. For a core

type transformer, leakage inductance is three independent parts, one inside it and two out-

side [6]. For a shell type transformer, only the inside component of leakage inductance exists.

Analytical evaluation of leakage inductance of shell type transformer is well reported in lit-

erature [5], [18]. But for core-type ones, materials on its leakage inductance were not readily

available.

Open circuit and short circuit tests were performed on the prototype and Table.2.2 lists

the results. L12 value obtained from simulation differed significantly from the practical value

for the core-type transformer. Also,the prototype was found to have more than 1 p.u leakage

inductance, which is entirely undesirable. So, further analysis was ceased and focus was laid

2.5. Core-type and Shell-type Transformers 19

Figure 2.12: MagNet simulation of core-type transformer

Figure 2.13: MagNet simulation of shell-type transformer


Figure 2.14: Core-type test prototype

Quantity Value

Magnetizing inductance (LM) 1.6H

Leakage inductance L12 (measured) 90mH

Leakage inductance L12 (from MagNet) 5mH

Leakage impedance Xl 28Ω

Base impedance Zb 24Ω

p.u Leakage impedance Xl(pu) 1.17p.u

Short circuit current Is.c at rated voltage 4.3A

Table 2.2: Test results of core-type transformer

on shell type transformers.

2.5.2 Shell type transformer

Shell type transformers are extensively discussed in literature. Analytical expression for its

leakage inductance is also readily available with rigorous proof via different approaches [17],

[18]. It is given by Rogowski’s formula (Equation.2.19). Fig.2.15 and Fig.2.16 show the

basic construct of a shell type transformer and the corresponding leakage flux existing in it

respectively.

Ll12 = µoN2

Heq

π[1

3(T1Dw1 + T2Dw2) + TgDwg

](2.19)

2.6. Three-winding filter-transformer design 21

Figure 2.15: Shell-type test transformer

with,

Heq =Hw

kR(2.20)

kR = 1− 1− ε−πHwλπHwλ

(2.21)

λ = T1 + T2 + Tg (2.22)

where,

T1 and T2 = Winding widths of LV and HV windings respectively,

Tg = Inter-winding distance,

Dw1, Dw2 and Dwg = Mean diameter of LV, HV and inter-winding gap respectively,

N = Number of turns.

Hw = Height of the winding,

kR = Rogowski factor

The above calculation is for a two-winding case. Even in three-winding case, same approach

is applicable for leakage inductance evaluation for every pair of windings.

2.6 Three-winding filter-transformer design

In order to verify the transfer functions obtained for the proposed structure, a three winding

test transformer was built as a first pass iteration. Conventional area-product approach was


Figure 2.16: (a)Leakage field with equivalent height; (b) MMF variation [Ref.[18]]

employed for the design [22]. The structure’s geometry is illustrated in Fig.2.18

Open circuit and short circuit tests were performed on the structure and the pertinent

parameters were evaluated from the measurement data in Table.(2.5) and (2.4). Using the

parameters from these measurements, relevant transfer functions can be obtained.


Figure 2.17: 3kVA three-winding filter-transformer test prototype


ITEM SPECIFICATION

VA 3kVA

VMW , VSW 240V, 240V

IMW , ISW 12.5A, 12.5A(SWG12)

IAW 1.6A(SWG20)

NMW , NSW , NAW 225, 225, 225

Bm 1.28T

J 2.5A/mm2

kw 0.656

f 50Hz

Core type Amorphous AMCC367’s

Table 2.3: Design details of three winding shell-type test transformer

Figure 2.18: Filter-transformer geometry


Quantity Value

Vin(rms) 240V

I0(rms) 1.77A

P 11W

Q 423.8V AR

LM 0.427H

R0 5.13kΩ

Table 2.4: O.C test results of three winding shell-type transformer

Quantity/Condition MW excited; SW excited; AW excited;

SW shorted; AW shorted; MW shorted;

AW opened; MW opened; SW opened;

Vin(rms) 16.81V 6.13V 7.76V

Is.c(rms) 12.538A 1.551A 1.643A

Zs.c 1.34Ω 3.9522Ω 4.723Ω

P 99W 9W 10W

Q 186VAR 3VAR 8VAR

Table 2.5: S.C test results of three winding shell-type transformer

In general, the transfer function of the structure (from Equation.2.13) governing the

injected grid current can be written as,

Ig(s)

vi(s)=

1

sLT

s2

ω2zg

+ 1

s2

ω2p

+ 1

(2.23)

Similarly the control transfer function (from Equation.2.18) can be written as,

Ii(s)

vi(s)=

1

sLT

s2

ω2zc

+ 1

s2

ω2p

+ 1

(2.24)


Quantity Value

RMW 0.3Ω

RSW 0.3Ω

RAW 3.6Ω

L12 3.77mH

L23 4mH

L31 9.32mH

LI 4.545mH

LII -0.775mH

LIII 4.775mH

Table 2.6: Three-winding transformer and its equivalent circuit parameters

It can be seen that the control transfer function of the proposed structure is strikingly similar

to that of a discrete LCL-filter (obtained in chapter 1), even though the integrated structure

does not emulate a LCL-filter completely from grid current perspective. So, control strategy

is same as that of a discrete filter. The above transfer functions for the three winding test

transformer can be obtained by plugging in the parameter values furnished in Table.2.6.

2.6.1 First pass design procedure

It was desired to verify if the conceived idea would work. So the test prototype was not

designed based on a concrete design procedure. The primary (MW) and the secondary

windings (SW) were designed based on area-product approach with the available amorphous

core structures. Since these two windings are responsible for 50Hz power transformer, they

were wound concentrically as close as possible so as to have minimum leakage inductance.

Now, the desired transfer function must be achieved by placing the third winding (AW)

adequately away from the two windings. To begin with, it was placed at a distance of 2mm

away from the SW.

Now, leakage inductances of various winding pairs were measured and subsequently com-

posite inductances were obtained. From these values and the desired location of zeros (which

causes a valley) in Is(s)vi(s)

(Equation.2.13, 2.23), the capacitance value was chosen.

2.7. Conclusion 27

Quantity Value

ωzg 125663.7 rad/s

fzg 20kHz

Lzg 0.23mH

C 0.25µF

Table 2.7: Three-winding transformer and its equivalent circuit parameters

2.7 Conclusion

A three winding transformer configuration along with a capacitor was proposed for the

purpose of magnetically integrating a higher order filter into a transformer. Its equivalent

circuit was developed and relevant transfer functions were obtained. Core-type transformers

were found to be unsuitable for this application. A first pass design of the structure was

done. Experimental results verifying the transfer functions and performance of the structure

as a filter-transformer would be furnished in final chapter.

Chapter 3

Power circuit for grid interface, sensor

and Digital controller

3.1 Introduction

This chapter furnishes all the hardware details associated with the power converter employed

for this work. The converter was designed and built in the past. The grid interfacing

scheme with the filter-transformer is illustrated and the corresponding starting procedure

is described. Non-isolated sensor circuit design is discussed. Details pertaining to FPGA

based digital controller and implementation techniques are also furnished.

3.2 Power Circuit

3.2.1 Power converter

A 10 kVA three phase, two-level power converter is being operated as a 3 kVA single phase

converter in H bridge configuration. The Protection-Delay card, Gate-Drive card and the

annunciation card form the control cards of the inverter whose design existed beforehand.

The cards were tested sequentially for their working. Specifications of the converter are

furnished in Table. 3.1.

3.2.2 PWM Technique

Unipolar PWM technique is employed where each of the leg is switched at switching frequency

fs using sine-triangle comparison method and the output voltage of the converter is the

difference between the pole voltage of either legs. Fig. 3.1 depicts the reference sine for each

28

3.2. Power Circuit 29

ITEM SPECIFICATION

IGBT SKM100GB123D

CDC 2350µF

CAC 1µF

VDC(rated) 750V

IAC(rated) 100A

Bleeder Resistor 20kΩ

Power 10 kVA

Table 3.1: Details of the Power Converter

of the leg in this scheme. In this scheme, for a given polarity of the output funfamental,

Figure 3.1: Carrier and references in unipolar PWM technique

the actual output voltage switches between zero and a voltage (here ±VDC) of identical

polarity as the fundamental. The clear-cut advantage with unipolar switching scheme is

that only even switching frequency harmonics (2fs, 4fs...) and their associated side-bands

exist in the output waveform. This means the output voltage waveform is of better quality

when compared to that obtained with bipolar switching scheme [19]. In bipolar scheme, the

polarity of the output fundamental and the switching output voltage may be opposite as well

and the output waveform has both even and odd switching frequency harmonics along with

their side-bands (1fs, 2fs, 3fs...). Thus, with unipolar scheme, burden on the output filter

30 Chapter 3. Power circuit for grid interface, sensor and Digital controller

is reduced. Another benefit with H-bridge topology is that burden on the DC bus voltage

is only 50% of that with single leg topology for a given output voltage fundamental. This

is because the peak output fundamental with H-bridge is Vdc and not Vdc2

as with single leg

topology [19] .

Figure 3.2: Actual output voltage with unipolar switching scheme along with its fundamental

Figure 3.3: Actual output voltage with bipolar switching scheme along with its fundamental

Fig. 3.2 and Fig. 3.3 show the actual output voltage along with its fundamental for

unipolar and bipolar technique respectively.

One drawback of these methods in grid interactive mode is that the common mode voltage

of the positive and negative rails is going to contain switching frequency components (fs),

3.2. Power Circuit 31

which get reflected in the voltage sensor output as noise riding on the actual DC bus voltage.

This may be attributed to the inability of sensor to filter the common-mode noise entirely.

This is the case when the neutral of the filter-transformer is earthed. In the unearthed

case, since the neutral itself is going to see a common-mode voltage at 50 Hz, the DC bus

common-mode voltage (Vcm) has both switching frequency and 50 Hz component.

Figure 3.4: DC bus Common-mode voltage with transformer’s primary neutral earthed

Figure 3.5: DC bus Common-mode voltage with transformer’s primary neutral unearthed

As a result, further filtering of sensed DC bus voltage is necessary. This may add to

the delay in the feedback. One possible way to deal with this sort of common-mode voltage

is to switch only one leg at fs and the other (connected to the neutral) at 50 Hz. Now,


Figure 3.6: Actual DC bus voltage and the sensed DC bus voltage

common-mode noise consists only a mild 50 Hz component. It is still a unipolar technique

but the references to each leg are different now.

3.2.3 Power circuit and starting Procedure

Pre-charging is done through the diode devices of the IGBT module through a 1kΩ pre-

charging resistor as shown in Fig. 3.7. When the DC bus voltage reaches a preset value

(V′dc), the pre-charging resistor is shorted by a contactor. Subsequently, DC bus voltage is

boosted to the rated value when the control is enabled. The transformer does not possess

a mechanically robust construct as it is self made. This makes its acoustic behaviour (due

to magnetostriction) considerably poor. To keep the humming noise low, the grid voltage is

stepped down by 10% of its rated value through an autotransformer and then used.

Figure 3.7: Power Circuit with filter-transformer

3.3. Non-isolated Sensor circuit 33

Figure 3.8: DC bus voltage profile during pre-charging

As seen in Fig. 3.8, the DC bus starts charging once the grid voltage is applied and when

the preset value is reached, it abruptly jumps to the grid voltage peak due to the closure of

the contactor.

3.3 Non-isolated Sensor circuit

The existing sensing cards incorporated isolation between the input and output through an

opto-isolater. The design employs a forward converter on board that acts as the isolated

power supply meant for the opto-isolater. Output of the opto-isolator was amplified using a

differential amplifier. 555-Timer was used to generate 50% duty ratio pulses for the forward

converter. Passive R-C based flux reset circuit was employed. These together make the

design more or less complicated and hence less reliable. Moreover, isolation is not mandatory

for sensing. Thus, a non-isolated sensing card was designed that employs just a potential

divider and a differential amplifier to serve the purpose. Noise filter is incorporated in the

differential amplifier itself. The circuit is both simple and more reliable.

3.3.1 Design

3.3.1.1 Voltage sensor

Here, a simple potential divider employed as a first stage to step-down the input voltage.

Mid-point of the divider and the op-amp ground are earthed.In the second stage, a differential


amplifier is used to amplify and to filter the differential signal obtained from the divider.

The final output voltage is fraction of difference of the input voltages which is given by:

Vo(s) =R2

R1(Va(s)− Vb(s))

(1 +R2Cfs)(1 +RoCos)(3.1)

fc1 =1

2πR2Cf, fc2 =

1

2πRoCo(3.2)

Figure 3.9: Non-isolated voltage sensor circuit

ITEM SPECIFICATION

RX 12kΩ

RY 1MΩ

R1 560kΩ

R2 1.2MΩ

Ro 250Ω

Cf 28µF

Co 60nF

fc1, fc2 4.737kHz, 10.61kHz

Voltage gain 0.02V/V

Input voltage range ±750V

Table 3.2: Design Data for voltage sensor

3.3. Non-isolated Sensor circuit 35

3.3.1.2 Current sensor

Here, a burden resistor is used to convert the current output produced by a Hall-effect based

current sensor into a voltage signal. Subsequently, a differential amplifier is employed to

amplify and filter the voltage signal.

Figure 3.10: Current sensor circuit

Vo(s) =R2

R1Io(s)Rb

(1 +R2Cfs)(1 +RoCos)(3.3)

ITEM SPECIFICATION

Rb 47Ω

R1 120kΩ

R2 1.2MΩ

Ro 250Ω

Cf 28µF

Co 60nF

fc1, fc2 4.737kHz, 10.61kHz

Current Sensor HE055T01

CT ratio 1000:1

Current gain 0.466V/A

Table 3.3: Design Data for current sensor


The output filter serves two purposes. Firstly, it attenuates the common-mode noise

present at the op-amp output. Common-mode noise may be present because of mismatch of

component values due to tolerances. Secondly, also acts as a current limiter if the output is

accidentally shorted.

3.4 Digital controller

FPGA based digital platform employed is employed for closed loop control.The choice of an

FPGA device for a given application is based on the size (i.e. no. of logic elements) required,

clock speed and number of I/O pins. ALTERA EP1C12Q240C8 was found to be suitable

for this application. The board was programmed using Quartus II (Version 9.0) software.

3.4.1 FPGA board

Figure 3.11: Block diagram of FPGA board

ALTERA EP1C12Q240C8 devics with CYCLONE FPGA chip has been chosen for this

work.The devices interfaced with the FPGA chip include configuration device (EEPROM),

ADC and DAC. Also dedicated I/O pins are also provided. The FPGA has logic elements

arranged in rows and columns. Each logic elements has certain hardware resources, which

will be utilized to realize the user logic. The vertical and horizontal interconnects of varying

3.4. Digital controller 37

speeds provide signal interconnects to implement the custom logic. The device data are

furnished in Table.3.4.

Part No EP1C12Q240C8

Manufacturer Altera

No of pins 240

No of I/O pins 60

Package PQFP

No of logic elements 12,080

No of PLL 2

Maximum clock frequency using PLL 275 MHz

Power supply required for core 1.5 V (VCCINT)

Power supply required for I/O 3.3 V (VCCIO)

Power supply required for PLL circuit 1.5 V (VCCPLL)

Table 3.4: ALTERA FPGA device data

3.4.2 ADC

ADC on the board, the AD7864AS-1 of analog devices, is used to convert the analog input

signals from the system into digital signals which are used for further processing. This MQFP

packaged, 12 bit, 44-pins simultaneous sampling ADC has 4 channels with a conversion time

of 1.6µs per channel. There are four such ADCs on the board and hence can take up to

16-analog input.

3.4.3 DAC

DAC on the board,the AD5447, is used to output the digital variables in the controller in

analog form. The DAC is CMOS based working with +5V and -5V power supply. This is a

12-bit, 24 pin, dual channel, current output DAC of AD has a conversion time of 10µs.


3.5 Experimental set-up with digital controller

All the necessary controller transfer functions are digitally implemented in the digital con-

troller. The relevant signals are fed into the FPGA through ADCs for processing. Once

processing is done, the digital controller subsequently produces the pertinent gate pulses for

each of the legs of converter such that system response tracks the set reference.

Figure 3.12: Experimental set-up with digital controller

3.6 Digital implementation

Implementation of all the algorithms and controllers has been done in 16-bit, 1’s complement

representation on the FPGA platform. But ADC and DAC are of 12-bits, so 4 LSB bits

are added as zeros and then properly scaled after sensing the signals to make them of 16-

bits. For outputting the signals through DAC, 4 LSB bits have been disregarded. 3FFF has

been chosen as 1 pu base. 16-bit by 16-bit, 32-bit output multipliers have been used. After

multiplication the 32-bit format have been retained for the state variables in integrations for

increasing the accuracy. After integration the signals have been scaled down to the 16-bit

format by shifting them 3-bits to left and and taking the 16 MSB bits.

The table 3.5 shows the digital equivalent (in Hex and Decimal formats) of the corresponding

pu value.

3.6. Digital implementation 39

pu value Equivalent Hex Value Equivalent Decimal Value

2 pu 7FFFH 32767d

1 pu 3FFFH 16383d

0 pu 0000H 0d

-1 pu C000H 49152d

-2 pu 8000H 32768d

Table 3.5: PU values

3.6.1 Base Values for Various Quantities

As the implementation is realized digitally, there arises the need for following a p.u system

for simple understanding. For perunitization of different quantities, their base values are

required, which can be chosen as per convenience. For example, the Table. 3.6 shows the

base values for voltage (chosen as the desired DC bus voltage), current (chosen as the peak

of the rated line current of the VSI) and frequency (chosen as grid frequency. The other base

quantities are calculated from the above mentioned base quantities.

Prated = 3kW (3.4)

Vgrid = 240V (3.5)

Irated = 12.5A (3.6)

Voltage (Vb) 400V

Current (Ib) 12.5 ∗√

2 = 19A

Frequency (fb) 50Hz

Frequency in rad/sec (ωb) 2π ∗ fb = 314.16rad/sec

Impedance(Zb)VbIb

= 21.05Ω

Table 3.6: Base values

Every sensed quantity (i.e. VDCbus and Io) must be perunitized inside the controller by

suitably scaling them for inerrant closed loop control. This measure is necessary when the

sensor gains are such that the sensor outputs are unperunitized in the firat place.


3.6.2 Transfer function implementation

Every frequency domain polynomial function that needs to be digitally implemented is first

discretized using suitable transformation procedure. A variety of discretization methods such

as Euler’s forward rule, Euler’s backward rule, Bilinear transformation, Impulse-invariant

transformation etc. are available in literature [21]. Suitable transformation technique may

be chosen for implementation. Depending on the sampling time (Ts) used, every method

has a fixed error associated with it, when implemented . This error approaches zero as Ts

approaches zero. Of all the techniques, forward rule has the possibility of making the system

unstable, when used. Impulse-invariant gives minimal error among all.

3.6.2.1 Low pass filter

In frequency domain, a low-pass filter is represented as:

y(s)

x(s)=

1

1 + sωc

(3.7)

where,

ωc =1

τ(3.8)

Here, ωc is the desired cut-off frequency. Equation.3.7 can be rewritten in time domain as:

y(t) + τdy(t)

dt= x(t) (3.9)

Discretizing the above using Backward rule, we get,

y(k − 1) + τy(k)− y(k − 1)

Ts= x(t) (3.10)

which finally yields the equation to be implemented,

y(k) = y(k − 1) +Tsτ

[x(k)− y(k − 1)] (3.11)

3.6.2.2 PI controller

In frequency domain, a PI controller is represented as:

y(s)

e(s)= ks +

kis

(3.12)

3.7. Conclusion 41

Equation.3.12 can be rewritten in time domain as:

y(t) = kpe(t) + ki

∫e(t) (3.13)

Discretizing the above using Bilinear transformation, we get the required equation to be

implemented,

y(k) = kpe(k) +ki

2Ts[e(k) + e(k − 1)] (3.14)

3.6.2.3 PR controller

Figure 3.13: Resonant controller

In frequency domain, a PR controller (whose details will be furnished in subsequent

chapter) is represented as:y(s)

e(s)= kp + ki

s

s2 + ω2o

(3.15)

To begin with, let us disregard the proportional term. The resonant structure would appear

as shown in the Fig.3.13. Now, Forward rule can be applied to discretize p(t) and q(t),

p(k) = p(k − 1) + ωoTsq(n− 1) + kie(k − 1) (3.16)

q(k) = q(k − 1) + ωoTsp(k) (3.17)

So, with the proportional term included, the total output of the PR controller is given by,

y(k) = kpe(k) + p(k) (3.18)

3.7 Conclusion

In this chapter, details pertaining to power circuit components were furnished. Non-isolated

sensor circuit design was discussed briefly. FPGA based digital controller and its attributes

were described along with per-unitization and digital implementation techniques.

Chapter 4

Single phase closed loop control

4.1 Introduction

In this chapter, all the essentials for closed loop control are dealt with in detail. De-

sign of Single phase PLL structure based on resonant controller is discussed along with

AFEC/STATCOM operation of the power converter. Fundamentals of resonant controller

are explained. Design of current controller and voltage controller are done.

4.2 Grid interactive mode

Figure 4.1: Scheme for power transfer between two active sources

Whenever power needs to be needs to be transferred from one active source to another, it

is required that the two are of identical frequency, as shown in Fig.4.1. Grid interactive mode

of operation of a converter is basically one such situation where power is transferred from

grid to inverter or vice-versa. In AFEC mode, active power is transferred from grid to the

42

4.2. Grid interactive mode 43

converter at unity power factor . The converter here acts as an active rectifier (as opposed to

a conventional diode/thyrister based rectifier) catering DC load. Such a rectification process

is quite advantageous as the grid current harmonics are reduced to a large extent. It is also

very flexible as it allows bi-directional power flow at any desired power factor.

In STATCOM mode, the converter supplies lagging reactive power to grid thus improving

the effective power factor seen by the grid. This in turn reduces undesirable losses occurring

at generation, transmission, and distribution levels.

So, grid interface as such entails accurate tracking of grid frequency. Hence, a Phase

locked loop (PLL) is mandatory. Once tracking is done, DC bus voltage of the converter is

raised to the required value. This value, in AFEC case, depends on the application. In case

of STATCOM, this boost value depends on the maximum amount of reactive power that

needs to be supplied to the grid by the converter. Ideally, once DC bus voltage boosts, it

remains at that value even when the STATCOM is supplying rated reactive(lagging) current

to the grid. But practically, the DC bus voltage would fall due to the losses occurring in the

converter. These losses mainly include conduction and switching losses of the converter. It

case of AFEC, DC bus voltage promptly falls when the DC link is loaded, and the quantum

of fall depends on the quantum of loading. Hence, there arises a requirement to maintain

the DC bus voltage at the required (raised) value. So a control loop is required for this DC

bus voltage maintenance. It is also desirable to operate the converter as a current controlled

VSI rather than a voltage controlled VSI so as to avoid the possibility of instability [20]. So

a current control loop is required.

It is relatively easy to do such a control for a three phase power converter. Typically,

d-q control/vector control technique is employed where the three phase AC quantities are

transformed to DC through Synchronous Reference Frame (SRF) transformation. Conse-

quently, all references become DC and hence conventional PI controllers would suffice to

yield zero steady state errors for both the aforementioned control loops. PI control design

is straightforward and well discussed in literature [15].

But, such a control is not so trivial in case of single phase systems. Here, d-q control

is not feasible since only one grid voltage is available. References are thus AC in nature.

And usage of PI controllers would result in significant gain and phase errors depending on

the bandwidth of the system. This is because, a PI controller has infinite gain only at DC

and thus loop gain will be infinite only at DC. Since infinite loop gain is essential for zero

steady-state error, a PI controller based control is satisfactory for DC quantities only. For AC

44 Chapter 4. Single phase closed loop control

references, PI controller’s performance is acceptable only for very large bandwidth systems.

At higher power levels, switching frequency is limited in order to bring down the losses in

the system. Hence system bandwidth is also limited. Again, for grid synchronisation, the

PLL structure in single phase case is not straight as it is in the three phase case.

In this work, single phase resonant PLL structure is employed for grid synchronisation

and PR controller is used for accurate AC reference current tracking. For DC bus voltage

control, conventional PI controller is sufficient.

4.3 Phase Locked Loop

Figure 4.2: A three phase PLL

In Fig.4.2, a conventional three phase PLL is shown. Vα and Vβ are stationary frame

orthogonal vectors obtained from the three phase grid voltages (through conventional 3φ to

2φ transformation).

Vα(t) =3

2(Va) (4.1)

Vβ(t) =

√3

2(Vb − Vc) (4.2)

They are then transformed to synchronous reference frame where they get converted to DC

4.3. Phase Locked Loop 45

Figure 4.3: Phasor diagram for grid voltage alignment

quantities (viz. Vd and Vq). Vd

Vq

=

32V cos (ωt− φ)

32V sin (ωt− φ)

(4.3)

Now, to align the grid space phasor along q-axis, it is required to set Vd to zero. Information

about the grid voltage peak is not required. Once this alignment is done, q-axis would

correspond to real power axis and d-axis would stand for reactive power.

The open loop transfer function of the PLL and the corresponding PI controller design

has been well discussed in literature [11]. The plant transfer function and loop gain of the

system is given by,

Gplant(s) =1

1 + sTs

V

s(4.4)

GHol = kpll

(1 + sTpllsTpll

)(1

1 + sTs

)(V

s

)(4.5)

where, Ts is sampling time. Method of symmetrical optimum is used to calculate the con-

troller gains [11].

ωc =1

αTs(4.6)

Tpll = α2Ts (4.7)

kpll =1

α

1

V Ts(4.8)

Fig.4.4 shows a general structure of a single phase PLL. It is quite similar to a three

phase SRF PLL structure, except for the orthogonal vector generation block. In three

phase case, stationary frame orthogonal vectors are directly obtained from grid voltages. In


Figure 4.4: A general single phase PLL structure

single phase case, an orthogonal vector corresponding to the single available grid voltage

Vg needs to be generated. Various ways of single phase PLL implementation are available

viz. transport delay method, pure integrator method, all-pass function method, inverse

Park transformation method etc. Each differs from the rest in the way of generation of the

aforementioned orthogonal vector [12].

In this work, the required orthogonal vector is generated using a resonant controller, as

shown in Fig.4.5. It can be seen that the block consists of two integrators connected back to

Figure 4.5: Resonant controller based orthogonal vector generation


back [13]. Here, ωo is fixed corresponding to 50Hz. To understand its working, it necessary

to comprehend certain transfer functions.

Vph(s)

Vg(s)=

ωos

s2 + ωos+ ω2o

(4.9)

V′qd(s)

Vg(s)=

ω2o

s2 + ωos+ ω2o

(4.10)

Figure 4.6: Bode plot forVph(s)

Vg(s)

Figure 4.7: Bode plot forV′qd(s)

Vg(s)


The resonant controller has infinite gain at ωo which in this case corresponds to 50

Hz. Thus, error rapidly converges to zero making Vph to follow Vg. This is easily seen in

Equation. 4.9 whose gain is unity only at 50 Hz. Also, V′qd forms the quadrature component.

SRF transformation can now be applied.

But the setback here is that if the grid voltage happens to have a DC offset, it is directly

reflected in V′qd. This is evident from Fig.4.7, where the transfer function has unity gain for

DC. But this is not the case with Vph. This severely affects the performance of the PLL. Vd

and Vq are no longer DC quantities due do the DC offset present in V′qd and this seriously

affects the PI controller output. To deal with this, the error (which again contains the same

Figure 4.8: Simulated response of V′qd and Vph for a DC offset in grid voltage

DC offset) is filtered and subtracted from V′qd to get Vqd, which is the required orthogonal

vector. Now Vph and Vqd are our stationary frame orthogonal vectors for the single grid

voltage Vg. Now, SRF transformation may be applied to yield corresponding Vd and Vq.

Once Vd is made zero by the PI controller, grid voltage would align along q-axis and Vq

would then represent the peak of grid voltage. With θ available from the PLL, the unit

vectors can be conveniently obtained from a look-up table.

Fixing ωo to 50 Hz limits the frequency range in which the PLL would operate properly

as intended. In the present case, the PLL was found to track input frequency accurately

between 47Hz to 53Hz. Outside this range, performance was poor. Performance can be

significantly improved if the gain ωo was made adaptive depending on the PLL output ωref .

But then, for all practical purposes, this range was adequate as it accounts for the maximum

allowable grid frequency variation.


Figure 4.9: Grid voltage [CH1(Yellow)] and unit vectors [CH4(Green) and CH3(Pink)] when

PLL is enebled [CH2(Blue)]

Figure 4.10: Unit vectors [CH4(Green) and CH3(Pink)] and grid voltage [CH1(Yellow)] at

steady state


Figure 4.11: In-phase unit vector [CH4(Green)] when there is a sudden dip in grid voltage

[CH3(Pink)]; CH2(Blue): Enable signal

Figure 4.12: In-phase unit vector [CH4(Green)] with DC offset in grid voltage [CH3(Pink)]

4.4. Resonant controller 51

4.4 Resonant controller

As explained in Section.4.2, a PI controller is not suitable when references are AC in nature.

Fig.4.13 shows the construct of a resonant controller [10]. Its transfer function is given by,

p(s)

e(s)= ki

s

s2 + ω2o

(4.11)

Figure 4.13: A resonant controller

Figure 4.14: Bode plot of resonant controller (with resonance at 50Hz

It could be considered as a generalised integrator with a resonance at ωo. When ωo is set

to zero, it reduces to an ordinary integrator. The gain of the function tends to infinity a ωo.

Hence by suitable selecting ωo, it is possible to achieve very large loop gain for 50Hz and

negligible loop gain for other frequencies. Thus, it tracks the required 50Hz AC reference.


4.4.1 Proof

To prove this more rigorously, internal model principle [9] may be used. The principle states

that the output of a control object follows its reference without a steady state error if the

open-loop transfer function of the system includes a mathematical model which can generate

the required reference. In a PI controller, the integrator (1s) is the mathematical (frequency

domain) model for a DC quantity. Thus it achieves zero steady state error for DC references.

So, we need a sinusoidal model (such as the one in Equation.4.11) in the controller to achieve

zero steady state error for sinusoidal reference. Consider a simple system shown in Fig.4.15.

Figure 4.15: A simple control system

Gol(s) = G(s)H(s) =N(s)

D(s)(4.12)

For sinusoidal reference,

U(t) = Acos(ωt) (4.13)

U(s) =As

s2 + ω2o

(4.14)

E(s) =U(s)

1 +Gol(s)=

D(s)U(s)

D(s) +N(s)(4.15)

=D(s)

(s− p1)(s− p2)..(s− pn)

As

s2 + ω2o

(4.16)

where pi′s are the poles of a general nth order system with all Re(pi) < 0. Using partial

fraction expansion, error can also be represented as,

E(s) =a1

(s− p1)+ ..

an(s− pn)

+b1

(s+ jωo)+

b2(s− jωo)

(4.17)

where,

b1 = (s+ jωo)E(s)|s=−jωo (4.18)

4.4. Resonant controller 53

b1 = (s− jωo)E(s)|s=+jωo (4.19)

This yields,

b1, b2 =A

2

D(±jωo)D(±jωo) +N(±jωo)

(4.20)

If the open loop transfer function has +jωo and −jωo as poles, then,

D(s) = (s2 + ω2o)D

′s (4.21)

and this means,

D(±jωo) = 0 (4.22)

This makes ,

b1 = b2 = 0 (4.23)

Thus, from Equation.4.17, the error function converges to zero asymptotically.

4.4.2 Testing of resonant controller

A first order test plant with sinusoidal reference as shown in Fig.4.15 was used to verify

the above result. The converter was ran in standalone mode with just a current controller.

System specifications are listed in Table.4.2

Parameter Specification

Vdcbus 400V

R 10Ω

L 45mH

fp 35.3Hz

fBW 353Hz

kp 100

ki 44444.44

ωp 222.22

ωo 100π

Table 4.1: Test system specifications


Plant transfer function is given by,

G(s) =0.1

1 + sωp

(4.24)

Transfer function of the PR controller used is given by,

H(s) = kp + kis

s2 + ω2o

(4.25)

Figure 4.16: Error function comparison for a reference of 10A through simulation

Figure 4.17: Output current[CH3(Pink)] with PR current controller for a reference of 10A;

CH4(Green): Reference; CH3(Blue): Feedback

4.5. DC bus voltage determination 55

Figure 4.18: Bode plot for a PR controller set to track 50Hz reference

The current controller was found to track the reference accurately. For controller gains

calculation, firstly a PI controller (i.e. a DC compensation network) is designed. Subse-

quently, it is transformed into an equivalent AC compensation network (with generalised

integrator) as suggested in [8]. This yields,

kp|PR = kp|PI (4.26)

ki|PR = 2ki|PI (4.27)

4.5 DC bus voltage determination

Before closing the loop, it is essential to know the boost level of DC bus voltage so as to

set reference for the control loop. As mentioned before, this value depends on application in

case of AFEC. In case of STATCOM, it needs to be predetermined. Fig.4.19 illustrates the

relevant calculation.

To begin with, a 10% drop across the filter inductance may be assumed. It may be

note from the phasors that the burden on the DC bus is more in case of STATCOM when

compared to AFEC. This is because the filter drop adds algebraically to the grid voltage,

whereas with AFEC, it is a phasor addition. For a 3 kW operation, considering the worst

(STATCOM) case,

Vi(peak) = Vdcbus = Vg(peak) + ωLIg(peak) (4.28)


Figure 4.19: Phasor diagram for DC bus voltage evaluation

Prated 3kW

Vrated 240V

Irated 12.5A

fsw 9.76Hz

Ts 25.6µs

Table 4.2: Rated system specifications

= 240√

2 + 0.1× 240√

2⇒ 373.35V (4.29)

Assume Vdcbus = 400V (4.30)

4.6 Overall control structure and strategy

The overall control structure for AFEC/STATCOM mode of operation is shown in Fig.4.20

4.6. Overall control structure and strategy 57

Figure 4.20: Overall control structure for single phase AFEC/STATCOM

4.6.1 Control strategy

In a conventional three phase case where d-q control is employed, Iq and Id represent real cur-

rent and reactive current reference respectively (in synchronous reference frame), provided

the grid spacer is aligned along q-axis [24]. For brevity, same notation is being followed

here. However, in this case they represent the actual peak values of real and reactive current

references respectively in stationary reference frame. In the three phase case, SRF trans-

formation enables decoupling of active and reactive currents and hence makes independent

power control possible. In the present case, such an isolation is achieved with the help of

PLL which produces unit vectors in phase and quadrature with the grid voltage.

The control structure has an outer voltage loop for maintaining the DC bus voltage at the

desired (calculated) value. A PI controller is employed in the loop as the reference here is DC.

Since the active power requirement in the system is directly reflected as fall in the DC bus

voltage, the output of the outer voltage loop is taken as the peak of active current reference

( denoted as I∗q ). The corresponding active AC current reference is obtained by merely

multiplying the in-phase unit vector with I∗q . In AFEC case, this reference is determined

by the quantum of loading on the DC side. In STSTCOM case, this reference is very small

catering the losses in the converter.

Reactive current reference depends on the desired operating power factor in case of AFEC

and on the amount of reactive power compensation desired, in case of STATCOM. The


reactive current reference again is obtained by merely multiplying the quadrature unit vector

with I∗d as illustrated in Fig.4.20. Desired I∗d may be set externally in the controller. But

this is not the case with I∗q , as it is set by the voltage controller.

Since the current references are AC quantities, a PR controller is employed for the inner

current loop which is set to have a resonance at 50Hz . For inerrant operation of the system,

the inner current loop needs to be quire faster than the outer voltage loop [15], [24]. Typical

relationship used is,

fBW (outer) ≤fBW (inner)

10(4.31)

fBW (inner) ≤fSW10

(4.32)

4.6.1.1 Feed-forward terms

Feed-forward essentially helps in improving the dynamic performance of the system and

completes the decoupling of active and reactive currents. Typically DC load current feed-

forward (for voltage loop), inductive drop feed-forward and grid voltage feed-forward (VgFF )

(for current loop) are employed [14]. Here, only current loop feed-forward terms are being

used as illustrated in Fig.4.20. The inductive drop feed-forward terms to be added can be

readily obtained from the phasor diagram (Fig.4.19). To begin with, when control is not

enabled, due to VgFF which is same as the grid voltage, no power transfer takes place between

the two active sources. Once control is enabled, depending on the system conditions and

references, the controller produces adequate output above/below VgFF so as to make the

system response follow the references.

4.7 Current controller design

The design procedure here is similar to that of a three phase case [24]. The relevant plant

transfer function is given by,

G(s) =ii(s)

Vi(s)=

1

Rf + sLf(4.33)

As mentioned in the foregoing section, to design a PR-controller, it is essential to design a

conventional PI controller first. The PI controller transfer function is given by,

H(s) = k′

p

1 + sTcsTc

(4.34)

4.8. Voltage controller design 59

Figure 4.21: Current control loop

where k′i =

k′p

Tc

G(s)H(s) =1

sTbw=

k′p

sTcRf

(4.35)

Tc =LfRf

(4.36)

The desired constants are,

k′

p =LfTbw

(4.37)

k′

i = kpωbw (4.38)

Therefore, the constants for PR-controller are,

kp =LfTbw

(4.39)

ki = 2kpωbw (4.40)

4.8 Voltage controller design

For voltage controller design, the gain of inner current loop can be assumed to be unity

(from Eq.4.31 and Eq.4.32). To begin with, the same design methodology as that of a three

Figure 4.22: Voltage control loop


phase case is adopted.

k =IdcIac

=Vl−l(rms)√

2Vdc(4.41)

kkvsC

=1

sTv(4.42)

kv =

√2CVdc

Vl−l(rms)Tv(4.43)

The voltage controller gains were slightly varied from design values to achieve satisfactory

system response. The design values are listed in Table.4.3

fsw 10kHz

fbw(inner) 600Hz

kp 4.68

ki 5616

fbw(outer) 8Hz

kv 2.5

Tv 120ms

Table 4.3: Control loop design data

4.9 Conclusion

In this chapter, closed loop control strategy is explained in detail. Design of single phase

resonant PLL, PR controller and PI controller for grid interactive mode of operation of the

converter is discussed. The converter was run in both AFEC and STATCOM mode and

the injected grid current was examined for harmonics. Experimental results are furnished in

forthcoming chapter.

Chapter 5

Results and conclusion

5.1 Introduction

In this chapter, some of the experimental results which were used to verify the transfer

function model developed for the proposed filter-transformer and its performance as a higher

order filter are discussed. The frequency response characteristics of the filter-transformer

configuration are obtained from a network analyzer. Experimental results pertaining to grid

interactive mode of operation of the power converter (with the proposed filter-transformer)

are furnished. Additionally, Fourier analysis results for the relevant output currents are

presented. Finally, conclusions are drawn.

5.2 Frequency response characteristics

Here, based on the developed transfer function model of the filter-transformer, simulated

frequency response of various transfer functions is presented. Also, the frequency response

was measured using an analog network analyzer manufactured by AP Instruments. The

network analyzer has a frequency range from 0.01 Hz to 15 MHz, with a maximum output

of 1.77V. Current measurements were made with Textronix TCP300 AC/DC current probe.

All the transfer functions of the filter-transformer as detailed in chapter 2 were measured

in the frequency range of 10 Hz to 1 MHz with atleast 1000 data points, each point averaged

40 times. The actual output of the network analyzer are compared with simulated frequency

response

61

62 Chapter 5. Results and conclusion

Figure 5.1: Simulated frequency response of O.C secondary voltage (Vs(s)) to primary voltage

(Vi(s))

Figure 5.2: Measured frequency response for O.C secondary voltage (Vs(s)) to primary

voltage (Vi(s))

5.2. Frequency response characteristics 63

Figure 5.3: Simulated frequency response of injected grig current to inverter voltage ( Ig(s)Vi(s)

)

with Vg = 0

Figure 5.4: Measured frequency response of injected grig current to inverter voltage ( Ig(s)Vi(s)

)

with Vg = 0


Figure 5.5: Simulated frequency response of inverter current to inverter voltage ( Ii(s)Vi(s)

) with

Vg = 0

Figure 5.6: Measured frequency response of inverter current to inverter voltage ( Ii(s)Vi(s)

) with

Vg = 0

5.3. Standalone mode 65

5.3 Standalone mode

Here, the filter-transformer’s performance with and without the third winding (AW) are

shown under open secondary (SW) condition. Without AW, the structure is similar to a

simple first order L-filter. With the third winding, the structure exhibits a higher order filter

behaviour as seen in the foregoing chapter.

Figure 5.7: CH1(Yellow):Applied primary (inverter) voltage; CH2(Blue): Secondary (out-

put) voltage; Without AW

Figure 5.8: CH1(Yellow): Primary voltage; CH2(Blue): Secondary voltage; With AW


5.4 Grid interactive mode

The power converter was interfaced with grid through the proposed integrated filter-transformer.

Experimental results pertaining to its performance with and without the third winding (AW)

under STATCOM and AFEC modes of operation are presented. Tektronix TPS 2024 DSO

was employed to capture the results.

5.4.1 Operation as a two-winding transformer

Here, the structure is operated without the third winding (AW). Thus, the structure be-

haves as a first order L-filter. The corresponding inverter and grid currents under different

operating conditions are captured and presented.

Figure 5.9: CH1(Yellow,1A/div): Grid current; CH2(Blue,0.1A/div): Inverter current;

CH3(Pink): Sensed grid voltage; With control not enabled


Figure 5.10: CH1(Yellow,50V/div): DC bus voltage boost profile; CH2(Blue): Enable signal

Figure 5.11: CH1(Yellow,2A/div): Grid current; CH2(Blue,5A/div): Inverter current;

CH4(Green): Grid unit vector; with control enabled, 0A reference


Figure 5.12: CH2(Blue,5A/div): Inverter current; CH4(Green,2V/div): Grid unit vector; In

STATCOM mode at 90% load

Figure 5.13: CH1(Yellow,5A/div): Grid current; CH4(Green,2V/div): Grid unit vector; In

STATCOM mode at 90% load


5.4.2 Operation as a three-winding transformer

Here, the proposed structure is operated with the third winding (AW). Now, the structure

behaves as a higher order filter.The corresponding inverter and grid currents under different

operating conditions are captured and presented.

Figure 5.14: CH1(Yellow,50V/div): DC bus voltage boost profile; CH2(Blue): Enable signal


Figure 5.15: CH1(Yellow,2A/div): Capacitor current; CH2(Blue,2A/div): Inverter current;

CH3(Pink): Sensed grid voltage; with control enabled, 0A reference

Figure 5.16: CH1(Yellow,2A/div): Grid current; CH2(Blue,5A/div): Inverter current;

CH4(Green): Grid unit vector; with control enabled, 0A reference


Figure 5.17: CH1(Yellow,50V/div): DC bus voltage ripple; CH2(Blue,5A/div): Grid current;

CH3(Pink,5A/div): Inverter current; CH4(Green,2V/div): Grid unit vector; with control

enabled, 80 % load

Figure 5.18: CH1(Yellow,50V/div): DC bus voltage ripple profile; CH3(Pink): Enable signal

for Current reference change from 25% to 90%


Figure 5.19: CH2(Blue,5A/div): Inverter current; CH4(Green,2V/div): Grid unit vector;

with control enabled, 90% current reference at 0 p.f (leading)

Figure 5.20: CH1(Yellow,5A/div): Grid current; CH4(Green,2V/div): Grid unit vector;

with control enabled, 90% current reference at 0 p.f (leading)



with control enabled, 90% current reference at 0 p.f (lagging)


with control enabled, 90% current reference at 0 p.f (lagging)



with control enabled, AFEC UPF operation


with control enabled, AFEC UPF operation



with control enabled, AFEC operation with 10% reactive (leading) current ref-

erence


with control enabled, AFEC operation with 10% reactive (leading) current reference


5.5 Harmonic analysis

Most utilities insist that current harmonic limits (as dictated by IEEE 519-1992 system

standard) should be met at the point of common coupling of non-linear equipments. In

the present case, it is a power converter. Hence, to measure the efficacy of the integrated

filter-transformer, harmonic analysis is necessary. Total demand distortion (TDD) of the

injected grid current is quantity of interest here, which is given by,

ITDD =

√I22 + I23 + I24 ...

Irated× 100% (5.1)

TDD is a better way to measure current distortion as it is independent of fundamental

current and hence the operating point of the system. Data points of relevant currents

were captured and further processing (in MATLAB 7.0) was done to obtain their respective

harmonic spectrums.

Here, results pertaining to harmonic analysis and TDD value for inverter and grid currents

under two-winding and three-winding operation of the filter-transformer in STSTCOM mode

is presented.

Figure 5.27: Inverter current under two-winding operation

5.5. Harmonic analysis 77

Figure 5.28: Inverter current harmonics under two-winding operation

Figure 5.29: Grid current under two-winding operation


Figure 5.30: Grid current harmonics under two-winding operation

Figure 5.31: Inverter current under three-winding operation

5.5. Harmonic analysis 79

Figure 5.32: Inverter current harmonics under three-winding operation

Figure 5.33: Grid current under three-winding operation


Figure 5.34: Grid current harmonics under three-winding operation

Current(TDD) Two-winding operation Three-winding operation

Ii(TDD) 7.9% 9%

Ig(TDD) 7.8% 5.2%

Table 5.1: TDD comparison

Resonant peak,valley/Transfer function ig(s)vi(s)

ii(s)vi(s)

vs(s)vi(s)

fpeak(calculated) 5.14kHz 5.14kHz 3.3kHz

fpeak(measured) 5.4kHz 5.9kHz 3.37kHz

fvalley(calculated) 20kHz 4.04kHz 20kHz

fvalley(measured) 18kHz 4.25kHz 16kHz

Table 5.2: Comparison of theoretical and practical resonance/anti-resonance frequencies

5.6. Conclusion 81

5.6 Conclusion

It was intended to emulate a discrete higher order LCL-filter with an integrated magnetic

structure. A multi-winding transformer configuration was proposed to serve the purpose. An

appropriate equivalent circuit was developed for obtaining the pertinent transfer functions.

From the so obtained transfer functions, it was found that the proposed structure did not

emulate a LCL-filter entirely from output current perspective due to the presence of zeros.

Nevertheless, from the input current perspective, it was similar to a LCL-filter. Hence control

strategy for the filter-transformer remained the same as that of a LCL-filter.

Initially, core-type transformers were investigated for the purpose of magnetic integration.

Later, it was found unsuitable for the application in hand. Hence, a single phase shell-type

3kVA three winding transformer was built and tested. The measured transfer functions of

the transformer (through network analyzer) closely matched the theoretically predicted ones

(from the equivalent circuit). Since the equivalent circuit model of the structure disregarded

winding resistances, the developed transfer functions had no damping terms in them. As

a result, frequency responses in simulation had much greater resonant/anti-resonant peaks

than those obtained from the network analyzer, since winding resistances are practically

finite.

To verify the effectiveness of the filter-transformer, a grid connected operation of a single

phase power converter was necessary. A three phase power converter was operated in single

phase H-bridge configuration as a STATCOM. A resonant controller based single phase PLL

was implemented to track grid frequency. It was found to function well in a rather small input

frequency range of 47Hz to 53Hz. This performance was adequate to track grid frequency.

Proportional-resonant current controller was employed to ensure zero steady state errors for

AC references. Its performance was very effective. Conventional PI controller was employed

for regulation of DC bus voltage at 400V.

A closed loop control of the power converter interfaced with the grid through the inte-

grated filter-transformer was done using FPGA based digital controller. The transformer

was operated in two-winding configuration (without AW) emulating a first order L-filter and

in three-winding configuration (with AW) emulating a higher order filter. The correspond-

ing inverter and grid currents were examined. With two-winding configuration, there was

no noticeable difference between the inverter current and grid current as far as the switching

harmonics were concerned. In contrast, with the third winding in place, notable reduction


in grid current switching harmonics was observed. The structure’s performance was found

to be much better than a first-order L-filter. In all the cases, the two currents were found to

contain (mild) lower order harmonics that caused distortions in and around zero-crossings.

In terms of the total RMS value and third harmonic magnitude, the inverter side and grid

side currents differed slightly due to the peaky magnetizing current of the transformer (which

was not negligible in magnitude). The grid current was found to have slightly higher third

harmonic content and slightly lower total RMS value. The proposed structure and the con-

trollers were found to perform satisfactorily. DC bus voltage was found to contain 100Hz

ripple (over 400V DC value) which increased with increase in operating AC line current

magnitude. However, the oscillation was within acceptable limits of 5%. This behaviour is

an outcome of single phase operation of the power converter.

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Documents

Integrated Magnetic Filter Transformer Design for Grid Connected Single Phase PWM-VSI