North-Holland Microprocessing and Microprogramming 18 (1986) 355--362 355

I n t e l l i g e n c e D r i v e n T e m t S e q u e n c e G e n e r a t o r f o r V L S I D e m i g n

Al la Hohleni Behbahani(*) , Fredr ick a, H i l l ( + ) ~ and Hayank R, Patel (+)

(s) Dept. of E,E, Shar i f Univ. of Technology, Tehranl IRAN (+) Dept. of E.C.Et Univ. of Arizonav Tucson~AZ. UBA 85721

Rbstract

This paper describes the development of a user f r i end l y automatic Sequential CIRcuit Test System, SCIRTSS, for Custom VLSI design. The only descr ipt ion of the d i g i t a l c i r cu i t required by SCIRTSS is wr i t ten in A Hardware Programming Language, AHPL. SCIRTSS has been tested and found to funct ion properly for AHPL descr ipt ion of large d i g i t a l systems.

I. [NTRODUCTION

With the advent of VLSI d i g i t a l In tegra ted C i r c u i t s (ICs) conta in ing thousands of gates, i t is becoming more d i f f i c u l t to test the ICe completely since the IC has only a re . hundered inputs and outputs, and therefore no addi t ional observable tes t po in ts . Exerc is ing the func t ion of the h igh ly sequent ia l c i r c u i t usua l l y requ i res a la rge amount of tes t sequences and a l o t of t i e s on the t e s t e r . Stuck-at f au l t test ing is desirable but requires ~ the designer to come up with a test sequence to detect desired port ion of a l l stuck-at f au l t s . An automatic test generation system can obtain a nearly optimum test sequence for detecting these stuck-at f au l t s .

Sequential CIRcuit Test System (SCIRTSS) is an automatic test generation system which takes a funct ional descr ipt ion of a d i g i t a l sequential c i r c u i t described in A Hardware Programming Language ,AHPL. AHPL as well as SCIRTSS were developed at the U n i v e r s i t y of Arizona [ 1 , 2 , 3 , 4 ] . AHPL is a Register Transfer Language that can be used to descr ibe

synchronous and asynchronous s e q u e n t i i l c i r c u i t s . Af ter the designer has completed func t iona l s imu la t ion , the AHPL can be compiled to a g a t e - l e v e l desc r i p t i on to prepare for SCIRTSS. Consider f i gu re 1 tha t symbolizes our AHPL based approach to c l o c k adds VLSI design. The Designer works i n t e r a c t i v e l y with a funct ion leve l s imulator u n t i l an AHPL desc r i p t i on which s a t i s f i e s the o r i g i n a l s p e c i f i c a t i o n is obta ined. At t h i s po in t the designer can turn his a t t e n t i o n to tes t generat ion wi thout wa i t ing for cosp le t i on of layout and mask generat ion or even f o r the f i na l logic l i s t . I t is even poss ib le to a l t e r the AHPL descr ipt ion to f a c i l i t a t e tes t ing , i f the f i na l pass at test generation fo r some reason was unsat is factory.

SCIRTSS is based on an i n t e l l i g e n t h e u r i s t i c dr iven search system which generates the tes t sequence to propaga[e the #au l t e f f ec t to a pr imary output of the c i r c u i t . The tes t sequence generated is a concatenat ion of the sequence generated by repeated searches on the s ta te space of the design. These sequences are v e r i f i e d by a p a r a l l e l f a u l t s imu la to r . The search is implemented using a Funct ional leve l 3-valued simulator of the AHPL d e s c r i p t i o n . The recent vers ion of SCIRTSS is a menu-driven user f r i e n d l y packaga.

The asssueptions of t r e a t i n g only s tuck-a t zero and one f a u l t models, t r e a t i n g a s ing le f a u l t at a time and the clock node design are cont inued in t h i s stage of the developsent process. Ac tua l l y in the tea; xo r l d of t es t technology these assumptions are commonly accepted.

356 A.M. Behbahani et aL / Intelligence Driven Test Sequence Generator

Function Level Design (UAHPL) I

J Revision

d

I Function Simulation [

>

[ Automatic Test Generation 1

l '

Technology Dependent NetworkJ (UAHPL Compilers) I

1 J Logic/Switch Simulation I

• Timing Analysis I

I '

l , Pattern Generation 1

l LPro to type Fabr ica t ion ]

Figure I AHPL based VLSI Design

In the following the AHPL based SCIRTSS as well as the heuristic evaluation functions and design for t e s t a b i l i t y in the SC1RTSS environment will be t reated. Finally, the resu l t s of SCIRTSS and another ATBS package will be discussed.

2. AHPL Based ATGS

Two trends ex is ts in Automatic Test Generation System (ATGS). The f i r s t is based on s t ruc tured func t iona l desc r ip t ion language and an i n t e l l i g e n t test generation algorithm that would depend on the functional behavlour as well as the ga te l e v e l d e s c r i p t i o n of the

des ign . A good candidate, other than SCIRTSS, i s HITEST system [5 ] . The other t rend i s based on design for t e s t a b i l i t y , spec ia l l y the scan design that include the famous Level Sensitive Scan Design (LSSD) [6]. SCIRTSS i s based on the f i r s t approach, however, design for t e s t a b i l i t y is also permitted in SCIRTSS.

In the CAD for digital systems the user needs to describe the design in a proper level of abstraction that could be used as a unique source for the d i f f e r e n t l e v e l s of l o g i c des ign and to support an ATSS. SCIRTSS requi res a func t i on level desc r ip t i on of the des ign , supported by the corresponding gate leve l d e s c r i p t i o n .

AHPL is one of the widely circulated and completely documented modular hardware descr ip t ion languages. I t has a r i ch software support. The Universal AHPL (UAHPL), a superset of the i n i t i a l AHPL, is supported by a hardware compiler and a functional simulator [2,7], The UAHPL compiler is used as a tool to support the functional and two gate level simulators of SCIRTSfi (see f i gu re 2).

Network I Descr ip t ion in UAHPL

STAGE I Compiler

Executable J J SEARCH .... Functional Tables I S imula tor

STAGE 2,3 Co ip i le rs

1 Gate- level I Network Descr ip t ion J

SCIRTSS

D-Algori thm + Pa ra l l e l Faul t Simulator

Figure 2 Compiler Driven SCIRTSS

A.M. Behbahani etal. /Intelligence Driven Test Sequence Generator 357

The hardware language comp i la t i on is an invo lved process. The UAHPL compi ler i s p a r t i t i o n e d i n t o th ree stages. Two stages Ni l l be the same for a l l appl icat ions while the th i rd stage w i l l generate the appropriate output for the p a r t i c u l a r a p p l i c a t i o n . AHPL is a medium of clocked mode system d e s c r i p t i o n . i t h the assumption tha t most d i g i t a l systems could be par t i t i oned in to data and control sections. In the declarat ion section of the design wr i t ten in AHPL various buses, r e g i s t e r s , inpu ts , outputs and combinational logic c i r c u i t uni ts (CLU) are declared. The control section is a l i s t of numbered statements, each consist ing of action statements followed by a branch funct ion. The action statement consists of the bus connect ions and r e g i s t e r t r ans fe r s , the branch func t ion s p e c i f i e s which set of ac t ions , con t ro l s ta tes , are to be performed next . The branch may be c o n d i t i o n a l on the va]ue of any l i n e or reg is te r [ 1 ] .

3. INTELLIBENCE GUIDED AT6S

In A r t i f i t i a l In te l l igence, the problem- solving process is always viewed as a search in the state space. Each state represents e i ther pa r t i a l or complete so lut ion. The task is to f ind a path from some i n i t i a l state to the goal state. The object ive is to f ind and apply an operator that always generates the goal state. The search could be s i g n i f i c a n t l y reduced i f a set of i n t e l l i g e n t heur is t ics are used to select the best operator.

SCIRTSS uses heur is t i c search technique to determine test sequences which are subsequently ve r i f i ed by a pa ra l l e l f a u l t simulation. The searches are implemented by funct ion level execution of a Register Transfer representat ion of the c i r c u i t .

In the basle SCIRTSS loop shown in f igure 3, an i n i t i a l input sequence is applied to the f au l t simulator to dr ive the c i r cu i t in to a known state, then the system look for an undetected f au l t . Fault select ion process is based on a smart algorithm. Normally, an o p p o r t u n i s t i c one where d i f f i c u l t f a u l t s are selected f i r s t for propagation and easy fau l t s are selected for sens i t i za t ion , however, the user can change th is pol icy. Next, SCIRTSS searches for an input sequence to propagate or ssns i t i z~ that f au l t . F ina l l y , the f au l t simulator v e r i f i e s the generated input sequences.

The Search Algorithm

The search process is an i n t e l l i g e n c e - based a lgo r i thm to obta in tes t input sequences to e i ther propagate a stored fau l t or sens i t ize a particular fault. For fault propagation, search rece ives the present good s ta te and several s ta r t nodes. Each s tar t node is a f a u l t y s ta te of the c i r c u i t associated to a

p a r t i c u l a r f a u l t s tored in a f l i p - f l o p . Search takes a s t a r t node and at tempts to propagate the f a u l t to a c i r c u i t ou tpu t . Using ca lcu la ted h e u r i s t i c func t ion valuemt search goes from one s ta te to another, search c a l l s the func t i ona l s imu la to r tw ice , f i r s t fo r the good s ta te and secon~ for the f a u l t y s ta te of the c i r c u i t . Search conta ins two sets of nodes, different states of the circuit. One set, SETI, contains all the expandod nodes aftmr applying

I UAHPL Design I

1 Homing Experiment I

Search D-filgorithm

I

_ _

Ses i t i za t ion Search i

J

1 r

Para l le l Fault Simulation Fault L is t Reduction

Figure 3 SCIRTSS Flow Diagram

358 A.M. Behbahani eta/./Intelligence Driven Test Sequence Generator

a l l the i n p u t v e c t o r s . Search chooses a node w i th the lowes t h e u r i s t i c f u n c t i o n va lue f rom SETB and adds i t t o the o t h e r s e t , SETA, where a l l the nodes in the c u r r e n t p r o p a g a t i o n pa th a re m a i n t a i n e d . A f t e r e v e r y node i s g e n e r a t e d , SEARCH checks to see i f the f a u l t e f f e c t i s observable on an o u t p u t . When the fault effect is observable on an output, search stops and concatenate the set of input sequences it took to propagate that fault.

For f a u l t s e n s i t i z a t i o n , search s t a r t s w i th the p resen t good s t a t e o f the c i r c u i t , the s t a r t node, and a se t o f goal nodes, each corresponding to a distinct flip-flop or gate f a u l t . To s e n s i t i z e the s e l e c t e d f a u l t , search d r i v e s the c i r c u i t to the goal node s t a t e . Search u s e s the functional simulator to simulate the good state of the c i r cu i t from star t state to goal state, and SETA and SETB nodes with heurist ic values to obtain a near optimum input sequence set.

H e u r i s t i c Func t i on E v a l u a t i o n

Among the most e f f e c t i v e gu idance of the s t a t e - s p a c e graph d i r e c t e d search i s the h e u r i s t i c e v a l u a t i o n f u n c t i o n . The two modes of sea rch , the f a u l t p r o p a g a t i o n and the path s e n s i t i z a t i o n modes, are suppor ted by two t ypes of heuristic function.

The generalized heurist ic function is a collectio~1 of f o u r components. The p r e d e c e s s o r - n o d e Ap, f a u l t p r o l i f e r a t i o n A t , the c o n t r o l s t a t e d i s p a r i t y ad jus tmen ts A d and the boo lean d i s t a n c e A ~ U s e r - s p e c i f i e d weights associated with these adjustments are Wp,Wf ,W d and W b. The H e u r i s t i c f u n c t i o n H n i s d e f i n d as;

H n = wH d + G n - A

where

A = min( (A + A + A + A ),wH )

The d e f a u l t h e u r i s t i c H d and i t s w e i g h t , a re user d e f i n e d . S n i s the depth of the node n in the graph. A b r i e f d e s c r i p t i o n of each component, A, follows: 1) Ap : Th is h e u r i s t i c component depends on the h e u r i s t i c va lue o f the p redecesso r node and i t min im izes the jump around the graph. Apes used in the tq~ search modes. 2) Af : The d e t e c t i o n o f a f a u l t in the propagation search mode would be enhanced if more f a u l t s are s t o r e d in the f l i p - f l o p s of the c i r c u i t . Af i n c r e a s e s w i th the number of s t o r e d faults. This e f f e c t i v e component of the h e u r i s t i c e v a l u a t i o n f u n c t i o n i s o n l y a p p l i e d in the propagation search mode. In evaluating t h i s component c o n t r o l s t a t e f l i p - f l o p are g i ven tw i ce the weight of the da ta flip-flops s ince they are ha rde r to t e s t . 3) A d : Th is component would encourage the expans ion of t hose c o n t r o l s t a t e s t h a t has been e~panded l e s s f r e q u e n t l y du r i ng the search

p rocess . 4) A~ : The boo lean d i s t a n c e h e u r i s t i c funcion of oh= p r e s e n t node v a r i e s i n v e r s e l y w i th the boo lean d i s t a n c e , i . e . number o f memory mismatches, f rom the goal node. AbiS u led in the s e s i t i z a t i o n mode o n l y .

I t i s a lways p o s s i b l e f o r the d e s i g n e r to improve the search proems by i n t r o d u c i n g emi l c i r c u i t dependent improvements in the h e u r i s t i c function calculation. Through a user s u p p l i e d h e u r i s t i c s u b r o u t i n e the user can r e e v a l u a t e the h e u r i s t i c f u n c t i o n in a d i f f e r e n t Nay t h a t cou ld produce more f r u i t f u l l r e s u l t s [ 8 ] .

Accurate Functional Simulation

Accura te search s i m u l a t i o n i s a must to produce c o r r e c t and s h o r t t e s t sequence. The package d e s c r i b e d in t h i s paper i s s u p e r i o r in t h i s r ega rd compared to an e a r l i e r semi - au toma t i c v e r s i o n of SCIRTSS. The e a r l i e r v e r s i o n s u f f e r e d f rom the f a c t t h a t the good and faul ty networks were simulated to their successor nodes based on the control state of the good network only [3,8] . Three concepts were implemented to achieve a high level of accuracy. First, the stuck fault effect at f l i p - f l o p ou tpu t were a lways r e t a i n e d . The UAHPL sequence below i l l u s t r a t e s the p o i n t . I f c o n t r o l s t a t e 4 i s a c t i v e in both the good and f a u l t y ne two rks , then the COUNTR b i t s would be r e s e t to a l l ze ro in the good and f a u l t y ne twork simulation runs .

4 COUNTR[0:7] <= B$O;

Thus the f a u l t e f f e c t i s gone f rom the succesbsor node and i t has to be r e s t o r e d to match the g a t e - l e v e l s i m u l a t o r r e l u l t l . Tha i t ype of i n t r i n s i c i n a c c u r a c y of t he funct ional s i m u l a t o r s was s o l v e d in SCIRTSS. second, s e p a r a t e simulation f o r the good and the f a u l t y ne tworks removes the i n a c c u r a c y embedded in the dependent s i m u l a t i o n method. F i n a l l y , t e s t g e n e r a t i o n p rocess r e s u l t s are c o n s i s t a n t w i th the UAHPL f u n c t i o n v e r i f i c a t i o n s i nce they both use the same f u n c t i o n a l s i m u l a t o r .

Input Vectors

The inpu t v e c t o r s t h a t are used by the search A l g o r i t h m are d i v i d e d i n t o two typms. The f i r s t type i s the C o n t r o l I npu t Vec to r s ( C . I . V ) , these are gene ra ted automatically by the search p rocess based on the UAHPL c o n d i t i o n a l s t a t e m e n t s . The second t ype i s the Data Input Vec to r s ( O . l . V ) , t hese cou ld be s u p p l i e d by the user f o r any c o n t r o l s t a t e in the UAHPL d e s c r i p t i o n . The user may wish to p r o v i d e D . I .V f o r a subset o f the control states. The unspecified inputs will be assumed as don't cares. The interact ive data entry i e a user f r i e n d l y m u l t i l e v e l query system. O b v i o s l y , the number of lUCC lS lO r l o f each

A.M. Behbahani etal. / Intelligence Driven Test Sequence Generator 359

s t a t e (node) equal the p roduc t of the nusber of D . I .V and the C . I . V .

User F r i e n d l y SCIRTSS

In SCIRTSS an e x t e n s i v e e f f o r t has been made to min imize the problem of user i n t e r a c t i o n wi th t h i s CAD t o o l , and p r o v i d e the user w i th a r e l a x e d c o n t r o l over the system. For instance, while runn ing SCIRTSS the user can change the debug modes, view the set of expanded nodes i f the search f a i l s to sens i t ize a f au l t e f f ec t , or change the heur is t ic weights. The user can re ta in the f i na l state of the network a f te r each SCIRTSS run. This gives him the a b i l i t y to restore se lect ive runs and continue the test generation process along the preferred paths in the state-space of the network to ach ieve a near op t ima l t e s t sequence.

Bid i rect iona l Buses

Since SCIRTSS simulators do not model t r i - state values, SCIRTSS does not d i r ec t l y support b i -d i rec t i ona l buses. But b id i rec t iona l buses, EXBUSES, can be modeled us ing e x t e r n • l i n p u t s , EXINPUTS, BUSES, and e x t e r n a l o u t p u t s , EXOUTPUTS, f a c i l i t i e s in UAHPL. The EXOUTPUTS f a c i l i t y is assigned the va lue of the BUSES af te r the always act ive c o n t r o l state, ENDSEQUENCE. The EXINPUT f a c i t l i t y is used on the source side of the expressions and the BUSES f a c i l i t y is used on the dest inat ion side of the exp ress ions in the c o n t r o l s t a t es [B ] .

4. Design fo r T e s t a b i l i t y

The main problem that eight face the designer is the d i f f i c u l t y to test the design. However, i t is possible to modify the UAHPL c i r c u i t descr ipt ion in to a highly testable design. The design for t e s t a b i l i t y technique used in UAHPL is cal led the Clock Sensit ive Scan Design (CSSD). This is b a s i c a l l y an adoption of the scan design technique used in LSSD. In CSSB the system cluck is act ive in the normal and scan mode, and i t is the only synchronizing signal ava i lab le . The uelory elements in the CSSD change state on the negative edge of the clock s ignal , that is the source of the name 'Clock Sensi t ive ' zn c o n t r a s t to the 'Leve l S e n s i t i v e ' memory elements in LSSD [8].

The basic modif icat ion done to convert a normal UAHPL design to i t s equivalent CSSB design is the addi t ion of a Control Test input, possibly a separate test output, and to chain the data memory e lements i n t o a s h i f t r e g i s t e r s t r u c t u r e c o n t r o l l e d by the c o n t r o l t e s t i npu t l ine . In the test mode, the control input is a c t i v e and the t e s t ou tpu t p r o v i d e s an o b s e r v a t i o n p o i n t of the memory elements t ha t arm on the scan path . In the normal mode the

design behaves as expec ted . The des ign method in CSSB are f l e x i b l e and the user ingenuity p lays an impor tan t r o l e in w r i t i n g an op t ima l CSSD des ign . The main p e n a l t y in t h i s techn ique i s the a d d i t i o n a l p h y s i c a l requ i rements which means more p ins and d ie consumpt ion. The advantages gained by. the CSSD m o d i f i c a t i o n are simi lar to those of the LSSD techn ique .

5. CASE STUDY AND RESULTS

The r e s u l t s presented in t h i s paper i l l u s t r a t e s the c a p a b i l i t y of SCIRTSS to h •nd le l a rge and complex s e q u e n t i a l c i r c u i t s e f f i c i e n t l y . Severa l c i r c u i t s h•ve been t es ted under SCIRTSS, one of the c i r c u i t s which have been tes ted l o s t t h o r o u g h l y , namely the BYTADDR, is l i s t e d •nd d iscussed in the fo l lowing.

The c i r cu i t shown in f igure 4 is a byte processing c i r c u i t . I t re•ds from or writes to a 1bx16 random access memory that is embedded in the c i r c u i t . The Cosbinational logic uni ts used in th is c i r c u i t , namely an Incrementer and a Decoder are described in f igure 5. This is a r e l a t i v e l y large c i r c u i t with 585 gates and 283 f l i p - f l o p s , 256 of which are c o n t r i b u t e d by the RAH. The c i r cu i t contains a 4-b i t counter, • t r a d i t i o n a l l y hard to test funct ion. To sens i t ize the fau l t s in the HSB of the counter, the counter must be • l l o w e d to count up to t ha t b i t p a t t e r n , r e q u i r i n g • l a r g e number of input sequences to de tec t those f a u l t s . Since random i n i t i a l i npu t sequences u s u a l l y de tec t the easy f au l t s , a random input sequence of 50 clocks was a p p l i e d , which de tec ted 55 percen t of the f a u l t s . Three more SCIRTSS runs were executed to detect the harder f a u l t s .

A l l 32 p o s s i b l e comb ina t ions were s p e c i f i e d fo r the 5 - b i t ADDRESS e x t e r n a l i npu ts for D.I.Vs to assure that SCIRTSS can access a l l the locat ions for reading and wr i t ing the RAM. Except for the tO-bit DATAIN external inputs, only the a l l zeros combination was used as a D . I .V to reduc~ the number of successors generated from c o n t r o l s t a t e one. D i f f e r e n t D . I .V were app l i ed fo r the second, t h i r d , and the f o u r t h run to de tec t the r e s t of the f a u l t s in the c i r c u i t . In the f r n a l two runs the DATAIN va lues of a l l zeros and a l l ones were merely used as D . I .Vs to de tec t a l l the p a r a l l e l f a u l t s . SCIRTSS de tec ted 99.8 percen t of the detectable fau l t s in the c i r c u i t in four runs and an input sequence of 329 clocks.

I t would be i l l u s t r a t i v e to have a look at the r e g u l a r SCIRTSS ou tpu t fo r the BYTADDR c i r c u i t . The l i n k e d nodes in BETA of the successfu l search are shown in F igure b. In the s t a r t node, the good and f a u l t y networks i n d i c a t e d by symbols B and F r e s p e c t i v e l y , a re both in the control state I and 6 of module I. As shown in f i g u r e 6 two nodes were expanded to get to the goal node. The f a u l t e f f e c t , D, i s

360 A.M. Behbahani etal. / Intelligence Driven Test Sequence Generator

MODULE:BYTADDR.

EXINPUTS: ADDRESS[5]; READ; NRITE; DATAIN[16]; CLOCK. EXOUTPUTS: DATAOUT[16]; READY. HEHORY: ADDRE6[5]; DATAREG[16]; H<16>[16]. BUSES: ADOBUS[4]; DBUS[16]; DCDBUS[L6]. CLUNITS: DCD[16] <: DCDER(4}. CLUNITS: INC[4] <: INCER (4} .

BODY SEGUENCE: CLOCK,

1 ADDBUS = ADDRESS[O:3]; DATAREB[0:7] * (READ+NRITE) (=

(DBUS[O:7] !OBUS[B: I5 ] !DATAIN[0:7] ) * (READ&^ADDRESSE4]+~RITE&ADDRESS[4], READkADDRESSE4I,HRITEk^ADDRESS[4]);

DATARES[B:I5] * (READ+NRITE) ( " (DBUS[8:LS]!DATAIN[O:7]!DATA]N[B:151) * (READI#RITE&AOORESS[4]INRITE&^ADDRESS[4]);

ADDREB[0:3] (= (INC(ADDBUSI!ADDBUS) e (READ,NRITE); ADORES[4] <= ADDREBS[4]; => (^REAO&^NRITE,READ,NRITE)/( i ,2,4) .

2 DATAOUT = DATARE6; READY = ^ADDREG[4]; ADDBUS = ADDRE6[0:3]; DATARE6[8:I5] * ADORES[4] <= DBUS[0:7]; => ( ^ADDREB[4 ] ) / ( I ) .

3 DATAOUT = DATAREB; READY = \ 1 \ ; => (1) .

4 ADDBUS=ADDRE6[O:3]; ADDREB[O:3] <= INC(ADDBUS); H • DCDBUS (= DATARE6; READY = ^ADDRES[4I; DATAREB[O:7] <= DATAIN[B:15]; => ( ^ A D D R E S [ 4 ] ) / ( L ) .

5 ADDBUS = ADORES[O:3]; DATARE6[8:IS] <= DBUS[B: I5] .

6 ADDBUS = ADDRE6[O:3]; H * DCDBUS (= DATARE6; READY = \ 1 \ ; => ( l ) .

ENDSEOUENCE CONTROLRESET(I); DCDBUS = DCD(ADDBUS); DBUS = H * BCDBUB.

END.

F igure 4 BYTADDR UAHPL D e s c r i p t i o n

propagated f roe eeaory f l i p - f l o p 279 to the DATAREE f l i p - f l o p 23 whtch in tu rn p ropaga te i t to b i t ~ 2 of the ou tpu t l i n e DATAOUT in the next c l ock . The r e s u l t s of another r e l a t i v e l y l • r g e c i r c u i t 1 the d u p l i c a t e cha rac te r checker DUPCHK~ • r e a lso l i s t e d in f i g u r e 7.

I n t e r e s t i n g r e s u l t s were r e p o r t e d on HITEST [5 ] t ha t Ne N i l1 l i s t fo r i l l u s t r a t i v e purpose. HITEST is an i n t e r a c t i v e au tomat ic t e s t gene ra t i on system~ based on s t r u c t u r e d f u n c t i o n a l d e s c r i p t i o n language and k n o , l e d g e - based h e u r i s t i c s to c o n t s t r a i n i t s search fo r • p o s s i b l e inpu t sequence. The i n f o r m a t i o n a v a i l a b l e on the HITEST r e s u l t s xere not s u f f i c i e n t to s tage a de te rm ina te coepar ison

x i t h BCIRTSS r e s u l t s . Thus, we m i | l on l y use HITEST r e s u l t s to i l l u s t r a t e the c a p a b i l i t i e s of the eND sys tess .

The r e s u l t s of t#o c i r c u i t s t es ted by HITEST produced versus t x o o the rs tes ted by SCIRTSS are shoNn in f i g u r e 8. Accord ing to [53 CIRCUITI i s an a r i t h m e t i c l o g i c processor ch ip ; CIRCUIT 2 i s • ULA c i r c u i t c o n s i s t i n g of • bank of s e r i a l - i n / p a r a l l e l - o u t s h i f t reg is te rs , some combinational log ic t and a second bank of ser ia l - i n /para l le l -ou t r e g i s t e r s . HITEST genera tes s h o r t e r t e s t sequences. Th is i s expected Since i t i s supplemented x i t h a p o x e r f u l i n t e r a c t i v e g raph ic and wavefore languages mhich i n c r e a s e |

A.M. Behbahani etal./Intelligence Driven Test Sequence Generator 361

CLU : INCER(X) ( I } . INPUTS : X [ l ] . OUTPUTS : Y [ I ] . CTERHS : RESULT[el; CARRY[I-I].

BODY CARRY[I-2],RESULT[I-I]=X[I-I],^X[I-I]; FOR J - l - 2 TO 0 CONSTRUCT

RESULTCJ] = CARRY[J] g X[J]; IF J(>O THEN

CARRY[J-el = CARRY[J]&X[J]

FI ROF; Y = RESULT,

END.

CLU : DCDER(IN) ( I } . INPUTS : I N [ I ] . OUTPUTS : OUT[2^I]. CTERMS : RESULT[2^I]. BODY

FOR M=O TO (2^ l ) -1 CONSTRUCT RESULT[M] = &/TERM(M;IN)

ROF; OUT = RESULT.

END.

Figure 5 BYTEADDR CLUs Description

the operator con t ro l over the tes t generat ion process. The two systems run on VAX but SCIRTSS CPU time f igures are given for the VAX/750. In running SCIRTSS for the two c i rcu i t mentioned above, only the bu i l t in heurist ic functions were used. Results could have been better i f a user supplied heur ist ic routine was supplied to influence the h e u r i s t i c evaluatiofl.

6. CONCLUSIONS

This research con t r ibu ted in developing an i n t e l l i g e n t user f r i e n d l y ATOS for VLSI design. The main character ist ic of SCIRTSS is the accurate search simulation process. Another feature ~ f SCIRTSS is the capabi l i ty to handle VLSI type c i rcu i ts with up to lOOO memory elements and I0000 gates. Large c i rcu i ts produced efficient tes t sequences in a reasonable time. The new vers ion of SCIRTSS accepts the full range of the UAHPL including multiple modules and combinational logic unit description. Search algorithm is based on a t r i a l and error technique used to solve the NP- complete problem of test generation [9], thus the worst case complexity for the heurist ic guided search is not strongly dependent on the number of c i r c u i t elements. The fault s imulator simulates all the faults in parallel but varies

with the cubic power of the number of c i r c u i t elements [10] .

The SCIRTSS concept is that of generat ing the tes t sequence for a c i r c u i t in an ea r l y stage of the process, that is , even before the generation of the final logic desc r i p t i on of the circuit. Thus, the designer o;gkt i t e r a t i v e l y modify the high leve l desc r i p t i on of the design before a t es tab le func t i ona l c i r c u i t desc r i p t i on is developed. This concept resu l t s in a s i g n i f i c a n t saving in the demign time and e f f o r t . To improve tes t sequence generat ion, design for t e s t a b i l i t y is I recommended approach in SC[RTSS.

ACKNONLED6EMENT

The authors wish to thank 6. R. Zou, Z. Wang and A. Al tayeb for t h e i r c o n t r i b u t i o n in SCIRTSS programming and he lp fu l comments.

REFERENCES

[ I ] H i l l , F. J. and G. R. Peterson, Dig i ta l System: Hardware Organization and DesiDn, 2nd ed., John Wiley and Sons, New York, 1978.

[2] H i l l , F. J. , R. E. Swanson, H. Hasud, Z. Navabi, "Structure spcecif icat ion with m procedural hardware desc r i p t i on language," IEEE Trans. Comput. Vol. C-JO, No. 2, pp. [57-171, February 19B1.

[3] H i l l F . J . , and Den Huey, "SCIRTSS: A Search System for Sequent ial C i r c u i t Temt Sequences," IEEE Transact ions on Computers. Hay, 1977, pp.4?O-501.

[4] Chiang C. H., F. J. H i l l , Alma Mohmmni, and O. P. Chen I "Faul t Detect ion Teat Generation at the Register Transfer Design Leve l , " Proc l e t . PCCC, IEEE, 1982.

[5] Bending, M., "HITEST: A Knowledge-Based Test 6enrat ion System," IEEE Design and Test of Computers, Hay 1984.

[b ] N i l l i ams , T. W. and K. P. Parker, "Design for T e s t a b i l i t y - A Survey," IEEE Transact ions on Computers, Vol. C-JI , No. 1, January 1982.

[7] A l s h a r i f , H. S., " 'Funct iona l Level Simulator for Universal AHPL," H.S. Thesis, University of Arizona, Electr ica l and Computer Engineering Department, Tucson, 1983.

IS] Alma Mohsseni, " I n t e l l i g e n c e Driven Automatic Test Sequence 6enerator for VLSI," Ph.D. D i s s e r t a t i o n , Un i ve rs i t y of Arizona, Electrical and Computer Engineering Department, 1984.

[9] Aho, Hopcraft J. and J. 0. Ullman, The Design and Analys is of Computer A lgor i thms, Addison-Wesley, New York, 1974.

[10] Goel, P., "Test 6enerat ion Costs Analys is and P r o j e c t i o n s , " Proceedings 17th ACR- IEEE Design Automation Conference, 1980, pp. 84-88.

362 A.M. Behbahani et aL /Intefligence Driven Test Sequence Generator

SEARCH: SIMULATOR CALL LIMIT = 1200 SEARCH MODE = FAULT PROPAGATION NUMBER OF START NODES = 4 START NODE = 1

##g####g# SUCCESSFUL SEARCH AFTER 82 CALLS TO THE FUNCTIONAL SIMULATOR

# t | # # | l # | INPUT SEQUENCES OF LENSTH 2

NODE: 1 . . . . . EXTERNAL INPUTS . . . . .

ADDRESS [ O: 4 ] : 00000

READ [ O: 0 ] : 0 NRITE [ O: 0]: 0 DATAIN [ O: 7]: 00000000 DATAIN [ B: 15]: 00000000

..... EXTERNAL OUTPUTS ..... DATAOUT [ O: 7]: DATAOUT [ B: 15] READY [ O: O]

..... MEMORY .....

ADDREG < 0>[ O: 4]: DATARE6 < 0)[ O: 7] : DATAREG ( 0>[ 8: 15]: N < 0>[ O: 7]: N ( 0>[ 8: 15]:

( 1>( O: 7): 4 ~r R: 15]:

M M ( 1 4 ; t v . . . . M < 14>[ 8: 15]: H < 15)[ O: 7] : M < 15>[ B: 15]:

NO, OF ACTIVE CONTROL STATES:

PREDECESSOR NODE: NODE LEVEL : HEURISTIC VALUE:

2 3

11110 00000

1 l 0 0 00000000 00000000 00000000 00000000

00000000 00000000 11110111 00000000 00000000 lllDIlll 0 1 1

00001 00000 00010 01001011 11110111 OOll[OOl 00101101 111D1111 00111101 O01llO01 00111001 00111001 00101101 00101101 00101101 O O l i l lO i O0111Jn' lOlOtt~ ' ~vA

. . , 11100101 .v~,Auul 10011001 10011001 00000000 00000000 00000000 I I I I 0 1 1 1 01001011 01001011 l l l O l l l l O0101101 00101101

6 F S F 6 F 2 2 2 2 2 2

10011001 10021002 10011001 10061006 100t1001 10021002

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 0 1 0 0 105 0

F igure 6 SCIRTSS Output , Search Nodes in SETA

C i r c u i t BYTADDR DUPCHK

Number of Gates 585 161 Number of f l i p - f l o p s 283 300 Number of I npu ts 23 33 Number of Outputs 17 3 Number of Fau l t s 3114 1079 Fau l t s Found 3110 1079

Fau l t Found 99.8 100 Sequence Length 329 486 CPU t ime (see. ) 10784 1475

" C i r c 'u i t BYT CIR DUP CIR AODR CULT1 CHK CUIT2

No. of e lements 868 850 461 68 Test Sequences 329 85 486 40 No, of Fau l t s 3114 1340 1079 1092 Z Fau l t Found 99,8 2 95 100 100 CPU Time (sec . ) 10784 2520 1475 523

F igure 7 Summary of SCIRTSS Resu l ts F igu re 8 5C|RTSS and HITEST Resu l t s