I2c Bus Implementation and Application

INDEX CONTENTSPAGE NO1. ABSTRACT32. INTRODUCTION4 2.1 WHAT IS I2C4 2.2 HARDWARE5 2.3 OPERATING MODES53. I2C KEY FEATURES64 .I2C COMMUNICATIONS PROCEDURE65. I2C PROTOCOL CHARECTERISTICS7 5.1 I2C TERMINOLOGY7 5.2 CONFIGURATION9 5.3DATA VALIDITY11 5.4START AND STOP CONDITIONS12 5.5CONTROL SIGNALS13 5.6DATA TRANSFERS13 5.7 ACKNOWLEDGMENT14 5.8ARBITRATION15 5.9DATA FORMATS16 5.10 READ AND WRITE I2C:17 5.11 I2C ELETRICAL CHARACTERISTICS206. IMPLEMENTATION OF I2C MASTER CONTROLLER ON FPGA USING VHDL226.1REGISTER DESCRIPTION226.2 IMPLEMENTATION23 6.3 RESULTS23INDEXTABEL OF CONTENS PAGENO

7. IMPLEMENTATION OF I2C MASTER CONTROLLER 24USING INTEL MCS-51 7.1 MCS-51 HARDWARE REQUIRMENT25 7.2 MCS-51 I2C SOFTWARE EMULATION MODULES26 7.3 I2C SOFTWARE EMULATION PERFORMANCE268. I2C DESIGNER BENEFITS AND MANUFACTURER BENEFITS289. APPLICATION29 9.1 TV RECEPTION30 9.2 LCD DRIVER3110. CONCLUSION3211. REFERENCES32

ABSTRACT

I2C is the most commonly used serial protocol for both inter-chip and intra-chip low/medium bandwidth data-transfers. This paper contrasts and compares physical implementation aspects of the two protocols through a number of recent Xilinx's FPGA families, showing up which protocol features are responsible of substantial area overhead. This valuable information helps designers to make careful and tightly tailored architecture decisions. For a comprehensive comparative study, both protocols are implemented as general purpose IP solutions, incorporating all necessary features required by modern ASIC/SoC applications according to a recent market investigation of an important number of commercial I2C and SPI devices. The RTL code is technology independent, inducing around 25% area overhead for I2C over SPI, and almost the same delays for both designs. And also another method for implementing i2c controller by using MCS-51.This controller is connected toa microprocessor or computer and reads 8 bit instructions following I2C protocol. The instructions are then processed and converted to instructions which follow SPI protocol. 32 bit register is designed to send data serially as per SPI instructions. The complete module is designed in VHDL and simulated in Model SIM. The design is also synthesized in Xilinx XST 12.1 and optimized for area and power. This concept is widely applicable where a microprocessor wants to communicate with SPI device. This module acts as a slave for the microprocessor at the same time acts like a master for the SPI device which can be considered as a slave. Also this paper consists global application of i2c bus and their field.

INTRODUCTION:-The I2C-bus is a de facto world standard that is now implemented in over 1000 different ICs manufactured by more than 50 companies. Additionally, the versatile I2C-bus is used in various control architectures such as System Management Bus (Sambas), Power Management Bus (PMBus), Intelligent Platform Management Interface (IPMI), Display Data Channel (DDC) and Advanced Telecom Computing Architecture (ATCA).What isi2c ?IC(Inter-Integrated circuit), pronouncedI-squared-C, is amultimaster, multi slave,single-ended,serialcomputer businvented byPhilip semiconductors in 1982 or known today asNXP Semiconductors, used for attaching low-speed peripherals to computer to communication between integrated circuits (ICs) from different manufacturers. Motherboardsandembedded systems.Applications that use the I2Cbus include microcontrollers, LCD, memory, keyboards, PCs, cell phones, car radios, TVs, and blade servers. The I2C bus uses two bidirectional signals, one as the serial clock (SCL) line and one as the serial data (SDA) line. Each device connected to the bus has a unique address used to identify the device in communication. The protocol is comprised of a set of conditions to establish or terminate communication, a designation to read or write, and the ability to address devices with an expanded address scheme. A simple master/slave relationship is present on the bus continuously, and any device on the line can act as the master or slave.I2C has a data transfer rate of 400Kbits/s at a maximum length of 2 meters. It is possible to get a transfer rate of 3.4 Mbits/s at 0.5 meters on the high speed I 2C bus, and by using signal buffers, one can go up to 100 meters on the I2C bus.Devices connected to the I2C-bus system can operate as Masters and Slaves. The Master device controls bus communications by initiating/terminating transfers, sending information and generating the I2C system clock. On the other hand, the Slave device waits to be Addressed by the controlling Master. Upon being addressed, the Slave performs the specific function requested. An example of this configuration is a Master Controller sending display data to a LED Slave Receiver that would then output the requested display.The configuration described above is the most common; however, at times the Slave can become a Transmitter and the Master a Receiver. For example, the Master may request information from an addressed Slave. This requires the Master to receive data from the Slave. It is important to understand that even during Master Receive/Slave Transmission, the generation of clock signals on the I2C bus is always the responsibility of the Master. As a result, all events on the bus must be synchronized with the Master's SCL clock line.[3]I2c Hardware:I2C Hardware Characteristics Both SCL (Serial Clock) and SDA (Serial Data) are bi directional lines that are connected to a positive supply Voltage via pull-up resistors. It displays a typical lI2C-bus configuration. Devices connected to the bus require open-drain or open-collector output stage interfaces. As a result of these interfaces, the resistors pull both lines HIGH when the bus is free.

(.source :http://www.ermicro.com/blod)Data is transmitted to, and received from, the I2C bus via a buffered interface. Control and status information is relayed through a set of memory-mapped registers. (For a complete list of I2C bus features, capabilities, and operation details, see the I2C-Bus Specification.)[5]

I2C EEPROM Overview

Serial EEPROM devices are popular for storing system configuration parameters, user settings, measurement data, and other non-volatile information. In a typical usage model, an SoC processor acts as a master device that controls the exchange of data with the EEPROM .All I2C bus-compatible devices are incorporated on-chip to enable them to communicate directly with each other via the I2C bus.

The I2C module can operate in any of the following I2C systems:As a slave deviceAs a master device in a single master system (slave may also be active)As a master/slave device in a multi-master system (bus collision detection and arbitration [3]The official I2C bus protocol supports three modes of transfer rates:

Standard Mode Up to 100 Kbps Fast Mode Up to 400 Kbps High-Speed Mode Up to 3.4 Mbps[5]

Key features of the I2C module include the following:Independent master and slave logicMulti-master support, which prevents message losses in arbitrationDetects 7-bit and 10-bit device addresses with configurable address masking in Slave modeDetects general call addresses as defined in the I2C protocolAutomatic SCL x clock stretching provides delays for the processor to respond to a slave data requestSupports 100 kHz and 400 kHz bus specifications .Some intelligent control, usually a single-chip microcontroller General-purpose circuits like LCD and LED drivers, remote I/O ports, RAM,EEPROM, real-time clocks or A/D and D/A converter Application-oriented circuits such as digital tuning and signal processing circuits .[5]

I2C Communication Procedure:-One IC that wants to talk to another must: 1) Wait until it sees no activity on the I2C bus. SDA and SCL are both high. The bus is 'free'. 2) Put a message on the bus that says 'its mine' - I have STARTED to use the bus. All other ICs then LISTEN to the bus data to see whether they might be the one who will be called up (addressed). 3) Provide on the CLOCK (SCL) wire a clock signal It will be used by all the ICs as the reference time at which each bit of DATA on the data (SDA) wire will be correct (valid) and can be used. The data on the data wire (SDA) must be valid at the time the clock wire (SCL) switches from 'low' to 'high' voltage4) Put out in serial form the unique binary 'address' (name) of the IC that it wants to communicate with. 5) Put a message (one bit) on the bus telling whether it wants to SEND or RECEIVE data from the other chip. (The read/write wire is gone!) 6) Ask the other IC to ACKNOWLEDGE (using one bit) that it recognized its address and is ready to communicate. 7) After the other IC acknowledges all is OK, data can be transferred. 8) The first IC sends or receives as many 8-bit words of data as it wants. After every 8-bit data word the sending IC expects the receiving IC to acknowledge the transfer is going OK. 9) When all the data is finished the first chip must free up the bus and it does that by a special message called 'STOP'. It is just one bit of information transferred by a special 'wiggling' of the SDA/SCL wires of the bus.[5]

I2bus Protocol :

Standard-mode, Fast-mode and Fast-mode Plus I2C-bus protocols:

Two wires, serial data (SDA) and serial clock (SCL), carry information between the Devices connected to the bus. Each device is recognized by a unique address (whether It is a microcontroller, LCD driver, memory or keyboard interface) and can operate as Either a transmitter or receiver, depending on the function of the device. An LCD driver May be only a receiver, whereas a memory can both receive and transmit data. In addition to transmitters and receivers, devices can also be considered as masters or slaves when Performing data transfers. A master is the device which initiates a data transfer on the bus and generates the clock signals to permit that transfer. At that time, any device addressed is considered a slave.[8]

I2C Bus Terminology

Transmitter - the device that sends data to the bus. A transmitter can either be a device that puts data on the bus of its own accord (a master-transmitter), or in response to a request from data from another devices (a slave-transmitter). Receiver - the device that receives data from the bus. Master - the component that initializes a transfer, generates the clock signal, and terminates the transfer. A master can be either a transmitter or a receiver. Slave - the device addressed by the master. A slave can be either receiver or transmitter. Multi-master - the ability for more than one master to co-exist on the bus at the same time without collision or data loss. Arbitration - the prearranged procedure that authorizes only one master at a time to take control of the bus. Synchronization - the prearranged procedure that synchronizes the clock signals provided by two or more masters. SDA - data signal line (Serial DATA) SCL - clock signal line (Serial CLOCK) [8]I2c Bus Implementation and Application

Electronics and Communication EngineeringPage 1

I2C CONFIGURATON:

The I2C-bus is a multi-master bus. This means that more than one device capable of controlling the bus can be connected to it. As masters are usually microcontrollers, let us consider the case of a data transfer between two microcontrollers connected to the I2C-bus.

(.source file:http://www.ermicro.com/blod)This example highlights the master-slave and receiver-transmitter relationships found on the I2C-bus. Note that these relationships are not permanent, but only depend on the direction of data transfer at that time. The transfer of data would proceed as follows:1. Suppose microcontroller A wants to send information to microcontroller B: microcontroller A (master), addresses microcontroller B (slave) microcontroller A (master-transmitter), sends data to microcontroller B(slave-receiver) microcontroller A terminates the transfer.2. If microcontroller A wants to receive information from microcontroller B: microcontroller A (master) addresses microcontroller B (slave) microcontroller A (master-receiver) receives data from microcontroller B(slave-transmitter) microcontroller A terminates the transfer.Even in this case, the master (microcontroller A) generates the timing and terminates the Transfer. The possibility of connecting more than one microcontroller to the I2C-bus means that more than one master could try to initiate a data transfer at the same time. To avoid the chaos that might ensue from such an event, an arbitration procedure has been developed. This procedure relies on the wired-AND connection of all I2C interfaces to the I2C-bus.If two or more masters try to put information onto the bus, the first to produce a one whenthe other produces a zero loses the arbitration. The clock signals during arbitration are connection to the SCL line (for more detailed information concerning arbitration see Generation of clock signals on the I2C-bus is always the responsibility of master devices;each master generates its own clock signals when transferring data on the bus. Bus clocksignals from a master can only be altered when they are stretched by a slow slave deviceholding down the clock line or by another master when arbitration occurs..[8]

I2C Standard Communication ProtocolThis section will explain a complete I2C data transfer emphasizing data validity, information types, byte formats, and acknowledgment. Typical I2C protocol data transfer frame. The important frame components are the START/STOP conditions, Slave Address, and Data with Acknowledgment. This Frame structure remains constant except for the number of data bytes transferred and the transmission direction .It can be seen that all functionality except Acknowledgment is generated by the Master and current slave.[8]

(Source:The I2C-Bus and How to Use It (Including Specification) Philips Semiconductors [2])Data validity:The bit transfer protocol that must be maintained on the I2C-bus. The data on the SDA line must be stable during the HIGH period of the SCL clock. The HIGH or LOW state of SDA cans only change when the clock signal on the SCL is LOW. In addition, these bus lines must meet required setup, hold and rise/fall times prescribed in the timing section of the I2C protocol specifications always affects the Master, Transmitter and Receiver.Master every byte transfer, the Master must generate an acknowledge related clock pulse. this clock pulse is indicated as the 9th bit and labeled ``ACK''.Following the 8th data bit transmission, the active Transmitter must immediately release the SDA line enabling it to float HIGH. To receive another data byte, the Receiver must verify successful receipt of the previous byte by generating an acknowledgment.

An acknowledge condition is delivered when they Receiver drives SDA LOW so that it remains stable LOW during the HIGH period of the SCL ACK pulse. Conversely, a not acknowledge condition is delivered when the Receiver leaves SDA HIGH. Setup and hold times must always be taken into account and maintained for valid communications. SEND_BYTE and RECV_BYTE subroutines described later evaluate and/or generate acknowledgment conditions.[8]

11 of 40

SDA

Data line stable; Data validSCL

Change of data allowed

(Source:The I2C-Bus and How to Use It (Including Specification) Philips Semiconductors [2])START and STOP Conditions Within the procedure of the I2C bus, unique situations arise which are defined as START (S) and STOP (P) conditions. START: A HIGH to LOW transition on the SDA line while SCL is HIGH STOP: A LOW to HIGH transition on the SDA line while SCL is HIGH The master always generates START and STOP conditions. The bus is considered to be busy after the START condition. The bus is considered to be free again a certain time after the STOP condition. The bus stays busy if a repeated START (Sr) is generated instead of a STOP condition. In this respect, the START (S) and repeated START (Sr) conditions are functionally identical. The S symbol will be used as a generic term to represent both the START and repeated START conditions, unless Sr is particularly relevant. Detection of START and STOP conditions by devices connected to the bus is easy if they incorporate the necessary interfacing hardware. However, microcontrollers with no such interface have to sample the SDA line at least twice per clock period to sense the transition.[8]

Start ConditionStop ConditionSCLSCLSDASDA

(Source:F. Leens, An Introduction to I2C and SPI Protocols, IEEE Instrumentation & Measurement[8])Control SignalsSTART and STOP conditions are used to signal the beginning and end of data communications. A Master generates a START condition (S) to obtain control of afree I2C-bus by forcing a HIGH to LOW transition on the SDA line while maintaining SCL in its HIGH state. This condition is generated during software emulation in the MASTER_CONTROLLER subroutine described in another section. Again, START conditions may be generated by a Master only when the I2C-bus is free. This free bus state exists only when no other Master devices have control of the bus (i.e. both SCL and SDA lines are pulled to their normal HIGH state).Upon gaining control of the bus, the Master must transfer data across the system. After a complete data transfer, the Master must release the bus by generating a STOP (P) condition. The SEND_STOP subroutine described in a later section ends data communications by sending an I2C STOP.[8]

Data TransfersThe Slave address and data being transferred across the bus must conform to specific byte formats. The only byte transmission requirement is that data must be transferred with its Most Significant Bit (MSB) first. However, the number of bytes that can be transmitted per transfer is unrestricted. For both Master Transmit/Receive, the MASTER_CONTROLLER subroutine described in a later section performs these functions. From Figure 4, it can be seen that the Slave address is one byte made up of a unique 7-bit address followed by a Read or Write data direction indicator bit. The Least Significant Bit (LSB) data direction indicator always determines the direction of the message and type of transfer being requested by the Master_ either Slave Receive or Slave Transmit. If the Master requests the Slave Receive functionality, the LSB of the addressed Slave would be set to ``0'' for Write. Therefore, them aster would Transmit or Write information to the selected Slave. On the other hand, if the Master was requesting the Slave Transmit functionality, the LSB would be set to ``1'' for Read. As a result, the Master would Receive or Read information from the Slave. SEND_DATA and RECV_DATA subroutines described later send and receive data bytes across the bus.[8]Address RecognitionWhen an address is sent from the controlling Master, each device in a system compares the first 7 bits after the START condition with its predefined unique Slave address. If they match, the device considers itself addressed by the Master as either a Slave-Receiver or Slave-Transmitter, depending upon the data direction indicator. Due to the bus's serial configuration, only one device at a time may be addressed and communicated with at any given moment.[8]

Acknowledge (ACK) and Not Acknowledge (NACK)

To ensure valid and reliable I2C-bus communication, an obligatory data transfer acknowledgment procedure was devised. How acknowledgment always affects the Master, Transmitter and Receiver. Master every byte transfer, the Master must generate an acknowledge related clock pulse. In Figure 1, this clock pulse is indicated as the 9th bit and labeled ``ACK''. Following the 8th data bit transmission, the active Transmitter must immediately release the SDA line enabling it to float HIGH. To receive another data byte, the Receiver must verify successful receipt of the previous byte by generating an acknowledgment. An acknowledge condition is delivered when the Receiver drives SDA LOW so that it remains stable LOW during the HIGH period of the SCL ACK pulse. Conversely, a not acknowledge condition is delivered when the Receiver leaves SDA HIGH. Set-up and hold times must always be taken into account and maintained for valid communications. SEND_BYTE and RECV_BYTE subroutines described later evaluate and/or generate acknowledgment conditions.[8]

Figure: Acknowledge (ACK), Not Acknowledge (NACK)(Source:F. Leens, An Introduction to I2C and SPI Protocols, IEEE Instrumentation & Measurement[8])ArbitrationMultiple masters can synchronize their clocks, for example during arbitration. When bus capacitance affects the bus rise or fall times the master will also adjust its timing in a similar way If there are two masters on the same bus, there are arbitration procedures applied if both try to take control of the bus at the same time. When two chips try to start communication at the same time they may even generate a few cycles of the clock and data that match, but eventually one will output a low when the other tries for a high. The low wins, so the loser device withdraws and waits until the bus is freed again. Once a master (e.g., microcontroller) has control, no other master can take control until the first master sends a stop condition and places the bus in an idle state.[8]

(Source.Leens, An Introduction to I2C and SPI Protocols, IEEE Instrumentation &Measurement[7])Data FormatsAny I2C device can be attached to the common I2C bus and they talk with each other, passing information back and forth. Each device has a unique 7-bit or 10-bit I2C address. For 7-bit devices, typically the first four bits are fixed, the next three bits are set by hardware address pins (A0, A1, and A2) that allow the user to modify the I2C address allowing up to eight of the same devices to operate on the I2C bus. These pins are held high to VCC, sometimes through a resistor, or held low to GND. Each node has a unique 7 (or 10) bit address Peripherals often have fixed and programmable address portions Addresses starting with 0000 or 1111 have special functions:- 0000000 Is a General Call Address 0000001 Is a Null (CBUS) Address 1111XXX Address Extension 1111111 Address Extension Next Bytes are the Actual Address

(Source:I2CBITS.ASM, G. Goodhue, Philips Semiconductors[1])R/Wr0 Slave written to by Master1 Slave read by MasterACK Generated by the slave whose address has been output.READ AND WRITE I2C:The last bit of the initial byte indicates if the master is going to send (write) or receive (read) data from the slave. Each transmission sequence must begin with the start condition and end with the stop condition. On the 8th clock pulse, SDA is set high if data is going to be read from the other device, or low if data is going to be sent (write). During its 9th clock, the master releases SDA line to accomplish the Acknowledge phase. If the other device is connected to the bus, and has decoded and recognized its address, it will acknowledge by pulling the SDA line low. The responding chip is called the bus slave.Master writing to a Slave (figur1)Master is transmitter of data and Slave is receiver of dataMaster reading from a Slave (figur2): Master is Receiver of data and Slave is Transmitter of data.

Figure(1):

1Figure(2)

(source:A.K. Oudjida et al, Master-Slave Wrapper Communication Protocol: A Case Study, Proceedings of the 1st IEEE International Computer Systems and Information Tec-hnology Con-ference [6])

START byte:Microcontrollers can be connected to the I2C-bus in two ways. A microcontroller with anon-chip hardware I2C-bus interface can be programmed to be only interrupted by requestsfrom the bus. When the device does not have such an interface, it must constantly monitorthe bus via software. Obviously, the more times the microcontroller monitors, or polls thebus, the less time it can spend carrying out its intended function.[8]Bus clear

In the unlikely event where the clock (SCL) is stuck LOW, the preferential procedure is toreset the bus using the HW reset signal if your I2C devices have HW reset inputs. If theI2C devices do not have HW reset inputs, cycle power to the devices to activate themandatory internal Power-On Reset (POR) circuit.If the data line (SDA) is stuck LOW, the master should send nine clock pulses. The devicethat held the bus LOW should release it sometime within those nine clocks. If not, thenuse the HW reset or cycle power to clear the bus[8].

Type of I2C Implementations

Byte Oriented Interface Data is handled one byte at a a time Processor interprets a status byte when an event occurs For instance Philips 8xC554, 8xC591 Bit Oriented Interface Processor is involved in every bus event when the interface is not Idle Bit Banged Implemented completely in software on 2 regular I/O pins of the microcontroller Works for single master systems Not recommended for Slave devices or Multimaster systems

The official I2C bus protocol supports three modes of transfer rates:

Standard Mode Up to 100 Kbps Fast Mode Up to 400 Kbps High-Speed Mode Up to 3.4 Mbps

Electrical connections of I2C-bus devices to the bus lines:

Pull-up resistor sizing

The bus capacitance is the total capacitance of wire, connections and pins. This capacitance limits the maximum value of Rp due to the specified rise time. Shows Rp(max) as a function of bus capacitance.Consider the VDD related input threshold of VIH = 0.7VDD and VIL = 0.3VDD for thepurposes of RC time constant calculation. Then V(t) = VDD (1 et / RC), where t is thetime since the charging started and RC is the time constant.V(t1) = 0.3 VDD = VDD (1 et1 / RC); then t1 = 0.3566749 RCV(t2) = 0.7 VDD = VDD (1 et2 / RC); then t2 = 1.2039729 RCT = t2 t1 = 0.8473 RCshows maximum Rp as a function of bus capacitance for Standard-, Fast- and Fast-mode Plus. For each mode, the Rp(max) is a function of the rise time maximum (tr) and the estimated bus capacitance (Cb)[1]

Rp(max)=Tr/0.8653*Cb

(Source: F. Leens, An Introduction to I2C and SPI Protocols, IEEE Instrumentation & Measurement Magazine [8)]

Input leakageThe maximum HIGH level input current of each input/output connection has a specifiedmaximum value of 10 A. Due to the required noise margin of 0.2VDD for the HIGH level,this input current limits the maximum value of Rp. This limit depends on VDD.[1]

Higher drive outputs

If higher drive devices like the PCA96xx Fast-mode Plus or the P82B bus buffers areused, the higher strength output drivers sink more current which results in considerablyfaster edge rates, or, looked at another way, allows a higher bus capacitance. Refer toindividual component data sheets for actual output drive capability. Repeat the calculationabove using the new values of Cb, Rp, tr and tf to determine maximum frequency. Bear inmind that the maximum rating for fSCL as specified in (100 kHz, 400 kHz and1000 kHz) may become limiting.[1]

Implementation of I2c master controller on FPGA using VHDL:Its main function will be, to understand the control register transmitted by PC and convert it into SPI control signals. The functional block in. Demonstrates the overview of the functionality of the I2C master controller.Fig.1.

Fig.1. Functional Block(source: file:http//www.springer.com)

II Register DescriptionThere are 6 control registers and a data register. Each control register corresponds to SPI control register. The first register corresponds to SPI status register. Second set of 8 bits are dedicated for write operations which also includes interrupt signals for write and read operation Third set of 8 bits are dedicated to read operations only 2 bits of this registers are used as bus busy and abort read signals and rest of the bits are tied to 0.Fourth and fifth set of 8 bits corresponds to 1st control register and 2nd control register of SPI respectively. Finally sixth set of 8 bits corresponds to baud rate register of SPI.[6]

III ImplementationThe PC connected to the controller sends data serially and every 8 bits corresponds a value specified by the i2cprotocol.The address and the chip select signal selects the I2C device. In this design both chip select and address of the device are default to 1, as the design is for a specific slave only. Every set of 8 bits which corresponds to a control registers which controls the flow of data, is stored in registers. A counter is initialized after successful transmission of 8 bits from the PC to the controller. As the complete set of control registers are transmitted, all the values of the registers are inverted and stored in a 32 bit register.32 bit registers are decided on the basis of SPI slave as there are only 4 control register before the data register. Every bit of the 32 bit register corresponds to a specific signal of SPI protocol. Once the 32 bit register is fed by the corresponding registers, the serial transmission takes place, which is the MOSI input of the SPI slave. A clock signal is also transmitted to the SPI slave as SCLK which acts the main clock for the slave.[6]IV ResultsThe following Fig.is the simulation results of I2C master controller.This result shows successful storage of data transmitted by the master on the mentioned address location.[6]

Figure: MULTI SIM STIMULATION

Figure: MULTI SIM STIMULATION(Source:A.K. Oudjida, M.L. Berrandjia, R. Tiar, A.Liacha, K. Tahraoui, FPGA Implementation of I2c & SPI Protocols: A Comparative Study Electronics, Circuits, and Systems[6])ImplementI2C Serial Communication Using Intel MCS-51MicrocontrollersMCS-51 Hardware Requirements:The I2C protocol requires open-drain device outputs to drive the bus. To satisfy this specification, Port 0 on the Intel MCS-51 device was chosen. By using open-drain Port 0, no additional hardware is required to successfully interface to the I2C-bus. However, since Port 0 Is designated as the I2C interface, it can no longer be used to interface with External Program Memory. In order for a MCS-51 device to communication in this environment,ASM51 software emulation modules were developed. This software can only execute out of Internal Memory. Port 0 is now configured for Input/output functionality. The diagrams the necessary hardware connections of the development circuit. Internal Memory execution is accomplished by connecting the External Access (EA) DIP pin 31 to VCC. The capacitor attached to RESET DIP pin 9 implements POWER ON RESET. While the capacitors and crystal attached to XTAL1&2enable the on-chip oscillator, additional decoupling capacitors can be added to clean up any system noise. The ASM51 software emulation modules described in this application note will occupy approximately540 bytes of internal memory. The device's remaining memory may be programmed with user software. [3]MCS-51 I2C Software Emulation ModulesWhen devices like the MCS-51 do not incorporate a non-chip I2C port, I2C functionality can be achieved through software emulation. The following software modules are based upon three distinct tasks: bus monitoring, time delays and bus control. Each task conforms to the I2C protocol as specified by Philips Semiconductors. The software modules designed to implement I2Cfunctionalityare comprised of macros and subroutines, each independently developed, yet both networked to achieve a desired system function. For example, the use of macros was favored to implement certain timing delay loops. Macros are extremely flexible and can be changed to construct delays of varying lengths throughout the software. On the other hand, subroutines are verified routines that require no additional changes. To operate the bus at different frequencies, only the specific macros must be changed, not the predefined subroutines. The following ASM51 macros and sub routines are for Master-Slave system controls.[3]Macro NamesFunctions

DELAY_3_CYCLESDelay loop for X secondswhere X e timeper cycle * 3

DELAY_4_CYCLESDelay loop for X secondswhere X e timeper cycle * 4

...

DELAY_8_CYCLESDelay loop for X secondswhere X e timeper cycle * 8

RELEASE_S_CLHIGHReleases the SCL line HIGH and waits forany clock stretching requestsfrom peripheral devices

Subroutine NamesFUNCTIONS

MASTER_CONTROLLERSends an I2C startcondition and Slave Addressduring both aMaster Transmit andReceive

SEND_DATASends multiple databytes during a MasterTransmit

SEND_BYTEsends one data byte lineduring a Master Transmit

SEND_MSGSends a message acrossthe I2C bus using a predefinedformat

RECV_DATAReceives multiple databytes from an addressedSlave during a Master receive

RECV_BYTEReceive one data byteduring a Master Receive

RECV_MSGReceives a messagefrom the I2C bus usinga predefined format

TRANSFERCopies EPROM programmeddata into RegisterRAM

SEND_STOPSend an I2C STOP conditionduring both aMaster Transmit/Receive

[3]

I2C Software Emulation Performance The Intel MCS-51 product line can successfully implement the I2C Master Controller functionality while maintaining data integrity and reliable performance. The system outlined in Figure 1 was evaluated for maximum bus performance and adherence to all I2C-bus specifications. Performance characterization was conducted at various crystal speeds on all devices listed in the MCS-51 Hardware Requirements section of this application note.WhendesigningI2C software emulation systems, keep in mind that the designer has the flexibility to implement large frequency ranges up to the I2C-bus maximum. However, by making software changes to adjust bus frequencies, the newly modified program may no longer meet required specifications and desired reliability standards. Therefore, designers should first always take into consideration the bus performance level they want to reach. After deciding this, an appropriate crystal can be chosen to achieve that implementation speed.[3] The table below gives a few examples of system performance for two of the MCS-51 devices:MCS-51 Devices

Crystal speedI2C BusMaximumPerformance

8751BH 87C51 (FX-Core12 MHZ24 MHZ66.7 KHZ80.0 KHZ

I2C Designer Benefits Functional blocks on the block diagram correspond with the actual ICs; designs proceed rapidly from block diagram to final schematic. No need to design bus interfaces because the I2C bus interface is already integrated on-chip. Integrated addressing and data-transfer protocol allow systems to be completely software-defined. The same IC types can often be used in many different applications. Design-time reduces as designers quickly become familiar with the frequently used functional blocks represented by I2C bus compatible ICs. ICs can be added to or removed from a system without affecting any other circuits on the bus. Fault diagnosis and debugging are simple; malfunctions can be immediately traced. Assembling a library of reusable software modules can reduce software development time.[2]I2C Manufacturers Benefits The simple 2-wire serial I2C bus minimizes interconnections so ICs have fewer pins and there are not so many PCB tracks; result - smaller and less expensive PCBs The completely integrated I2C bus protocol eliminates the need for address decoders and other glue logic The multi-master capability of the I2C bus allows rapid testing/alignment of end-user equipment via external connections to an assembly-line Increases system design flexibility by allowing simple construction of equipment variants and easy upgrading to keep design up-to-date The I2C bus is a de facto world standard that is implemented in over 1000 different ICs (Philips has > 400) and licensed to more than 70 companies [2].I2C Product CharacteristicsPackage Offerings Typically DIP, SO, SSOP, QSOP, TSSOP or HVQFN packagesFrequency Range Typically 100 kHz operation Newer devices operating up to 400 kHz Graphic devices up to 3.4 MHzOperating Supply Voltage Range2.5 to 5.5 V or 2.8 to 5.5 V Newer devices at 2.3 to 5.5 V or 3.0 to 3.6 V with 5 V toleranceOperating temperature range Typically -40 to +85 C Some 0 to +70 C Hardware address pins Typically three (AO, A1, A2) are provided to allow up to eight of the identical device on the same I2C bus but sometimes due to pin limitations there are fewer address pins,[2]

APPLICATION: TV reception: Provides TV tuning and reception Radio reception: Provides radio tuning and reception Audio Processing Infra-Red control DTMF: Dual Tone Multiple Frequency LCD display control: Provides power to segments of an LCD that are controlled via I2C bus LED display control: Provides power to segments of an LED that are controlled via I2C bus Real time clocks and event counters: counting the passage of time, chronometer, periodic alarms for safety applications, system energy conservation, time and date stamp for point of sales terminals or bank machines. General Purpose Digital Input/Output (I/O): monitoring of YES or NO information, such as whether or not a switch is closed or a tank overflows; or controlling a contact, turning on an LED, turning off a relay, starting or stopping a motor, or reading a digital number presented at the port (via a DIP switch, for example). Bus Extension/Control: expends the I2C bus beyond the 400 pF limit, allows different voltage devices on the same I2C bus or allows devices with the same I2C address to be selectively addressed on the I2C bus. Analog/digital conversion: measurement of the size of a physical quantity (temperature, pressure), proportional control; transformation of physical analog values into numerical values for calculation. Digital/analog conversion: creation of particular control voltages to control DC motors or LCD contrast. RAM: Random Access Memory EEPROM: Electrically Erasable Programmable Read Only Memory, retains digital information even when powered down Hardware Monitors: monitoring of the temperature and voltage of systems Microprocessors: Provides the brains behind the I2C bus operation. [9]

EXAMPLES:Tv receptionThe frequency range of most of the newer I2C devices is up to 400 kHz and we are moving to 3.4 MHz for future devices where typical uses would be in consumer electronics where a DSP is the master and the designer wants to rapidly send out the I2C information and then move on to other processing needs. I2C devices are designed in the process that allows best electrical and ESD performance and are manufacture of The SAA56xx family of microcontrollers are a derivative of the Philips industry-standard 80C51 microcontroller and are intended for use as the central control mechanism in a television receiver.[10]

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LCD Display Driver:The operating range of most of the newer CMOS devices is 2.3 to 5 V to allow operation at the 2.5, 3.3 and 5V nodes. Some processes restrict the voltage range to the 3.3 V node. Most customers have moved from 5 V and are now at 3.3 V but several are moving rapidly to 2.5 V and even 1.8 V in the near future. We are working on next generation general purpose devices to support 1.8 V operation and currently have some LCD display drivers that operate down to 1 V.The LCD display driver is a complex LCD driver and is an example of how "complete" a system an I2C chip can be - generates the LCD voltages, adjusts the contrast, temperature compensates, stores the messages, has CGROM and RAM etc The LCD segment driver is a less complex LCD driver (e.g., just a segment driver). Philips focus is for large volume consumer display apps, which is right now B&W and color STN LCD displays and in near future it will be TFT and OLED (organic LED displays). The OLED drivers will most probably not be useable with conventional LEDs.[10]

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Conclusionserial communication system, you have the option of using the Intel MCS-51 ProductThe design of i2c master controller has immense applications in future as the number of devices connected to a system is only going to increase. So there is always a need for a system which supports multiple protocols. In all these situations, I2C master controller acts as a great support and will be a key in future design to support multiple parallel functions. I2C master controller is successfully designed in VHDL and simulated in Model SIM. Simulation results verify that the communication has been established between the microprocessor and the controller. Data processed and the output has been successfully verified as per SPI slave input. The design meets timing constraints and there are no timing violations. And all these have been achieved with minimal utilization of resources. Intel MCS-51 microcontroller scan be successfully interfaced to an I2C-bus system as a Master controller. The interface communicates by ASM51 software emulation modules that have been tested on a wide array of I2C devices ranging from serial RAMS, Displays and a DTMF generators. REFERENCES

[1] I2CBITS.ASM, G. Goodhue, Philips Semiconductors, August 1992[2] The I2C-Bus and How to Use It (Including Specification), Philips Semiconductors, January 1992.[3] I2C Peripherals for Microcontrollers, Philips Semiconductors,1992 Data Handbook.[4] OM1016 I2C Evaluation Board, E. Rodgers and G. Moss, Philips Components Applications Lab Auckland, New Zealand.[5] Programming the I2C Interface, Mitchell Kahn, SeniorEngineer, Intel Corporation.[6] A.K. Oudjida, M.L. Berrandjia, R. Tiar, A.Liacha, K. Tahraoui, FPGA Implementation of I2c & SPI Protocols: A Comparative Study Electronics, Circuits, and Systems, 2009. ICECS 2009[7] A.K. Oudjida et al, Master-Slave Wrapper Communication Protocol: A Case Study, Proceedings of the 1st IEEE International Computer Systems and Information Tec-hnology Con-ference ICSIT05, pp 461-467, 19-21 July 2006 Algiers, Algeria.[8] F. Leens, An Introduction to I2C and SPI Protocols, IEEE Instrumentation & Measurement Magazine, pp. 8-13, February 2009.[9] J.M. Irazabel& S. Blozis, Philips Semiconductors, I2C-Manual,Application Note, ref. AN10216-0, March 2003.[10] M.D. Anu I2C to SPI Bridge, AN49217 Cypress application note, October 2008.