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Interfacing with the photonic ecosystem in a fabless world
Iñigo Artundo
23rd September 2015
2www.vlcphotonics.com09/24/15
Outline
1. The take off of fabless photonic integration
2. The fabless ecosystem
3. Interfacing with the different partners
4. Take-aways and recommendations
3www.vlcphotonics.com09/24/15
Pioneers in photonic integration
• Optical chip design house, consultant and tester.
• 12+ years in the field of optics and integrated photonics.
• Expertise in telecom/datacom, quantum, sensing, microwave
• Know-how in all main PIC technologies (SOI, InP, SiN, PLC, etc.)
• Brokers for +25 partners in fabrication and packaging.
4www.vlcphotonics.com09/24/15
The take off of photonic integration
Chip integration:● Size & weight reduction● Higher robustness and yield● Manufacturing cost decrease● Scale up complexity
Optical systems are...● Bulky and heavy● Complex to assemble & align● Expensive
Enabler for market revolutions:● Optical interconnects for datacom● Optical telecom for FTTH● Biomedical diagnostics● Fiber sensing
+
Experience from electronic integration:● Knowledge● Infrastructure● Business models
+
5www.vlcphotonics.com09/24/15
Development cycle of a PIC
System concept
Optical architecture
Chip architecture
Chip design
Performance simulation
Mask layout + DRC
Manufacture
Packaging
Chip testing
Si, SOIInP / GaAs
PLCSi3N4 ...
6www.vlcphotonics.com09/24/15
Horizontal fabless integration
Vertical model
✔✔ State-of-the art device✘✘ Huge investment
Horizontal model
Device test
Chip package
Chip test
Chip manufacture
Chip design
Concept / IP
✔ Performing device
✔✔ Low Investment
✘ Interfacing with external partners
Device test
Chip package
Chip manufacture
Chip design
Concept / IP
Chip test 1999 2012
28%
7www.vlcphotonics.com09/24/15
The rise of the PIC fabless model
1970 1980 1990 2000 2010 2020
Market value >$30B Market value <$8B
R&DInvestment
100 Gb/s TX/RXInP, 2004
40 Gb/s AOCSOI, 2007
Opticalcomponent
Manufacturers
LasersPhotodiodes
Passives
SplittersAWGsVOAs
Beam combinerSi
3N
4, 2012
Investment
FBG interrogatorInP, 2015
OCTSOI, 2015
FAB
LES
S
VER
TIC
AL
www.vlcphotonics.com
The birth of generic PIC manufacturing platforms
(6M€, 2004-2008)
ESSenTIAL
Silicon photonics (SOI) Indium Phosphide (InP)
(1M€, 2008-2011)
(1.6M€, 2011-2014)
(5.6M€, 2009-2012)
(13.2M€, 2010-2014)
www.vlcphotonics.com
The birth of generic PIC manufacturing platforms
(6M€, 2004-2008)
ESSenTIAL
Silicon photonics (SOI) Indium Phosphide (InP)
(1M€, 2008-2011)
(1.6M€, 2011-2014)
(5.6M€, 2009-2012)
(13.2M€, 2010-2014)
(private funding, 2011-2015)
IP-IMI +...
10www.vlcphotonics.com09/24/15
The fabless photonic ecosystem
Si, SOIInP / GaAs
PLCSi3N4 ...
OpticalEngineering
Consultancies
Softwareproviders
Design houses
Foundries
Testers
Packagers
11www.vlcphotonics.com09/24/15
Why and How to interface
Optical EngineeringConsultancies
Softwareproviders
Design housesFoundries
Testers
Packagers
YOU
12www.vlcphotonics.com09/24/15
Why to outsource?
Do you have resources in-house?
YESNO
Is this yourcore business?
Do you have allrequired know-how& infrastructure?
YES
IN-SOURCETiming isessential?
NO
TRAIN &ADAPT
YES
OUT-SOURCE
YES
NO
NO
Can you recruit & equip in time?
INVEST, HIRE & BUYIs this a long
term demand?
INVEST & OUT-SOURCE
NO YES
NO YES
INVEST & OUT-SOURCE
13www.vlcphotonics.com09/24/15
How to interface
Design house
YOU
Optical EngineeringConsultancy
Tester
Foundry
Packager
Softwareprovider Software
provider Foundry
Packager
YOU
Optical EngineeringConsultancy
Tester
Designer
Foundry
Packager
YOUSoftware
provider 1
Tester
Softwareprovider 2
Designer
Design house 2
Foundry 1
YOUFoundry 2
Design house 1
Tester
Packager
Softwareproviders
14www.vlcphotonics.com09/24/15
Interfacing when fabless prototyping
30-100k€ / 1 year
Every interfacing step can be a weak link in the chain.
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Interfacing with the links in the chain
Engineer
Designer
Foundry
Chip tester
Packager
Device tester
Material and fab selection, performance info, IP check, techno-economics.
Clear definition of needs, background information, trade-off tolerances.
GDS files, design simulation and trade-offs report.
Performance specs, layout requirements, process info, DoEs, delivery date.
Design manual and PDK, fab tolerances, pricing, design delivery, backend options, protected IP, guarantees.
Fabricated dies, metrology report.
Characterization report, all dies.Original & spare dies, chip description, interfacing layout, optical measurements.
Original & spare dies, package specs, (parts).
Packaged dies, remaining dies, packaging report, (remaining parts).
Packaged device, description, interfacing diagram, measurement specifications.
Test report, original packages (even damaged).
16www.vlcphotonics.com09/24/15
Interface risks when fabless prototyping
30-100k€ / 1 year
ERROR IN PACKAGING
=3+ months
30% investment
17www.vlcphotonics.com09/24/15
Interface risks when fabless prototyping
30-100k€ / 1 year
ERROR IN DESIGN
=8+ months
90% investment
18www.vlcphotonics.com09/24/15
Advices for successful fabless operation
Minimize risks at early stages.
Learn before doing, and stay updated.
Be ready to invest, and in-source only your core parts.
Ask for frequent and abundant feedback at all stages.
Engage deeply with reactive and professional partners.
The fabless PIC ecosystem is mature enough, but complex and quickly evolving.
Thank you for your attention
For all your photonic integration needs
www.vlcphotonics.com@vlcphotonics
