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© IMEC, CEA-LETI
Silicon Photonic IC Fabless Access Broker
Support Action
FP7 Grant Agreement 224232
Deliverable 3.1 – Roadmap Y2
Due date of deliverable: June 30 2009, 2010
Actual submission date: April 19, 2010
Start date of project: 1 September 2008
Duration: 36 months
Work package 3: Roadmap
Project co-ordinator:
Name: IMEC
Contact person: Pieter DUMON
Tel: +32 (0)9 264 3448
Fax: +32 (0)9 264 3593
E-mail: [email protected]
Project website address: www.epixfab.eu/photonfab
Project co-funded by the European Commission within the seventh framework programme
Dissemination Level
PU Public x PP Restricted to other programme participants (including Commission Services) RE Restricted to a group specified by the consortium (including the Commission Services) CO Confidential
PhotonFAB D3.1 Roadmap
© IMEC, CEA-LETI 2
April 2010
ROADMAP
FOR ACCESS TO SILICON PHOTONIC
TECHNOLOGIES
Contact: Pieter DUMON imec [email protected] Tel: +32-9-2643448
PhotonFAB D3.1 Roadmap
© IMEC, CEA-LETI 3
Contents 1 Executive summary ............................................................................................................................... 5
2 Design .................................................................................................................................................... 7
2.1 Design automation availability and needs .................................................................................... 7
2.1.1 Design flow and software ..................................................................................................... 7
2.1.2 Design libraries ...................................................................................................................... 9
2.1.3 Known work in progress ..................................................................................................... 10
2.1.4 Identified user needs .......................................................................................................... 11
2.2 Training availability and needs ................................................................................................... 11
2.2.1 Current status ..................................................................................................................... 11
2.2.2 Identified needs .................................................................................................................. 12
2.3 Design service availability and needs .......................................................................................... 12
3 Process technology, MPW and manufacturing access ....................................................................... 13
3.1 Current state ............................................................................................................................... 13
3.2 Detailed description of MPW wafers providers for silicon photonics ........................................ 14
3.2.1 IMEC (www.imec.be) .......................................................................................................... 14
3.2.2 CEA-LETI (www-leti.cea.fr) .................................................................................................. 15
3.2.3 IME (http://www.ime.a-star.edu.sg) .................................................................................. 16
3.3 Other potential providers ........................................................................................................... 18
3.3.1 IHP ....................................................................................................................................... 18
3.3.2 VTT (www.vtt.fi) .................................................................................................................. 18
3.3.3 Austriamicrosystems (www.austriamicrosystems.com)..................................................... 20
3.3.4 STMicroelectronics .............................................................................................................. 21
3.4 Chip-scale services ...................................................................................................................... 21
3.4.1 Nanostructuring platform ................................................................................................... 22
3.4.2 AMO .................................................................................................................................... 22
3.4.3 VTT ...................................................................................................................................... 22
3.4.4 NTT ...................................................................................................................................... 23
3.4.5 US National Nanotechnology Infrastructure Network (NNIN) ............................................ 23
3.5 MPW service centers .................................................................................................................. 23
3.5.1 Europractice ........................................................................................................................ 23
PhotonFAB D3.1 Roadmap
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3.5.2 CMP (Multi Project Circuits) ................................................................................................ 24
3.5.3 CMC ..................................................................................................................................... 24
3.5.4 MOSIS .................................................................................................................................. 24
3.6 Manufacturing ............................................................................................................................ 26
3.6.1 Current state ....................................................................................................................... 26
3.6.2 User needs .......................................................................................................................... 26
4 Packaging and test .............................................................................................................................. 28
4.1 Dicing, resizing ............................................................................................................................ 28
4.2 Packaging availability and needs................................................................................................. 28
4.2.1 Generic versus customized packaging ................................................................................ 28
4.2.2 Packaging providers ............................................................................................................ 29
4.2.3 Spot size convertors/interposers ........................................................................................ 32
4.3 Testing ......................................................................................................................................... 33
4.3.1 Current status ..................................................................................................................... 33
4.3.2 Identified needs .................................................................................................................. 33
5 Roadmap ............................................................................................................................................. 33
5.1 Technologies available for fabless prototyping .......................................................................... 34
5.2 Design .......................................................................................................................................... 36
5.3 Handling of small scale users ...................................................................................................... 37
5.4 Manufacturing ............................................................................................................................ 38
5.5 Test .............................................................................................................................................. 38
5.6 Wafer handling and packaging ................................................................................................... 39
5.7 Training ....................................................................................................................................... 39
ANNEX 1: Roadmap of technology introduction within ePIXfab ................................................................ 41
PhotonFAB D3.1 Roadmap
© IMEC, CEA-LETI 5
1 Executive summary
This roadmap has the ambition to map out the available access to silicon photonics technologies,
products and services and identifies the future needs for access for fabless R&D actors and companies.
Based on input from supplier and user side, the possibilities to implement access to these technologies,
products and services to small fabless users are studied and advice is formulated.This work was
undertaken by the FP7 PhotonFAB project in order to obtain a better view on the future of access to
silicon photonics technologies, and to support the evolution of the ePIXfab service (www.epixfab.eu).
The domains covered in this roadmap are:
Technology for silicon photonic ICs, both wafer scale and sample scale.
Design automation, design kits and design services
Prototyping and manufacturing access: MPW, small volume and volume manufacturing
Post-processing, packaging and test approaches
The roadmap was composed based on:
input from a wide range of technology & service providers
input from users and potential users through an on-line questionnaire
feedback from the many contacts ePIXfab has with users, potential users and suppliers.
This roadmap aims to help to identify additional R&D needed on the supply chain to enable the
matching between customer needs and technology/service availability. With the roadmap as a
cornerstone, ePIXfab has can help drive investment decisions.
Based on this roadmap, PhotonFAB will also set out the future business plan for ePIXfab:
evolution of technology and services offered
evolution towards a self-sustainable operation at the current technology & service level
The main recommendations spanning 2010-2012 are:
- intensified collaboration is necessary between fabs, technology providers, software providers
and support centers aggregating demand of small customers.
- wafer test procedures and mechanisms should be established.
- circuit design automation as well as software interoperability should be improved by in order
to establish an advanced design flow.
- collaboration between ePIXfab and other support centers aggregating demand of small
customers must be investigated.
PhotonFAB D3.1 Roadmap
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The rest of this document is structured as follows:
- Sections 2, 3 and 4 describe the available technologies and services and the needs in detail
- Section 5 gives an overview of the state of the art and roadmap
Abbreviations and codes
The following abbreviations are used in this document:
BEOL Back-End Of Line
FEOL Front-End Of Line
LVM Low Volume Manufacturing
MPW Multi Project Wafer
MtM More-than-Moore
NP Non-profit
PDK Process Design Kit
TSV Through Silicon Via
DRC Design Rule Checking
LVS Layout Versus Schematic
EM Electro-Magnetic
IP Intellectual Property
GDS Calma GDSII mask file format
EDA Electronic Design Automation
API ?
The following color codes are used:
Overview of tables
Table 1: overview of design software for silicon photonics ......................................................................... 8
Table 2: design flow components and current state .................................................................................... 9
Table 3: software for photonics design available from Europractice Software ........................................... 9
Table 4: overview of training availability .................................................................................................... 11
Table 5: technologies available in MPW ..................................................................................................... 34
Table 6: technologies without MPW access ............................................................................................... 35
Table 7: sample scale technologies with at least prototyping access ........................................................ 35
Table 8: availability of training .................................................................................................................... 40
Available
Early stage
Not available
PhotonFAB D3.1 Roadmap
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2 Design
2.1 Design automation availability and needs
2.1.1 Design flow and software
The current design flow is schematically shown in Figure 1, and an overview of available design software
is given in Table 1. A relatively simple flow is currently used with little interaction on the software level
between the different stages. Only a few vendors are working on a more integrated flow.
Figure 1: Current silicon photonic IC design flow
A more complete design flow is illustrated in Figure 2.
Figure 2: Future design flow
PhotonFAB D3.1 Roadmap
© IMEC, CEA-LETI 8
An important step towards such more complete design flow is the interoperability of software tools
even from different vendors. Also, it is possible to support the construction of design kits for different
software with the same function only if there exists a way to write a design kit once and be supported
by different tools. Therefore:
o An commonly agreed upon API is necessary to link software tools
o A uniform way to define design kits and libraries is necessary
Area Type Software name Vendor
Simulation Electromagnetic
Fimmwave, Fimmprop, Crystalwave, OmniSim
FieldDesigner, OptoDesigner
OptiFDTD, OptiBPM
MEEP, MPB
CAMFR
BeamPROP, FullWAVE, BandSOLVE, GratingMOD,
DiffractMOD, ModePROP,
Photon Design
PhoeniX BV
OptiWave
MIT
UGent
RSoft
Opto-electronic Cladiss-2D
FieldDesigner TO/EO module
VPI ComponentMaker
Photon Design
PhoeniX BV
VPI Photonics
Optimization Kallistos
MOST
Photon Design
RSoft
Circuit PICWave
ASPIC
OptiSPICE
Photon Design
PhoeniX BV
OptiWave
Material Harold Photon Design
Process FlowDesigner PhoeniX BV
Layout Static CleWin
KLayout
PhoeniX BV
Freeware
Parametric MaskEngineer
DW-2000
IPKISS/PICAZZO
PhoeniX BV
Design Workshop
UGent
Verification DRC Calibre
DIVA, ASSURA
DW-2000 Photonic DRC
Mentor Graphics
Cadence
Design Workshop
FAB PDKs IMEC
LETI
IMEC
LETI
IP libraries UGent PICAZZO library UGent
Table 1: overview of design software for silicon photonics
PhotonFAB D3.1 Roadmap
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Table 2 gives a consolidated state of the art view on the design software:
Schematic design
Simulation EM simulation
Circuit simulation
Extraction
Layout Device layout
Place and route
Verification DRC
LVS
Fab PDKs
IP libraries
Table 2: design flow components and current state
Software availability from Europractice Software for academic R&D
PhoeniX BV MaskEngineer, FlowDesigner,
Optics Lite, Optics Advanced
Design Workshop DW-2000 Photonic Bundle
Cadence IC/Virtuoso
Mentor Graphics Calibre
Table 3: software for photonics design available from Europractice Software
2.1.2 Design libraries
Currently available are:
limited process design kits, with technology settings, design rules, DRC decks for common
software suites for IMEC and LETI technology
various closed design libraries from different R&D actors (e.g. UGent)
extensive generic component libraries (not technology-specific) in major design tools: PhoeniX
MaskEngineer, Design Workshop DW-2000
PhotonFAB D3.1 Roadmap
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2.1.3 Known work in progress
Two major R&D projects are working on design automation aspects:
FP7 HELIOS project:
o Integration of photonic design automation functionality with a Cadence-based design
methodology – development of an OpenAccess compliant software framework
definition
o Development of behavioural level simulation capabilities
o Linking behavioural level with EM simulation level capabilities
FP7 EuroPIC project:
o Development of a Photonic Design Automation API
Within EuroPIC, a Photonic Design Automation (PDA) API is under development for interoperability of
photonics specific design software tools. Any vendor making its software PDA compliant will be able to
interface more easily to tools and engines of others. The PDA covers physical design, layout and circuit
design. While EuroPIC focuses on InP photonic ICs, the problems solved are very similar to those of
silicon photonics
Within Helios, a PDA-OpenAccess interface is created that allows EDA tools to address photonic tools,
engines and libraries.
Vendors involved in this work are PhoeniX Software, Photon Design and Filarete in cooperation with
design companies, IC companies, major research institutes and academic partners.
Integration with EDA software
To enable addition of photonic functionality to an electronic IC design flow, photonics simulation, layout
and verification capabilities should be available from EDA tools:
Accessing photonic design libraries natively from Cadence Virtuoso, Tanner L-Edit, …
Addition of behavioural modeling capabilities to Verilog-A / VHDL-AMS type simulators (e.g.
Spectre)
Accessing photonics engines (EM simulation, layout generation,…) from EDA tools
The OpenAccess API is a EDA community effort to achieve improved interoperability between EDA tools
gaining significant momentum (e.g. Cadence switched to an OpenAccess design database and is
OpenAccess compliant). Therefore, the best path to EDA interoperability may be to make photonic
design tools and libraries OpenAccess compliant.
PhotonFAB D3.1 Roadmap
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2.1.4 Identified user needs
Users indicated needs for
having off the shelf devices ready for use instead of having to redesign them each time from scratch
element libraries with a well defined structure, suitable for incorporation in frameworks
circuit level design is necessary:
o to make it much easier for designers not specialized in (silicon) photonics to step in
o to shorten the design cycle and decrease the design effort
o to increase the chances for first-time-right
o to design more complex circuits.
integration with EDA software is necessary to lower the barriers for electronic IC designers.
2.2 Training availability and needs
2.2.1 Current status
Table 4 gives an overview of the training in silicon photonics available.
Subject Availability
Photonics basics From university programs worldwide
Silicon photonics tutorials ePIXfab
Design software training From the design software vendors
(PhoeniX, Design Workshop)
Silicon photonics technologies ePIXfab
MPW access and supply chain ePIXfab
Design flow and rules ePIXfab
Design training (hands-on) - CMC (Canadian universities)
Table 4: overview of training availability
In addition, work is in progress on new training initiatives:
PhotonFAB is working on a hands-on design extension to its course (fall 2010)
FP7 Helios is working on a silicon photonics training on technology, devices and applications.
This will be in the form of downloadable presentations.
PhotonFAB D3.1 Roadmap
© IMEC, CEA-LETI 12
2.2.2 Identified needs
The PhotonFAB training courses held in October 2009 and March-April 2010 and other feedback clearly
indicate a (world-wide) need for training on access to silicon photonics technologies:
fabrication technology: a basic knowledge of wafer scale fabrication technology is necessary to
improve design capability and the chances for first-time-right. Currently this is partially covered
by the PhotonFAB training.
silicon photonics devices: especially for non-specialists, training on silicon photonics devices
(waveguides, filters, modulators, sources, detectors, fiber I/O ….) is necessary. Currently this is
partially covered by the PhotonFAB training
access: opportunities and procedures for fabless access to wafer and sample scale technologies.
This is covered by the PhotonFAB training
design basics and design rules: training is needed on basics and rules of chip layout as well as
optical design. Layout is currently covered by the PhotonFAB training
hands-on design: hands-on training on specific software and specific design kits for silicon
photonics, from optical design to layout.
2.3 Design service availability and needs
No commercial silicon photonics specific design services are currently available. Major R&D
actors currently act as design services providers, normally linked to a research activity
(component/application development) by that actor.
Several European photonic IC design service providers or product development companies are
active on the market, mainly in glass or III-V technologies.
An environment should be created in which silicon photonics-specific design houses should be
able to start up.
PhotonFAB D3.1 Roadmap
© IMEC, CEA-LETI 13
3 Process technology, MPW and manufacturing access
3.1 Current state
In MPW and prototyping, three types of service centers are discriminated:
MPW providers for silicon photonics – these offer silicon photonics today on wafer scale
(Inter)national MPW centers - some of them are broadening their scope to MEMS, photonics
and other technologies, and provide additional services to specific target groups.
Sample scale prototyping centers – these offer silicon photonics today on sample scale and can
be complementary to wafer scale centers.
On silicon photonics fabrication activities, apart from university small clean rooms, there are not many
players:
Asia: IME with fab service in Singapore, NTT with ebeam facility for own use in Japan, no real
fab in China
US: A small open fab service at Cornell University, BAE with own projects, no support of the
government for an access such as ePIXfab.
Europe: ePIXfab with LETI and IMEC, IHP starting a silicon photonics activity in Germany,
austriamicrosystems starting activity in the HELIOS project
So the public offer on silicon photonics MPW is based on IMEC, LETI and IME technology.
The technologies offered are passive and active device processes.
Design support is labour-intensive, given the design flow deficiencies outline above. A limited
PDK is available.
ePIXfab also offers training to its MPW service, put in place by the PhotonFAB project.
Both MPW centers offer also devices developed by the research institutes (ePIXfab: IMEC, CEA-
LETI; IME).
Major (inter)national MPW centers can offer silicon photonics MPW through the current MPW centers:
CMC offers ePIXfab MPW to its Canadian academic customers already.
Other centers such as Europractice, CMP and MOSIS serve are broadening their scope and could
serve European/US academia specifically.
PhotonFAB D3.1 Roadmap
© IMEC, CEA-LETI 14
Centers for prototyping devices on individual chips (e-beam based): NanoPIX (U. StAndrews, Glasgow
U.), AMO (Germany), Cornell nanofabrication center (US), NRC nanofabrication center (Canada), NTT-
ATN (Japan).
These are offering prototyping of individual devices or small scale circuits to academic or
industrial users, in various modes of operation from very research-like to more foundry-like.
Therefore, they offer a faster turn-around and more flexibility than the wafer scale centers.
The technologies have a higher resolution than what the MPW centers can offer, however the
level of total process stack complexity that can be supported is much less.
3.2 Detailed description of MPW wafers providers for silicon photonics
3.2.1 IMEC (www.imec.be)
IMEC is running a 200mm pilot line with advanced silicon fab tools including 193nm DUV lithography
capable of down to 90nm printing. The fab is running 24/7 with dedicated operation and support teams
and is used for R&D and manufacturing of MtM technologies (specialized electronics, MEMS, photonics).
IMEC has a standardized silicon photonics process now available and offered in ePIXfab MPW with the
following characteristics:
200mm SOI 220nm Si / 2000nm BOX
‘FC’ module (70nm etch) for vertical fiber I/O and passives
‘WG’ module (220nm etch) for ultra-compact passives
Options: top oxide, substrate thinning to 250um, dicing (internal or subcontracted)
Process modules in development include:
advanced passives: high-efficiency fiber I/O
active devices (implant)
route for integration with electronics
These modules will be available from IMEC’s CMORE service starting 2010. Availability in ePIXfab will be
evaluated in 2010.
IMEC’s silicon photonics PDK includes:
mask design rules
mask design guidelines
settings for layout software (Cadence, MaskEngineer, DW2000)
DRC settings for Calibre and DW2000
Template masks
Available standard masks
Example cells
PhotonFAB D3.1 Roadmap
© IMEC, CEA-LETI 15
Additional services offered by IMEC:
CMORE platform: custom process development for MtM technologies and small-volume
manufacturing capability
Design support by INTEC photonics research group (bilateral or funded project)
The short term roadmap of technology introduction within ePIXfab is given in Annex 2
3.2.2 CEA-LETI (www-leti.cea.fr)
LETI is running a 200mm pilot line with advanced silicon fab tools including 193nm DUV lithography
capable of down to 100 nm printing. The fab is running in five shifts with almost continuous operation
with dedicated operation and support teams and is used for R&D of microtechnologies.
LETI used processes developed in past silicon photonics project and standard process steps used in
microelectronics. These steps are offered in ePIXfab MPW with the following characteristics:
200mm SOI wafer with ranging Si thickness from 50 to 400nm on 2000nm BOX
Partial etching of Si for vertical fiber I/O and rib passives
Full etching of Si for ultra-compact passives
Amorphous silicon deposition at low temperature, doped or non doped polysilicon at high
temperature
Epitaxy of Si or Ge in full sheet or in cavity.
Oxide deposition
CMP
Implantation of Boron and Phosphorus with RTP annealing
Metal deposition and etching
These process steps allow most of the photonic devices ( passives, modulators, Ge photodetectors)
Process modules in development include:
Thin metallization for heaters
Si nanocristals (NL application)
Route for integration with electronics
Availability in ePIXfab is under discussion and depends on the user’s request.
LETI’s silicon photonics PDK includes:
mask design rules for multilevel design
mask design guidelines
Example cells
PhotonFAB D3.1 Roadmap
© IMEC, CEA-LETI 16
DRC settings for Cadence
Available standard masks for FC
Additional services offered by LETI:
Custom process development and small-volume manufacturing capability
The short term roadmap of technology introduction within ePIXfab is given in Annex 2
3.2.3 IME (http://www.ime.a-star.edu.sg)
The Institute of Microelectronics (IME) is a member of the Agency for Science, Technology and Research
(A*STAR) in Singapore. Established in 1991, the mission is to be a world class research institute in
advancing microelectronics technology. R&D at IME covers the semiconductor technology chain,
integrated circuit design, wafer fabrication process technology, packaging and assembly, and reliability
testing and analysis. In terms of personnel, IME employs around 250 staff, and also 150 students from
universities, polytechnics and junior colleges attached to the Institute every year.
IME's Silicon Photonics MPW Prototyping offers high-end fabrication at a cost affordable to research
groups and companies, for prototyping and small volume fabrication (<100 Wafers/Month run rate).
IME provides access to CMOS devices technology Platform (0.13 m and above) and Silicon-
Microphotonics technology platform.
The technology offer is:
200 mm Silicon-on-Insulator wafer: typically, 220nm top silicon, 2000nm buried oxide. 300 mm
wafer size available in 2012
248nm deep UV lithography with PSM Mask. 193nm (Available by mid of 2011).
IME's Silicon Photonics Platform is based on 248 nm deep UV lithography supporting a wide range of
submicron photonic devices and structures: passive structures from isolated strip waveguides to dense
photonic crystal structures, active structures through Ge and SiGe epitaxial growth, and high-quality SOI
as a substrate. The technologies are based on whatever developed through either 1-to-1 RD effort or
MPW service outcome.
3.2.3.1 MPW Service:
Shared Prototyping: Participation in the Shared Prototyping will be announced typically three
times per year. The users will share the cost of prototyping effort and have the option to use
either IME's or their own design which is within the technical specifications for each of the
announcements.
Customised Prototyping: This service is intended for user whose requirements are beyond the
timeline and technical specifications of a particular announcement.
PhotonFAB D3.1 Roadmap
© IMEC, CEA-LETI 17
The cost structure is somehow different from ePIXfab.
S/N Cost component Cost in Euros
1 Substrate (per wafer) 500 and above
2 Mask Area (per mm²) 40
3 Wafer Processing (per mm²) 80 and above
4 Administration 500
IME has Standardized Process Module and Integration as well as device library for both passives and
actives.
About 1 month is needed to compile requests from different requesters (for experienced users, based
on available design rules, discussions, GDS review and confirmation), assuming typical users size is 4-5
per call.
As for ePIXfab, the major concern for offering MPW access through MPW service is non-standardized
request on needed devices from various customers.
3.2.3.2 Other services
Packaging technologies
Application-specific photonic packaging is available, as well as RF opto-electronic component packaging
up to 10G.
CMOS IC (above 90nm) can be packaged in sample volumes
Design software:
The main types of design softwares (Electromagnetic simulation, Multiphysics, circuit simulation, layout,
schematic and verification) are available in the different IME labs.
Design services
ASIC and photonic IC design capabilities are available through different IME groups.
For IP blocks, a Basic Devices Library is available, and IME is also working with customers based on their
specific design (but compatible with IME’ process module and integration).
IME is working with major commercial foundries on process technology transfer. Co-design on
integration is possible if customers need special process support to implement device concept.
Training
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Training on technology , software and design are available on request.
3.3 Other potential providers
3.3.1 IHP
IHP (Frankfurt am Oder) is an R&D institute offering a range of specialty technologies, especially high-
speed SiGe BiCMOS. Part of IHP’s revenue is made on manufacturing.
Technology
IHP has a certified 200mm manufacturing line with 0.25um, 0.18um printing capability with 248nm DUV
lithography. Over the last years, and in the context of the FP7 Helios project, IHP developed a set of
processes for passive silicon photonics devices in 220nm thick SOI: relatively loss waveguides and fiber
couplers. IHP has the capability to develop front-end integration of such silicon photonics structures
with high-speed BiCMOS.
MPW, design, testing
IHP is currently offering MPW into its BiCMOS technologies through Europractice. IHP has extensive
expertise in the development and offering of design kits as well as in wafer and device test approaches
and implementation.
3.3.2 VTT (www.vtt.fi)
VTT offers its services on a commercial basis, but also carries out some scientific research on a non-
commercial basis. VTT as a whole is a not-for-profit organisation, but uses commercial pricing for fee-
based services. VTT's offering is open to both academic and industrial customers.
The current offer is R&D and commercial production in the Micronova clean room facility. The main
focus is on 150 mm silicon wafer processing for MEMS sensors, MEMS resonators, IC, nanoelectronics,
RF electronics, integrated passive devices, superconductors, imaging detectors, silicon photonics,
microfluidics, Fabry-Perot interferometers, heterogeneous integration etc.
In the medium term, MPW-type operation can be considered if enough users can be found (3 yrs).
Technical offering will shift towards 3D integration concepts (1-3 yrs). More processes should be
available for 200 mm wafers, depending on customer requests (3 yrs).
3.3.2.1 Process description
In the photonic domain, a standard fabrication processes for fabricating 2-10 µm thick SOI rib
waveguides and related waveguide components is available. Default process steps include
stepper/contact lithography, two Si etch steps, surface smoothing, cladding deposition, oxide etch
(cladding/BOX), and SiN AR coating of waveguide facets. Optional, but commonly used process steps are
metal deposition & patterning (Mo, Al, Au etc.), additional Si or oxide etch steps, thermo compression
bonding of optoelectronics on SOI.
PhotonFAB D3.1 Roadmap
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A variety of standard processes are available for other applications and devices: MEMS sensors, MEMS
resonators, IC, nanoelectronics, RF electronics, integrated passive devices, superconductors, imaging
detectors, microfluidics, Fabry-Perot interferometers, heterogeneous integration etc. The processing
capacity of the clean room is about 30 000 wafers/year.
More details about the process steps and the facilities can be found on
http://www.vtt.fi/research/technology/cleanroom_services.jsp and
http://www.vtt.fi/research/technology/micro_and_nanophotonics.jsp
As far as design rules are concerned, some design rules can be provided, but there is no single set of
design rules that would cover all available processes and devices. If a MPW concept would be
introduced for a certain set of processes and devices then a dedicated set of design rules can be
prepared. This could be easily done e.g. for the processing of 2-10 µm thick SOI rib waveguides, for the
hybrid integration of nanophotonic chips, optoelectronics etc. on those platforms, and for packaging the
resulting optoelectronic modules. In some other cases it can take significant effort to prepare the design
kit for MPW access
MPW access
The pricing structure can be adopted to support MPW processing. However, the number of users for a
given process must be sufficiently high to obtain cost benefits from the MPW concept.
In general, the processing is made on wafer-level. Basic research and prototyping is sometimes simpler
on chip-level, as is commonly done in academic fabs. However, the MPW concept could ease basic
research and prototyping also on wafer level. Micronova facility supports the entire micro-nano
innovation chain from basic research to small/medium scale manufacturing. The processes available in
Micronova include not only mature processes, but also experimental processes that are continuosly
developed and created. Similarly, the devices fabricated in Micronova range from emerging
technologies and novel devices to commercial products. The envisioned MPW service could also range
from mature processes and devices to highly experimental ones.
Some public funding could be needed to initiate the MPW service and to enable especially the first SMEs
and academic groups to use the service. VTT is currently cooperating with MPW services such as
Europractice and CMP
Manufacturing capability
Based on the product prototypes developed with the wafer level processes in Micronova one can
immediately start small volume manufacturing. The shift from single wafer processing to batch
processing is trivial as many processing tools readily offer cassette to cassette operation.
Shifting from small to medium/large volume manufacturing is also possible in Micronova. Depending on
the volume it might be necessary to upgrade certain process tools for higher throughput, but this is no
PhotonFAB D3.1 Roadmap
© IMEC, CEA-LETI 20
limitation. The maximum processing capacity of the Micronova clean room facility depends on the
processed devices, but it should be at least 30 000 wafers/year.
3.3.2.2 Other services
Design software:
The most popular types of design softwares (RF & Optics simulation, Multiphysics, analog and digital
circuit simulation, layout of photonic integrated circuits, schematic and verification) are available.
Design services
Complicated photonic integrated circuits can be designed with in-house design software that supports
hierarchical and fully parameterised design, numerical layout optimisation, arbitrary shapes and GDSII
export. A large library of existing elements is available. Electronic IC (analog, digital, mixed-mode) such
as DA and AD converters, neural networks, clocking circuits and sensor readout electronics can be
designed .
VTT is already working with external fabs like AMS, ST, UMC and TSMC.
Training
Even if training is not VTT's primary service offering, training on technology, software and design are
available on request.
3.3.3 Austriamicrosystems (www.austriamicrosystems.com)
3.3.3.1 Process
Austriamicrosystems is running a CMOS based manufacturing, SMIF fab. Different processes are now
available: 0.35µm CMOS, HV-CMOS, SiGe & EEPROM.
MPW service is established since several years and is offered as standard foundry access service with
e.g. 16 shuttle starting dates for 0.35µm technologies in 2010. Austriamicrosystems is currently
cooperating with the following MPW services: CMP-TIMA (Grenoble, FR), Fraunhofer IIS (Erlangen, GER),
MOSIS (Marina Del Ray, CA, USA). The MPW submission date is 1 week prior AMS MPW start date
The manufacturing capabilities are adapted either to prototyping through MPW service (see
http://asic.austriamicrosystems.com/cot/mpw/MPW_Shuttle_Pricelist_2010.pdf), small volumes (6
engineering wafers) or larger volumes (25 wafer batch MOQ)
The indicative price of MPW is 810 € per mm² in 0.35µm CMOS
The PDK is made available through the High Performance Interface Tool Kit (HIT-Kit) consisting of
software programs and libraries which contain full frontend (symbol, schematic, simulation model) and
backend (placement outlines, full layout) information for the development of digital, analog and mixed
signal circuits in a Cadence Design Systems, Mentor Graphics or Synopsys CAE design environment.
Pricing is available on http://asic.austriamicrosystems.com/hitkit/hk400/index.html
PhotonFAB D3.1 Roadmap
© IMEC, CEA-LETI 21
3.3.3.2 Other services
Packaging technologies
IC packaging: Almost any common used plastic & ceramic packages possible: CABGA, epTQFP, epTSSOP,
LQFP, MQUAD, MSOP, P2_QFP, PDIP, PLCC, PQFP, QFN, SOIC, SSOP ,TQFP, TSSOP, CCC, CDI, CLCC, CPGA,
CQFP_5, CSOIC. Only ceramic assembly in house, plastic assembly established via external co-operations
No photonic packaging available
Design software:
Multiphysics design is available with COMSOL. Other design tools (circuit simulation, layout and
schematic of devices, core cells, IO cells, rule checks) are included in the HIT Kit.
Design services
ASIC design capabilities No design services at foundry interface, 3rd party design services with
external partners (design house), ASIC design service with product business units
IP block design capabilities Only for ASIC customers
Specific IP blocks available http://www.austriamicrosystems.com/eng/Products/Full-Service-
Foundry/Foundry-IPs/IP-Block-List
Training
Software HIT-Kit trainings offered to customers:
http://asic.austriamicrosystems.com/hitkit/training.html
Design Technology specific trainings on demand
3 days training held at austriamicrosystems, but can on request held on-site at customer
3.3.4 STMicroelectronics
STMicroelectronics has been working on silicon photonics in the frame of several EU funded projects
such as PICMOS and WADIMOS. STMicroelectronics is already giving access to advanced CMOS and
BiCMOS technology nodes through MPW services such as CMP (http://cmp.imag.fr/). Even if silicon
photonics processes are not available yet at ST, this technology is considered as attractive for the future.
Thus, ST is willing to contribute to the next version of the access roadmap.
3.4 Chip-scale services
E-beam lithography may be used for patterning high-resolution structures with a rapid turn-around for
R&D. E-beam works with small fields on individual samples. This may complements the wafer-scale,
large-field, slower turn-around technologies offered by ePIXfab and may be organized as a post-
processing service.
PhotonFAB D3.1 Roadmap
© IMEC, CEA-LETI 22
3.4.1 Nanostructuring platform
http://www.nanophotonics.eu
E-beam lithography may be used for patterning high-resolution structures with a rapid turn-around for
R&D. E-beam works with small fields on individual samples. This may complements the wafer-scale,
large-field, slower turn-around technologies offered by ePIXfab and may be organized as a post-
processing service. See the nanostructuring platform : http://www.nanophotonics.eu
3.4.2 AMO
http://www.amo.de
AMO fabricates active and passive silicon photonic devices with e-beam lithography technology.
AMO is running a CMOS-compatible Silicon processing line in a class 10 to class 1000 cleanroom. High-
end fabrication equipment for semiconductor technology is operated in a flexible way to enable quick
process changes and unconventional solutions.
AMO is using processes developed in past silicon photonics projects. These steps are offered in ePIXfab
with the following characteristics:
SOI wafer or single chip processing ranging from 20x20 mm² up to full 6”. (Standard processes
for 200 nm up to 340 nm SOI thickness available)
High-Resolution Electron Beam Lithography with proximity correction for excellent CD control
and accuracy (positive and negative tone resist processing available).
Strip- and Rip waveguide technology and highly accurate Photonic Crystal patterning processes
available.
Experience in the fabrication of passive nanophotonic devices.
Grating Couplers and Mode Size Converters available
Implantation of Boron and Arsenic with RTP annealing for active devices available (already
demonstrated for modulator devices)
AMO currently offers a foundry service for passive devices. Typical volume ranges from 1 up to 5 chips
per order. AMO currently intensifies it´s effort in the field of silicon nanophotonics in a number of
research projects. Additional advanced process modules are expected to be available by the end of
2010. AMO provides access to these technology solutions and currently sets up design rules that will be
available soon.
3.4.3 VTT
Sample-scale technologies concern post process and packaging. The capacity ranges from hundreds to
tens of thousands of samples per batch, depending on sample and process type. Sample or chip scale
processes are mainly used to complement wafer scale processing. Examples are hybrid integration (flip-
PhotonFAB D3.1 Roadmap
© IMEC, CEA-LETI 23
chip), wire bonding and packaging (see below). Some of these processes are used commercially, while
others can be very experimental.
Wafers processed either in Micronova or elsewhere can be diced into chips and post-processed or
packaged in Micronova. Chips can be bonded either on chips or on wafers. Both chip and wafer scale
packaging concepts are available (hermetic sealing, TSVs etc.). Collaboration with external fabs can be
used to access wafer-scale processes for fabricating e.g. nanophotonics or advanced ICs. These can be
integrated with the devices processed in Micronova either on wafer scale or on chip scale. However,
transferring wafers between fabs can be limited by the different wafer sizes.
3.4.4 NTT
http://www.keytech.ntt-at.co.jp/nano/index_e.html
NTT Advanced Technology (NTT-AT) Nanofabrication corporation offers an e-beam silicon waveguide
fabrication service since 2007.
The technology offered is:
silicon wire waveguides with 400nmx220nm core size
5mmx5mm writing area
spot-size convertors to couple to fiber with low losses
Customers sign a NDA, design the circuits, and specify metrology. Fabrication is done by NTT-ATN,
optical functions or performance is not guaranteed. Access was open to Japanese domestic customers
only, but after communication with NTT ePIXfab customers can now also gain access.
3.4.5 US National Nanotechnology Infrastructure Network (NNIN)
http://www.nnin.org/
The NNIN coordinates a set of nanofabrication sites that offer world-class facilities, including e-beam
writing, at Cornell (CNF), Stanford (SNF), Georgia Tech (NRC) and other sites. These centers offer hands-
on access for external and internal researchers to use the tools at the center to do nanofabrication
work, with support of highly skilled staff.
These centers operate not in service mode for external fabless customers. However, for instance in the
Cornell Nanoscale Facility there are a number of independent fabrication consultants, highly skilled on
the tools, that can perform service activities on CNF tools for customers. For US and world-wide
researchers, these facilities may be an option complementary to wafer scale fabrication of larger and
more complex ICs.
3.5 MPW service centers
3.5.1 Europractice
PhotonFAB D3.1 Roadmap
© IMEC, CEA-LETI 24
Europractice offers electronic ASIC prototyping and small volumes to academic and industrial
customers:
Wide portfolio incl. digital, analog, mixed-signal and power technologies from IHP,
Austriamicrosystems, On SEMI, TSMC and UMC.
Since 2007, it has expanded its offer to MEMS (MEMSCap, Tronics).
Europractice software offers EDA software distributions and design kits
Since 2007-2008, photonics specific software packages were added to the Europractice Software set,
from PhoeniX and from Design Workshop. This allows academic silicon photonics designers to get low-
cost licenses.
Europractice is currently extending its offer to other technologies, e.g. MEMS, and to emerging
technologies. Offering IMEC silicon photonics MPW by Europractice to European academic researchers
is under investigation.
3.5.2 CMP (Multi Project Circuits)
CMP is a broker in ICs and MEMS for prototyping and low volume production. Circuits are fabricated for
universities, research laboratories and industrial companies.
Advanced industrial technologies are available in CMOS, BiCMOS, SiGe BiCMOS, P-HEMT E/D GaAs, etc..
CMP distributes and supports several CAD software tools for both industrial companies and universities.
3.5.3 CMC
CMC delivers the following ePIXfab-related products and services, primarily to Canadian academic
customers:
access to ePIXfab MPW runs
a silicon nanophotonics graduate course that includes prototyping of student designs through
ePIXfab
design kit and software (dw-2000)
engineering support
CMC facilitates research access to design environments, fabrication services and test equipment,
enabling researchers to design, realize and verify their photonics concepts. For researchers, the
opportunity to fabricate a design validates theories, guides further work and raises the credibility of the
research in publications. Proof-of-concept prototypes help move research toward a product stage, and
are increasingly pre-requisites to attract investment in new technologies.
As such, CMC acts as a broker for ePIXfab to Canadian academic customers today.
3.5.4 MOSIS
PhotonFAB D3.1 Roadmap
© IMEC, CEA-LETI 25
MOSIS is the first of all MPW services and has practically enabled the foundry model. It is running as a
not-for-profit entity within the University of Southern California. MOSIS is running entirely on revenue
from companies needing prototyping and low volume manufacturing. This makes low-cost access for
academic users possible, in a number of cases even at zero cost for educational programs and non-
funded faculty. The commercial users MOSIS serves need volumes smaller than the minimum volumes
the foundries will take.
MOSIS is building collaborations with other MPW centers and world-wide initiatives to offer new and
emerging technologies. In this way a world-wide customer base can be served for such limited use
technologies. MOSIS is also actively looking into photonics and silicon photonics.
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3.6 Manufacturing
3.6.1 Current state
Low volume manufacturing for industrial customers is currently offered by a few actors only:
IMEC, CEA-LETI, and AMO (chip-scale manufacturing).
A number of industrial foundries do have technologies available in which certain types of silicon
photonic ICs can be designed, but which are not (readily) accessible for MPW or small
customers: Freescale, Chartered. Dedicated photonic technologies do not exist yet in industrial
foundries.
The major research centers are ideally placed to guide customers from low volume
manufacturing at the research centers to volume manufacturing in a larger foundry.
o TSMC and IMEC have set up an Innovation Incubation Alliance, in which IMEC serves
small customers and emerging technologies, and volume customers can be moved more
smoothly to TSMC.
o This is only for large volumes (millions of devices/yr)
3.6.2 User needs
Currently, only a few direct requests for manufacturing capability have been identified/received. The
volumes corresponding to this are not yet of interest to commercial foundries and can be handled by
research centers.
However, any contact with potential industrial end users of silicon photonics indicated that supply chain
availability, including manufacturing capability is of prime importance.
Three types of future manufacturing needs can be identified based on the volume:
A number of industrial applications will always run on very low volumes (a few wafer batches
per year) that can only be served by volume aggregators offering MPW and LVM, e.g. space
applications, high energy physics, specialty ASICs, …
A wide class of applications will have sufficient volume to run through LVM aggregators and
cannot live with MPW only, but will not reach the volume requirements of 1000s of wafers
requirements of foundries.
A smaller number of applications, e.g. in health care, will have sufficient volume to be served by
foundries directly.
First fabless applications are entering the market or are in an R&D stage currently (2009-2010). In order
to serve the wide range of applications without sufficient volume projections to be served by foundries
directly, it seems important that during 2010-2012 LVM capability is deployed through aggregators (for
PhotonFAB D3.1 Roadmap
© IMEC, CEA-LETI 27
very small volumes) or through research institutes (imec, LETI) for somewhat larger volumes or
dedicated processes.
PhotonFAB D3.1 Roadmap
© IMEC, CEA-LETI 28
4 Packaging and test
4.1 Dicing, resizing
Many providers exist which have been working for a long time with wafer foundries.
Dicing without creating optical facets is a standard technology and is usually done by the fab or
subcontracted to a specialized company (e.g. HCM, …).
For silicon PICs, scribing of optical facets, either during the dicing process or afterwards, would be
beneficial, relieving the PIC user from this difficult and time-consuming job.
One can mention for example:
Gamberini located near Grenoble, specialized in dicing (www.microelectronics-sc.com) :
o Dicing wafer from 300mm
o Dicing wafer into chips
o Thinning chips down to mini 150µm
o Dicing glass, SiC, quartz
o Mounting and connecting chips with ball or wedge bonding
Laser Rhône Alpes, located near Grenoble, specialized in laser cutting (http://www.laser-rhone-
alpes.com/en.php)
o resizing wafer from 300mm to smaller flexible shapes (round, hexagons, etc…)
o Polishing of the edges and formation of notch or flat
o Thinning chips down to mini 150µm
4.2 Packaging availability and needs
Since silicon photonics manufacturing at industrial level is still in its infancy, there is no existing
packaging provider offering standard packaging solutions for such chips.
4.2.1 Generic versus customized packaging
A number of companies are identified that have the capability to develop and offer fiber array pigtailing
technology and services for si PICs. In addition, a sufficiently wide range of fiber array mount products is
available from various vendors.
Photonic packaging is currently mostly application and customer specific. For low-volume prototyping of
silicon photonic ICs with multiple fiber pinout, this is difficult to sustain. However, systems R&D needs
packaged components even in very low volume. A generic packaging approach that can support
prototyping for a wider range of applications and customers can be a solution.
The packaging services may therefore evolve along the following lines:
PhotonFAB D3.1 Roadmap
© IMEC, CEA-LETI 29
Develop and offer a small set of generic packaging technologies for prototyping silicon PICs
within a certain pinout range. This allows the NRE costs to be shared over many users and
devices. Uniform design rules with respect to packaging can be distributed to the IC designers
and pricing schemes can be set up.
Continue to optimize or custom develop packaging technologies for volume manufacturing of
devices or for prototyping devices with pinouts that cannot be (economically) handled with a
generic package technology.
4.2.2 Packaging providers
Several packaging providers (industrial providers of optoelectronic packaging of institutes developing
packaging solutions) have been identified
4.2.2.1 ePIXpack
The consortium ePIXpack is a provider of advanced packaging technologies, serving clients with small
scale packaging and assembly needs. ePIXpack offers packaging services for Si PICs. Two kinds of service
are available. There are bespoke packages precisely tailored to the client’s PIC. Bespoke packages and
pigtailing solutions offer high performance and quality of qualified standards, but are costly (costs can
easily exceed the price of the component by an order of magnitude). On the other hand, ePIXpack offers
more generic and cost effective packaging approaches, in particular for Si PICs. Such solutions have been
developed in close cooperation with ePIXfab. The generic packages are based on v-groove fiber array
pigtailing solutions that realize multiple optical i/o via grating couplers. Generic solutions are particularly
useful for testbed implementations. There is a continuous joint effort of ePIXfab and ePIXpack to
improve and extend the existing generic Si PIC packaging solutions.
4.2.2.2 VTT (www.vtt.fi)
The current packaging offer concerns flip-chip integration by using either solder bumps or Au-Au thermo
compression bonding, wafer bonding and fiber pigtailing for prototypes by attaching separate V-groove
arrays into optical chips with sub-µm alignment accuracy.
Fiber pigtailing:
Optical coupling from (to) the 2–10 µm thick SOI rib waveguides to (from) optoelectronics and
nanophotonic chips, such as the chips offered by ePIXfab, can be readily implemented by hybrid
integrating the other chips on SOI with sub-µm alignment accuracy. Au-Au thermo compression bonding
is a standard process that only requires Au contact pads on the chips that are bonded on SOI. The
thermal contact to the SOI substrate is so good that also high-power optoelectronics can be integrated
on SOI. The main focus is on optical coupling solutions that support an ultra-wide bandwidth (e.g. from
1.3 to 1.6 µm wavelength)
In the medium term, the plan is to develop a generic fiber pigtailing concept that enables low-loss fiber
pigtailing of SOI waveguide chips in larger volumes and with low cost. This concept could be applied also
to optoelectronics and nanophotonic chips, such as the chips offered by ePIXfab, by first hybrid
PhotonFAB D3.1 Roadmap
© IMEC, CEA-LETI 30
integrating those chips on VTT's SOI platform and by then applying the generic fiber pigtailing concept.
Additional developments concern hybrid integration options that solve the optical coupling to very small
optical modes, surface-active devices (PDs, VCSELs), devices that don't have Au contact pads, devices
that require very fast control electronics (>>10 Gb/s).
The technological offer will also evolve towards flip-chip integration with low-T solders and higher
throughput (1-3 yrs), bonding of various different wafers (1-3 yrs), wafer-level packaging and chip-on-
wafer encapsulation (1-3 yrs) and fiber pigtailing for volume production (1-3 yrs)
Specific fiber pigtailing and hybrid integration concepts can be developed based on the specific needs of
a customer, or for a group of MPW service users.
Component packaging
RF lines integrated on SOI presently support at least 10 Gb/s data, but even faster RF lines will be
developed. Through-silicon vias (TSVs) supporting RF operation up to 100 GHz are being developed. VTT
is developing silicon-based packaging concepts for optoelectronic RF modules. These aim to offer wafer-
level and chip-on-wafer packaging options with TSVs, fiber pigtails, hermetic sealing, fully-automated
assembly and very low packaging costs.
VTT offers mature LTCC-based packaging concepts for optoelectronics that are particularly well suited
for multi mode optics.
IC packaging with (or without) SOI platform is also available: IC chips can be hybrid integrated on the 2–
10 µm SOI waveguide platform where they can be used to control optoelectronics that is integrated on
the same platform.
Sample volumes from hundreds to tens of thousands of samples per batch can be handled, depending
on sample and packaging type:
The LTCC-based packaging of optoelectronics is very mature, but mainly used for multi mode
optics.
Some RF line, TSV technologies and fiber pigtailing are readily available, but these are being
developed further.
Silicon-based packaging concepts are being developed for optoelectronic RF modules.
Major concerns related to MPW service
Au-Au thermo compression bonding requires Au contact pads on the chips that are hybrid integrated on
VTT's SOI platform. The bonded chips should also have AR coating to prevent reflections from the
waveguide end facets.
PhotonFAB D3.1 Roadmap
© IMEC, CEA-LETI 31
Introducing a MPW service or a similar multi-user packaging service at VTT requires a sufficient number
of users. Some public funding could be needed to initiate the service and to enable especially the first
SMEs and academic groups to use the service.
Cost sharing is only possible if multiple users are interested in the same process. This could happen quite
naturally if VTT would offer packaging or hybrid integration service for the users of the ePIXfab.
4.2.2.3 Linkra – Teleoptix (www.teleoptix.com)
Linkra - Teleoptix does not have fab technologies capabilities and does not plan to offer/endeavour in
this kind of aspect.
Linkra – Teleoptix is specialized in fiber pigtailing/connection for RF opto-electronic components. Several
packaging technologies are currently available as application-specific approach (“gold box approach”). In
the next years (2-3 years from now) the company plans to move toward a generic packaging approach
for a wide variety of packaging type.
RF optoelectronic packaging is available for O/E components up to 40Gbit/s as well as for IC packaging
either at DC and up to 40 Gbit/s (i.e. TIAs up to 40Gbit/s). ICs can be handled at chip/die level. Following
stage of die attach and optical fiber alignment are performed using state-of-the art tools and machines.
Technology is currently mature, at production level. Several (hundreds) pcs per month can be handled
for internal manufacturing.
Concerns when collaborating with external entities for R&D activities regard the time-allocation of tools
and machines in production line. Cost sharing of innovative R&D projects/packaging activities can be
envisioned upon a clear view of potential opportunity and market for the specific case (i.e., component,
subsystems, etc…)
4.2.2.4 Acreo (www.acreo.se)
Acreo is a contract R&D company in the field of electronics, optics and communication technology.
Optoelectronics packaging technologies have been developed for two main application fields: image
sensors and telecommunications.
Packaging solutions include RF design, silicon microbench fabrication (eg. V-grooves, alignment features,
…) as well as hybrid integration processes of optoelectronic chips (Indium and Gold-Tin flip-chip
bonding). Fiber pigtailing equipment for MMF and SMF are available.
Small volumes up to several hundreds of pieces/month can be handled.
Additional packaging technologies such as hermetic packaging, vacuum packaging, anisotropic
conductive films are also available as well as specific processes for bio applications (eg. functionalization,
PDMS-based microfluidics).
Cost sharing can be considered if enough users can share standardized packaging processes (which is
not the case for the time being, because packaging is often specific to each application.
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4.2.3 Spot size convertors/interposers
Spot size convertors chips (interposers) are chips made in a refractive index contrast in between that of
fiber and Silicon PICs. The interposer can connect well with a suitably designed Si waveguide spot at one
end and a fiber at the other end. Potentially, the total insertion loss can be lower than with a direct
fiber-silicon IC connection.
When designed as a submount IC, the interposer may also carry other devices, such as electrodes or
controller ICs.
Three technologies can be identified that could serve this:
Silica-on-silicon, potentially available e.g. from NTT.
TriPLeX, available from LioniX.
Hydex, potentially available from Infinera.
4.2.3.1 TriPLeX/LioniX
LioniX offers a foundry service on the TriPLeX material, a medium to high index contrast material
system. TriPLeX allows for IR and VIS applications, and coupling to fiber is easier than for Si PICs. In
addition, TriPLeX waveguides can be designed so that they can be matched with well-designed SOI I/O
waveguide spots. Therefore, the material may be very relevant to silicon for making spot size
convertors or interposers. Technical viability of this is not yet confirmed.
4.2.3.2 Hydex/Infinera
Hydex is a proprietary material of Infinera (acquired Little Optics) and is used for their in-house needs as
a systems company. Infinera does not currently offer a foundry or ASIC supplier service on this material.
PhotonFAB D3.1 Roadmap
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4.3 Testing
4.3.1 Current status
Two areas are discriminated:
o wafer test by fabs to monitor and ensure process quality
o wafer or sample test by users
Availability of wafer test for fabs can be summarized as:
o no standards are available
o no wafer test services are available
o wafer test concepts are available, a lot of work has been done on fiber I/O from and to the chip
by various actors (UGent/imec, CEA-LETI, NTT, IBM, Cornell,…)
o a number of actors have developed or are developing test tools and procedures in-house:
Luxtera, CEA-LETI, imec, University of Washington
o test devices are included on designs submitted to imec MPW, but not monitored by the fab yet.
For wafer or sample test by users:
o Wafer test tools would be handy for optimization and parameter scanning purposes. A number
of approaches are in development (see fabs)
o University labs usually have all the experience and tools necessary for sample tests, as this is
very specific
o A number of approaches are in development to enable system level experiments with packaged
components, e.g. gPack packaging by ePIXfab-ePIXpack.
4.3.2 Identified needs
There is a great need for predefined component libraries (see design) and some level of specification on
processes also in MPW. Process monitoring is a prerequisite to develop this. Therefore, a number of
actions should be taken as soon as possible (2010-2012):
o development of standardized photonic test structures and reference data
o wafer scale photonic metrology tools and procedures
New users entering the field need support on building measurement setups. ePIXfab partially supports
this.
5 Roadmap
PhotonFAB D3.1 Roadmap
© IMEC, CEA-LETI 34
Given the feedback received from providers and users, it is for the time being difficult to build a
roadmap beyond 2-3 years. This mid to long term evolution will be addressed in future versions of the
roadmap.
5.1 Technologies available for fabless prototyping
Current technologies with MPW access for a fabless public include modules for passive devices, active
devices based on implants and Ge epitaxy and metallization; all in thin (100-400nm) SOI. Active device
processes are currently offered only in a flexible mode in which the designer has freedom to choose
process parameters. Standardization of this access is currently (2010) difficult. The providers are ePIXfab
(IMEC, LETI) and IME (Table 5).
Provider Technology Type of access Future
extensions
ePIXfab-IMEC - Thin SOI 220nm, 200mm
- Passive device processes, standardized
- Litho: 193nm DUV
MPW. LVM High-efficiency
I/O (2011)
Active devices,
3D integration
with electronic
IC (type of
access
undecided)
ePIXfab-LETI - Thin SOI 100-400nm, 200mm
- Standardized: Passive device in 220nm SOI
- Flexible: SOI 100-400nm
passive
active implant & metal
Ge epitaxy
- Litho: 193nm and 248nm DUV
MPW, LVM Heaters (2010)
3D integration
with electronic
IC (type of
access
undecided)
IME - Thin SOI, typ. 220nm
- Passive , active implant & metal, Ge epitaxy.
- Litho: 248nm DUV
MPW, LVM 193nm DUV
and 300mm
(2011)
Table 5: technologies available in MPW
A number of technologies exist with currently no MPW access but which may be of interest for
prototyping access to a wider public (Table 6).
A number of sample scale technologies exist with at least prototyping access (Table 7). These
technologies can be complementary to wafer scale technologies for rapid device prototyping and design
kit development.
PhotonFAB D3.1 Roadmap
© IMEC, CEA-LETI 35
Provider Technology Type of access Evolution
IHP Thin SOI 220nm 200mm, passive device processes with
potential for front-end integration with high-speed SiGe
BiCMOS
N/A Collaboration
with epixFAB
to be
investigated
VTT, NRC Thick SOI 150mm R&D,
manufacturing
Collaboration
with epixFAB
to be
investigated
Freescale, BAE Si photonics front-end integrated with 0.13um CMOS,
200mm
Manufacturing Collaboration
with epixFAB
to be
investigated
Table 6: technologies without MPW access
Provider Technology Type of access Evolution
Nanostructuring
Platform
Thin SOI 220nm samples, e-beam lithography
Passive devices, metallization, underetch
R&D,
Prototyping
Collaboration
with epixFAB
ongoing
AMO Thin SOI 220nm samples, e-beam and nano-imprint
lithography
Passive devices
Prototyping,
LVM
Collaboration
with epixFAB
to be
investigated
NTT-AT Thin SOI 220nm samples, e-beam lithography
Passive devices, fiber I/O
Prototyping Collaboration
with epixFAB
to be
investigated
Table 7: sample scale technologies with at least prototyping access
Evolution 2010-2012
Based on the current situation described, PhotonFAB will investigate in the future, the potential,
desirability and viability of:
access to IHP technology
collaboration with AMO, Nanostructuring platform and NTT.
standardization of access to current active device technologies and co-existence of flexible
access
collaboration between ePIXfab and IME
PhotonFAB D3.1 Roadmap
© IMEC, CEA-LETI 36
access to future IMEC active device technologies.
access to 3D integration technologies
the need for MPW/prototyping access to thick SOI technologies
Those strategic collaborations or evolutions will be commonly decided with the Steering Committee and
the Advisory Board. Technologies with a positive outcome of this evaluation will be considered in the
business plan of ePIXfab at the earliest mid 2011. Actual offering will depend on finding adequate
funding or generated revenue.
5.2 Design
The current design flow for silicon photonic IC’s is made by and for photonics and physics engineers and
scientists and is extended by PhotonFAB and other actors to support wafer scale prototyping (Figure 1).
Software and training is available from the vendors directly. For academic users, Europractice
Software offers a comprehensive set of photonic design packages already.
An early design kit is available for the ePIXfab and IME MPW services.
The major barriers for design of silicon photonics ICs today are:
lack of basic cell (building block) libraries
no integration with EDA tools for electronic IC designers
immature and incomplete circuit simulation and schematic capabilities
little circuit-level verification capabilities
Evolution 2010-2012
Design by circuit and systems engineers in collaboration with application engineers should be
enabled, for which the ground work needs to be laid 2010-2012
the design flow must be completed (Figure 2, Table 2), in particular with circuit level design,
simulation and verification
interoperability between the tools in the design flow and between tools of different vendrs
must be improved by development of a common standard supported by a broad industry
platform.
The foundries should develop advanced process design kits supporting the implementation
of schematics, layout, simulation and verification for the available foundry technologies.
This can of course only be done for fixed and standardized technologies.
PhotonFAB D3.1 Roadmap
© IMEC, CEA-LETI 37
interoperability with EDA tools is necessary to enable use of photonic modules by
engineers trained on electronic design
The FP7 EuroPIC and Helios R&D projects are working on the above described topics, first results
can be expected end 2010 and coming available as soon as 2011.
Collaboration between ePIXfab and Europractice Software on software and design kit
distribution for academic customers will be intensified in 2010-2011.
No commercial design services for silicon photonics are available today. The developments
described above should enable the start-up of such services starting 2011-2012.
5.3 Handling of small scale users
Academic R&D
World-wide academic users are currently served by ePIXfab and IME. Canadian academic users are
served by CMC in collaboration with ePIXfab. Design assistance is offered by IMEC, LETI and IME in an
R&D context.
Intensified collaboration between ePIXfab and other IC service providers, in particular Europractice, for
serving academic R&D needs may be beneficial. PhotonFAB will explore this starting mid-2010.
Fabless SMEs
Emerging technology exploration and very small volume prototyping by SMEs is supported by ePIXfab on
a at reasonable business effort basis. Any access for fabless SMEs beyond this (low volume
manufacturing, process development and optimization, design services) is handled by IMEC or LETI
directly.
Larger companies
Technology exploration and prototyping by larger companies is handled by IMEC or LETI directly.
Future handling of low volume users
PhotonFAB will investigate how these fabless SMEs as well as larger companies with small volume use
can be handled better in the future, especially for those volumes that even IMEC or LETI will not
consider to serve on a bilateral basis.
Evolution 2010-2012
1. The MPW centers need to move towards
finding a balance between offering a standardized generic process and flexibility for R&D.
offering advanced PDKs
PhotonFAB D3.1 Roadmap
© IMEC, CEA-LETI 38
being better integrated with the rest of the food chain.
2. Training efforts need to be continued and intensified, to reduce the total cost of design and to
increase technology uptake by students and researchers in their later jobs
3. For academic R&D, an improved integration between MPW centers and e-beam device
prototyping centers is beneficial, offering two advantages for patterning on samples predefined
through MPW:
rapid turn-around time for prototyping and testing individual devices
higher resolution patterning of small areas on fabricated
5.4 Manufacturing
Low volume manufacturing of silicon photonics is available from IMEC, LETI and IME. These research
institutes have agreements and contacts with commercial fabs and foundries to transfer customers and
technologies for volumes or projected volumes above certain limits.
Currently, there are no commercial fabs with silicon photonics technologies that offer both volume
manufacturing access and MPW. The few technologies available in volume (Freescale, Chartered) are
not available in MPW. No other fabs have no silicon photonics processes
Industrial photonic IC technologies can develop as the application demonstrators mature and a few
high-volume applications are identified. There is a large mismatch between ‘high-volume’ in the
electronics semiconductor industry and the typical volume of current photonics applications however.
Evolution 2010-2012
Based on the available data and above considerations, one can expect that:
A few volume foundries will serve dedicated customers in dedicated or CMOS technologies
(Luxtera, Lightwire, SiFotonics)
Major research centers with small series production capability (~10k-1M components/year)
will step in on the shorter term to serve smaller fabless users on platform processes as well
as larger companies with technologies built to specification.
5.5 Test Lab-scale test procedures and facilities on bare chips are well developed for academic R&D. For fabs and
foundries however, there are currently no established tools, methodologies and standards to test and
monitor silicon photonic device wafers. In order to support circuit-level R&D, enhanced low volume
manufacturing and transfer to volume fabs, further R&D on this is needed:
PhotonFAB D3.1 Roadmap
© IMEC, CEA-LETI 39
- development of standards/agreements of metrology of test structures that can serve as
process characterization and monitoring reference data. Both the methodology as well as
the actual structures should be investigated)
- development of wafer probe tools for silicon photonic wafers. A number of proprietary tools
for private use have been built by a number of actors.
PhotonFAB will help convince the actors in this to further invest in test infrastructure and standards.
First methodological application of wafer tests for silicon photonics by fabs can be expected in 2011.
5.6 Wafer handling and packaging
Many companies are offering packaging technology and services, but no established technology for
silicon photonics is available today. For R&D and prototyping purposes, a number of approaches are
available from R&D actors.
As packaging photonic devices for real products is very application-specific, it is impossible to drive
developments from a central actor as ePIXfab. However, ePIXfab is collaborating with ePIXpack to define
generic packaging technologies that can be used as a testbed for demonstration purposes of silicon
photonic ICs in system R&D. During 2010, design rules will be defined for the approach ‘gPack’ that has
been developed in 2007-2008. For easier adapting between fibers and silicon photonic circuits,
subassembly benches or interposers in a different material/technology may be used. A number of
technologies may be suitable for such an interposer/subassembly bench, in particular those with a
variable refractive index contrast, in particular the dielectric platforms TriPLeX (foundry service available
from LioniX) and Hydex (Infinera, no foundry service available). No such devices for silicon photonics
have been demonstrated yet.
For wafer sawing and other wafer handling, multiple companies are available that offer dicing and laser
cutting services. IMEC and LETI outsource these activities as deemed necessary to manage their supply
chain in a good way.
Evolution 2010-2012
A number of early solutions are available today for R&D purposes and use of them can start
from 2010
The packaging companies and research institutes should be brought together to think about
strategies and standardization.
5.7 Training
Basic training for silicon photonics is available, with training on technology and fabless access set up by
PhotonFAB during 2008-2010 (Table 8). Hands-on design training has been identified as a major need
and is being setup by PhotonFAB during 2010. Such training has already been setup by CMC for
Canadian universities in 2008-2009. The FP7 Helios project is also setting up training on silicon photonics
in general.
PhotonFAB D3.1 Roadmap
© IMEC, CEA-LETI 40
Subject Availability
Photonics basics From university programs worldwide
Silicon photonics tutorials ePIXfab
Design software training From the design software vendors
Silicon photonics technologies ePIXfab
MPW access and supply chain ePIXfab
Design flow and rules ePIXfab
Design training (hands-on) - ePIXfab starting fall 2010
- CMC (Canadian universities)
Table 8: availability of training
Evolution 2010-2012
Training is fractionally in place and new parts are in development.
As a number of actors are offering or developing parts of the training chain, cooperation
between the actors is necessary to rationalize the training offer and implement a full chain.
A first full training chain (by obtaining training from multiple sources) can be in place by mid
2011.
To keep this up to date and extend towards advanced design training, funding must be found
towards 2011-2012.
© IMEC, CEA-LETI 41
41 PhotonFAB - Deliverable 3.1
ANNEX 1: Roadmap of technology introduction within ePIXfab Call Sept
2008
IMEC03
January
2009
LETI03
June
2009
IMEC04
Nov
2009
IMEC05
Jan
2010
LETI04
May
2010
IMEC06
June
2010
LETI05
Nov
2010
IMEC07
January
2010
LETI06
May
2011
IMEC08
June
2011
LETI07
SOI 220nm/2µ
m BOX
Var Si
/2µm BOX
220nm/2µ
m BOX
Var Si
/2µm BOX
220nm/2µ
m BOX
Var Si
/2µm BOX
Fiber coupler
waveguide
aSi or polySi
Si or Ge epitaxy
B or P implantation
with anneal
CMP
Silicide
Heater
Metallization
Cladding SiO2
New processes No Yes No No No No Yes Yes users Yes SiOx??
© IMEC, CEA-LETI 42
42 PhotonFAB - Deliverable 3.1
Dicing
Design rules Improved
PDK,
standardiz
ation
Improved
PDK,
standardiz
ation
Improved
design
rules, mask
fab, DRC,
cost
calculation
Improvem
ent upon
user’s
recommen
dations
Improvem
ent upon
user’s
recommen
dations
Improvem
ent upon
user’s
recomman
dations
