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Puebla, December 2004
ICTP Microprocessor LaboratorySecond Central American Regional Course on Advanced VLSI Design Techniques
Benemérita Universidad Autónoma de Puebla, Puebla, Mexico29 November – 17 December 2004
Introduction to Analog Design in Submicron
CMOS Technologies
Giovanni AnelliCERN - European Organization for Nuclear Research
Physics DepartmentMicroelectronics Group
CH-1211 Geneva 23 – [email protected]
Giovanni Anelli, CERNPuebla, December 2004
The MOST important thing…
Giovanni Anelli, CERNPuebla, December 2004
A second tip…
sRC1
)s(V)s(V)s(H
in
out −==gs
mmax C
g21fπ
=fRkT4i2
n ∆⋅= ∫−=2/T
2/T2
av dt)t(xT1limP
2
2
2)x(
e21)x(p σ
µ−−
πσ=
)e1(eLWII t
DS
t
GSnV
nV
0DDSφ
−φ −=α+γ=
∆ f1
WLCK
g1kTn4
fv
2ox
a
m
2in
2t
DS
n2I.C.Iβφ
=
qkT
t =φ
( )21.C.I41
41
.C.I61
21.)C.I(F
+⋅+
+=
2
2BGD,n
2TOT,n
DUT,n )f(G)f(V)f(V
)f(E−
=
L WA
L WA 2
C2
ox+=σ µββ∆
2/
L WtConst ox
Vth
4 N⋅⋅=σ∆
d)ld(FnL 2 ⋅⋅⋅µ=
Adn
AlR w π
⋅ρ=⋅ρ=2220
40
2
n nh8qmZE
ε−
=
2TGSDS )VV(
n2I −
β=
DSTGSGS
DSm I
n2)VV(
nVIg β
=−β
=∂∂
= )VV(1 TGS
0
−θ+µ
=µ
SAT_DS
E
SAT_DSds0 I
LVI
1g1r ⋅
=⋅λ
==
Giovanni Anelli, CERNPuebla, December 2004
The last warning before we start
The transparencies I will show you are sometimes quite full of details. You will not have the time to “digest” all
these details this week, but I wanted to prepare the transparencies so that you will have a COMPLETE
material for future reference.
During the presentation, I will help you in identifying in the transparencies and in the formulas the most
important issues that you should retain.
I also made a special effort in referencing all the sources (books and papers) I have been using when preparing the lectures. This should help you in finding easily what you
do not find in the transparencies…
Giovanni Anelli, CERNPuebla, December 2004
Outline
• Semiconductor physicsSilicon and silicon dioxide propertiesBand diagram conceptIntrinsic and doped semiconductorsCarrier mobility in silicon
• CMOS technology: an analog designer perspectiveThe MOS transistorDC characteristicsImportant formulasSmall signal equivalent circuitSome cross sections of real integrated circuits
Giovanni Anelli, CERNPuebla, December 2004
Outline
• Semiconductor physicsSilicon and silicon dioxide propertiesBand diagram conceptIntrinsic and doped semiconductorsCarrier mobility in silicon
• CMOS technology: an analog designer perspectiveThe MOS transistorDC characteristicsImportant formulasSmall signal equivalent circuitSome cross sections of real integrated circuits
Giovanni Anelli, CERNPuebla, December 2004
Insulators and (semi)conductors
S. M. Sze, Semiconductor Devices, Physics and Technology, John Wiley and Sons, 1985, p. 1
Giovanni Anelli, CERNPuebla, December 2004
Physical Properties of Si and SiO2
at room temperature (300 K)
Y. Taur and T. H. Ning, Fundamentals of Modern VLSI Devices, Cambridge University Press, 1998, p. 11.
Giovanni Anelli, CERNPuebla, December 2004
Silicon crystalline structure
Diamond lattice
structure
Covalent bonding
Orbitalsfilling
3p2
3s2
2p6
2s2
1s2
a = 0.513 nm for Silicon
NucleusS. M. Sze, Semiconductor Devices, Physics and Technology, John Wiley and Sons, 1985, p. 5.
Linus Pauling, General Chemistry, Dover, 1988, p. 128.
Giovanni Anelli, CERNPuebla, December 2004
From energy levels to bands
Allowed energy levels
E1
E2
E3
En
E0 (reference)
2220
40
2
n nh8qmZE
ε−
=
… putting more atoms together
(and remembering Pauli’s exclusion
principle)
Allowed energy band Z: atomic number
m0: free electron mass
q: electron charge
ε0: permittivity free space
h: Planck’s constant
n: positive integers(level number)
Forbidden energy gap
x
Giovanni Anelli, CERNPuebla, December 2004
Energy-band diagrams
Insulator Semiconductor Conductor Conductor
Valence Band
Conduction Band
Energy Gap
Valence Band
Conduction Band
Valence Band
Conduction Band
Energy Gap
Conduction Band
Empty allowed energy band
Full allowed energy band
Giovanni Anelli, CERNPuebla, December 2004
Intrinsic and doped silicon
Y. Taur and T. H. Ning, Fundamentals of Modern VLSI Devices, Cambridge University Press, 1998, pp. 10, 13, 14.E. S. Yang, Microelectronic Devices, McGraw-Hill International Editions, 1988, pp. 9, 15.
Fictitious particle
Giovanni Anelli, CERNPuebla, December 2004
Donors and acceptors
Intrinsic Semiconductor: small amount of impurities compared to the thermally generated electrons and holes
Donor level: the allowed energy level provided by a donor is neutral when occupied by an electron and positively charged when empty
Acceptor level: the allowed energy level provided by an acceptor is neutral when empty (= occupied by a hole) and negatively chargedwhen occupied by an electron (= empty)
Y. Taur and T. H. Ning, Fundamentals of Modern VLSI Devices, Cambridge University Press, 1998, p. 15.
Giovanni Anelli, CERNPuebla, December 2004
Carrier density vs Temperature
N-type semiconductor
Electrons are the majority carriers
Intrinsic carrier density (= hole density)
kTE
vc2i
g
eNNn−
⋅⋅=
S. M. Sze, Semiconductor Devices, Physics and Technology, John Wiley and Sons, 1985, p. 27
Giovanni Anelli, CERNPuebla, December 2004
Mobility vs T and ND
ND: doping concentration
EEmqv n
e
md µ−=
τ−=
vd = drift velocity
τm = mean free time between collisions
me = conductivity effective mass
E = electric field
S. M. Sze, Semiconductor Devices, Physics and Technology, John Wiley and Sons, 1985, p. 33.
Giovanni Anelli, CERNPuebla, December 2004
Mobility vs doping
Y. Taur and T. H. Ning, Fundamentals of Modern VLSI Devices, Cambridge University Press, 1998, p. 20.
SIL
1111µ
+µ
+µ
=µ
µ = total mobility
µL = mobility due to lattice scattering
µI = mobility due to impurity scattering
µS = mobility due to surface scattering (the dominating factor in MOS transistors)
It is like for resistors in parallel: the smaller dominates!
Giovanni Anelli, CERNPuebla, December 2004
Carrier velocity vs Electric Field
R. S. Muller and T. I. Kamins, Device Electronics for Integrated Circuits, 2nd Edition, John Wiley and Sons, 1986, p. 36.
Giovanni Anelli, CERNPuebla, December 2004
Resistivity vs doping
)pn(q1
pn µ+µ=ρ
q = electronic charge
ρ = resistivity
n, p = carrier concentration
µn, µp = carrier mobility
Y. Taur and T. H. Ning, Fundamentals of Modern VLSI Devices, Cambridge University Press, 1998, p. 21.
Giovanni Anelli, CERNPuebla, December 2004
Outline
• Semiconductor physicsSilicon and silicon dioxide propertiesBand diagram conceptIntrinsic and doped semiconductorsCarrier mobility in silicon
• CMOS technology: an analog designer perspectiveThe MOS transistorDC characteristicsImportant formulasSmall signal equivalent circuitSome cross sections of real integrated circuits
Giovanni Anelli, CERNPuebla, December 2004
The MOS transistor
x
y
z
GATE
SOURCE
DRAIN
SUBSTRATEGSmDS vgi ⋅=
Transconductance
Y. Tsividis, Operation and Modeling of The MOS Transistor, 2nd edition, McGraw-Hill, 1999, p. 35
Giovanni Anelli, CERNPuebla, December 2004
CMOS technology
NMOS PMOSGG
n+ n+p+ p+ p+ n+
S Dsub S D well
n-wellp-substrate
PolysiliconOxideElectronsHoles
n+ source
n+ drain
NMOS layoutG
Giovanni Anelli, CERNPuebla, December 2004
Linear and Saturation regions
LINEAR REGION (Low VDS):Electrons (in light blue) are attracted to the SiO2 – Si Interface. A conductive channel is created between source and drain. We have a Voltage Controlled Resistor (VCR).
G
n+ n+
S D
SATURATION REGION (High VDS):When the drain voltage is high enough the electrons near the drain are insufficiently attracted by the gate, and the channel is pinched off. We have a Voltage Controlled Current Source (VCCS).
G
n+ n+
S D
Giovanni Anelli, CERNPuebla, December 2004
Drain current vs Drain voltage
0.0E+00
5.0E-06
1.0E-05
1.5E-05
2.0E-05
2.5E-05
3.0E-05
0.0 0.5 1.0 1.5 2.0 2.5
VDS [ V ]
I DS [
A ]
Saturation region (VCCS)
Linear region (VCR)
Output conductance
@ three different VGS
Locus of IDS_SAT vs VDS_SAT
Giovanni Anelli, CERNPuebla, December 2004
Equations: strong inversion
DSDS
TGSDS V)2
nVVV(I −−β= LINEAR REGION:
SAT_DSTGS
DS Vn
VVV =−
<
DSGS
DSm V
V I g β=
∂∂
=Transconductance:
2TGSDS )VV(
n2I −
β=
DSTGSGS
DSm I
n2)VV(
nVIg β
=−β
=∂∂
=
SATURATION REGION:
SAT_DSTGS
DS Vn
VVV =−
>
Transconductance:
LWCox µ=βx.1
gggn
m
mbm ≈+
=ox
SiOox t
C 2ε
=BS
DSmb V
Ig
∂∂
=
Giovanni Anelli, CERNPuebla, December 2004
Drain current vs Gate voltage
0.E+00
2.E-04
4.E-04
6.E-04
8.E-04
1.E-03
1.E-03
1.E-03
2.E-03
-0.4 0.0 0.4 0.8 1.2 1.6 2.0 2.4
VGS [ V ]
I DS [
A ]
Subt
hres
hold
regi
on
Line
ar re
gion
(gre
en) a
nd
satu
ratio
n re
gion
(red
)
High field (vertical and longitudinal)
effects
Giovanni Anelli, CERNPuebla, December 2004
Log(IDS) vs VGS
1.E-12
1.E-11
1.E-10
1.E-09
1.E-08
1.E-07
1.E-06
1.E-05
1.E-04
1.E-03
1.E-02
-0.4 0.0 0.4 0.8 1.2 1.6 2.0 2.4
VGS [ V ]
I DS [
A ]
LEAKAGE CURRENT
THRESHOLD VOLTAGE STRONG
INVERSION
WEAK INVERSION
SUBTHRESHOLD SLOPE
Giovanni Anelli, CERNPuebla, December 2004
Equations: weak inversion
)e1(eLWII t
DS
t
GSnV
nV
0DDSφ
−φ −=
then the drain current does not depend on VDS any longer (saturation)If tDS n4V φ>
t
GSnV
0DDS eLWII φ=
t
DS
GS
DSm n
IVIg
φ=
∂∂
=
Almost like a bipolar transistor!
K300mV25q
kTt @ ≈=φ
Giovanni Anelli, CERNPuebla, December 2004
Transcond. vs Gate voltage
0.E+00
1.E-05
2.E-05
3.E-05
4.E-05
5.E-05
6.E-05
7.E-05
8.E-05
9.E-05
1.E-04
-0.35 0.05 0.45 0.85 1.25 1.65 2.05 2.45
VGS [ V ]
g m [
S ]
Measurement made in the linear
region
Giovanni Anelli, CERNPuebla, December 2004
Output conductance
0.0E+00
5.0E-06
1.0E-05
1.5E-05
2.0E-05
2.5E-05
3.0E-05
0.0 0.5 1.0 1.5 2.0 2.5
VDS [ V ]
I DS [
A ]
∆V∆I
VDSVD VD’
IDS
IDID’
n+ n+
SG
D
∆LL
Dashed lines:ideal behavior
L-LL
VI
VIG D
out ∆∆
⋅∆
=∆∆
=
Giovanni Anelli, CERNPuebla, December 2004
Equations: output conductance
)V1()VV( n2
I DS2
TGSDS λ+−β
=
2SAT_DS
2TGSSAT_DS nV
2)VV(
n2I β
=−β
=
nVVV TGS
SAT_DS−
=
0.0E+00
5.0E-06
1.0E-05
1.5E-05
2.0E-05
2.5E-05
3.0E-05
0.0 0.5 1.0 1.5 2.0 2.5
VDS [ V ]
I DS [
A ]
SAT_DSDS
DSdsout I
VIgg ⋅λ=
∂∂
==SAT_DS
E
SAT_DSds0 I
LVI
1g1r ⋅
=⋅λ
==
)N,V(fLLL
LV1
DopingDSDS
where =∆∆−
∆⋅=λ
Giovanni Anelli, CERNPuebla, December 2004
Equations: addendum
( )SiSisbT VV φ−φ+⋅γ=∆ox
aSi
CNq2 ε
=γBulk effect
Sm
m'm Rg1
gg+
=Source parasitic resistance
)VV(1 TGS
0
−θ+µ
=µ
Vertical electric field effect
)VV(nL2
1Cg
21f TGS2
gs
mmax −
µπ
=π
= in s.i.Maximum frequency
K. R. Laker and W. M. C. Sansen, Design of Analog Integrated Circuits and Systems, McGraw-Hill, 1994, Chapter 1
Giovanni Anelli, CERNPuebla, December 2004
Equations: velocity saturation
For low values of the longitudinal electric field, the velocity of the carriers increases proportionally to the electric field (and theproportionality constant is the mobility). For high values of the electric field (3 V/µm for electrons and 10 V/µm for holes) the velocity of the carriers saturates.
scm10v)VV(vWCI 7
satTGSsatox.S.V_DS with =−=
satox.S.V_m vWCg =
Lv
21
Cg
21f sat
gs
m.S.Vmax_ π
=π
=
Giovanni Anelli, CERNPuebla, December 2004
gm / ID vs log(ID / W)
0
5
10
15
20
25
30
1E-11 1E-09 1E-07 1E-05 1E-03
ID / W
g m /
I D
W.I.
M.I.
S.I. &
V.S.
Weak Inversion (W.I.)
t
DSm n
Igφ
=tD
m
n1
Ig
φ=
Strong Inversion (S.I.)
DSm In
2g β=
DSD
m
I1
n2
Ig β
=
Velocity Saturation (V.S.)
satoxm vWCg =DS
satox
DS
m
IvWC
Ig
=
Giovanni Anelli, CERNPuebla, December 2004
Log(gm / ID) vs log(ID / W)
0.1
1
10
100
1E-11 1E-10 1E-09 1E-08 1E-07 1E-06 1E-05 1E-04 1E-03
ID / W
g m /
I D
Slope = - 0.5Strong inversion
Slope = - 1Velocity saturation
Giovanni Anelli, CERNPuebla, December 2004
The poor PMOS transistorG
DRAIN
SOURCE
2TGSDS )VV(
n2I −
β−=
DS
TGS
GS
DSm
In
2
)VV(n
V I g
β−=
=−β
−=
=∂∂
=
-3.0E-05
-2.5E-05
-2.0E-05
-1.5E-05
-1.0E-05
-5.0E-06
0.0E+00
-2.5 -2.0 -1.5 -1.0 -0.5 0.0
VDS [ V ]
I DS [
A ]
p+ p+ n+
S D well VT < 0 V
VGS < 0 V
IDS < 0 V
GATE WELL
n-well
-2.E-03-1.E-03-1.E-03
-1.E-03-8.E-04-6.E-04-4.E-04
-2.E-040.E+00
-2.4 -2.0 -1.6 -1.2 -0.8 -0.4 0.0 0.4
VGS [ V ]I D
S [
A ]
Giovanni Anelli, CERNPuebla, December 2004
Small-signal equivalent circuit
gsmvg 0r
G
S
D
GSmDS vgi ⋅=
2TGSQDSQ )VV(
n2I −
β= This equation fixes the bias point
This equation defines the small signal behavior
K. R. Laker and W. M. C. Sansen, Design of Analog Integrated Circuits and Systems, McGraw-Hill, 1994, p. 24.
Giovanni Anelli, CERNPuebla, December 2004
Small-signal equivalent circuit
gsmvg bsmbvg 0r
sbC
gsC
dbCgbC
gdC
DG
S
B
Giovanni Anelli, CERNPuebla, December 2004
The real thing!
SOI technology from IBMhttp://www-3.ibm.com/chips/gallery/
Giovanni Anelli, CERNPuebla, December 2004
The real thing!
Metallization exampleshttp://www-3.ibm.com/chips/gallery/
Giovanni Anelli, CERNPuebla, December 2004
Why is CMOS so widespread?
• The IC market is driven by digital circuits (memories, microprocessors, …)
• Bipolar logic and NMOS - only logic had a too high power consumption per gate
• Progress in the manufacturing technology made CMOS technologies a reality
• Modern CMOS technologies offer excellent performance (especially for digital): high speed, low power consumption, VLSI, low cost, high yield
CMOS technologies occupies an increasing portion of the IC market
… and this is why we will only talk about CMOS.
Giovanni Anelli, CERNPuebla, December 2004
The next three lectures
• Lecture 2: Noise and Matching in CMOS (Analog) Circuits• Lecture 3: Scaling Impact on Analog Circuit Performance• Lecture 4: Basic Building Blocks for Analog Design