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Introduction to Serial Attached SCSI (SAS) and Serial ATA (SATA)

Serial ATA (SATA) and Serial Attached SCSI (SAS) are two different protocols used for serial connections between hosts and peripherals in desktop, server, and other applications. SATA and SAS have several similarities in terms of data rate and signal requirements, but each technology is targeted for slightly different applications. This paper will present a general overview of each technology, including a description of some of the applications for SATA and SAS. A comparison between SATA and SAS is included to help describe why both technologies are supported and used together at times. Finally, some evaluation results using the Mindspeed M21250 quad channel reclocker is included to show how this device can perform to improve signal integrity with SATA and SAS systems.

SATA Overview:

Serial ATA is an evolution of the parallel ATA interface that was developed for use as an interconnect for desktop PCs, servers, and enterprise systems to connect a host system to peripheral devices such as hard disk drives, optical storage drives, etc. The transition from a parallel bus interconnect to a serial interconnect was largely driven by the need for increased data transfer rates. With a 16 bit parallel data bus, issues such as signal crosstalk and skew became significant as data transfer rates. These issues are resolved by using a serial architecture with differential signals instead of a parallel bus architecture. In addition, the cabling used with a serial interconnect is less complex and is physically smaller than what is used with a 16 bit parallel bus. A 40 pin cable is required for parallel ATA connections compared to a 7 pin cable for serial ATA connections. This means that cabling used for serial connections are physically much smaller than cables for parallel connections, which allow more flexibility in system design and allow for more storage devices to reside in the same location without the concern of large bulky cabling. SATA was designed such that is software compatible with legacy parallel interconnect protocol to minimize the impact on existing operating systems when SATA is employed.

SATA defines a 7-pin connector to be used for each interconnect, and SATA cables can be up to 1m in length for interconnect. See Figure 1 below for examples of connectors and cables used for serial vs. parallel ATA connec-tions.

Figure 1: Comparison of cable and connectors for parallel and serial ATA

Note that the physical size for the cables and connectors for Serial ATA are significantly smaller that the cables and connectors for parallel ATA. SATA connectors use only 25% of the PCB space required by Parallel ATA connectors, providing additional benefits in systems with multiple drives installed.

The physical data rates for SATA are 1.5 Gbps and 3.0 Gbps, with a roadmap for 6.0 Gbps operation in the future. Figures 2 and 3 below show some typical applications where SATA is used for the system interconnect.

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Serial ATA Connector Parallel ATA Connector Parallel and Serial ATA Cables

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Figure 2: Serial ATA application in a desktop

In a desktop application as illustrated in figure 2, the host is a PCI card installed in the PC or as part of the PC motherboard. The SATA drive(s) are connected using SATA connectors and cables. SATA drives are also used in enterprise servers and storage arrays, where multiple drives are used in each system to increase overall storage capacity. The Serial ATA protocol is used as the interconnect between the host and the drive in these systems, and communication to and from the drive is dictated by the SATA standard protocol. An application using SATA drives in a storage area network is shown in figure 3 below.

Figure 3: Serial ATA in a storage area network (SAN) application

The SATA drives are located inside each storage array and connected to the host con-troller using standard SATA cables and con-nectors. As systems are expanded to larger sizes, there is a need for longer lengths of interconnect between SATA hosts and drives. In larger server systems where the signal must travel through long backplanes, some signal conditioning could become necessary in order to maintain acceptable signal integrity throughout the system.

Switch

StorageArray

StorageArray

StorageArray

Server Server

Local Area Network (LAN)

Host Controller

SATA Drive

SATA Drive

StorageArray

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Serial Attached SCSI (SAS) Serial Attached SCSI, or SAS, is another protocol that can be used to interconnect between disk drives and host controllers. SAS was designed to be backwards compatible with SATA systems, although SAS systems offer more features than SATA systems. SAS offers for more capacity, easier scalability and expansion, and enhanced security over SATA systems. Where SATA was initially targeted for use in desktop PC applications, SAS was targeted for use in server systems. SAS systems are designed to operate in full-duplex mode, meaning that data can be transmitted and received to and from the drive simultaneously, compared to the half duplex mode supported with SATA, where communication can only take place in one direction at a time. In addition, SATA systems are designed to support connectivity with 1m cables to a single drive with a host port. SAS was designed to support connections with up to 8m cables, and can support the use of expanders which allow for connection to multiple SAS drives to a single host port. The physical connector used for SAS is different from the connector used for SATA; although a system backplane can be designed such that is can accept connections to either SATA or SAS cables. The SAS connector is backwards compatible with SATA connectors, but also includes additional pins which allow for full duplex operation of the drives.

In general, SAS drives are used in systems which require the highest performance in terms of data transfer and reliability, and SATA drives are used in systems where cost is a more important factor than performance.

The next sections of this document present some details on the physical layer requirements for SAS and SATA systems.

Physical Layer Requirements of SAS/SATA Systems:

This section of the paper will present the requirements at the physical layer for SAS and SATA systems. The re-quirements include operating bit rates, output signal eye parameters, and timing requirements.

SAS and SATA systems operate with data rates of 1.5 Gbps and 3.0 Gbps, with plans to migrate to 6.0 Gbps operation in the future. Data is transmitted using an 8b/10b encoding scheme using standard 8b/10b coding conventions. For SATA, the electrical interface specifications are defined as follows:

Gen1i: 1.5 Gbps interface for internal host to device applicationsGen1m: 1.5 Gbps interface for short backplane and external desktop applicationsGen 2i: 3.0 Gbps interface for internal host to device applicationsGen2m: 3.0 Gbps interface for short backplane and external desktop applicationsGen2x: 3.0 Gbps Extended length interface for long backplane and system to system applications

Table 1 below shows the electrical specifications for SATA signals at the various interface points as defined above.

Table 1: SATA Electrical Specifi cations

Parameter Units Gen 1i min

Gen 1i max

Gen1m min

Gen1m max

Gen1x min

Gen1x max

Gen2i min

Gen2i max

Gen2m min

Gen2m max

Gen2x min

Gen2x max

Data Rate Gbps 1.5 1.5 1.5 1.5 1.5 1.5 3 3 3 3 3 3AC Coupling Capacitance nF - 12 - 12 - 12 - 12 - 12 - 12

Common Mode Transient Settling Time ns - 10 - 10 - 10 - 10 - 10 - 10

Tx Differential Output Voltage mVp-p 400 600 400 600 400 1600 400 700 400 700 400 1600

Tx Rise/Fall Time ps 100 273 100 273 67 273 67 136 67 136 67 136Tx Differential Skew ps - 20 - 20 - 20 - 20 - 20 - 15Tx AC Common Mode Voltage mVp-p - - - - - - - 50 - 50 - -

Tj at Connector UI - 0.355 - 0.355 - - - 0.3 - 0.3 - -Dj at Connector UI - 0.175 - 0.175 - - - 0.17 - 0.17 - -

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For SAS, compliance points are defined as follows:

IT: Internal connector, Tx portIR: Internal connector, Rx portCT: External connector, Tx portCR: External connector, Rx portXT: Expander or SAS initiator PHY, Tx portXR: Expander or SAS initiator PHY, Rx port

Table 2 below shows the electrical specifications for SAS signals at the various interface points as defined above.

Table 2: SAS Electrical Specifi cations

Parameter Units 1.5 Gbps min

1.5 Gbps max

3.0 Gbps min

3.0 Gbps max

Data Rate Gbps 1.5 1.5 3 3

AC Coupling Capacitance nF - 12 - 12

Tx Differential Output Voltage mVp-p 240 1600 240 1600

Tx Rise/Fall Time ps 67 273 67 137

Tx Differential Skew ps - 20 - 15

Tj at IR,CR,XR UI - 0.55 - 0.55

Dj at IR,CR,XR UI - 0.35 - 0.35

Note that the electrical specifications for SAS and SATA are similar to each other, which suggests that components that are used in the physical transport of signals can be used in SAS and SATA systems.

Figure 4: OOB Signal ExampleOut Of Band Signaling:

SATA and SAS protocols both support a signaling scheme call Out-of-band (OOB) signaling. OOB signaling is used to establish communication between a host and drive to identify the type of drive used in the system as well as the maximum operating data rate of the drive. An OOB signal is a tri-level signal that contains a pattern of “idle” signals and “burst” signals. An example of an OOB signal is shown in figure 4.

Burst Idle

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SATA defines two different OOB signals, COMRESET/COMINIT and COMWAKE. SAS identifies the same two OOB signals that SATA does, plus one additional OOB signal called COMSAS. The length of time for the burst and idle periods for each OOB signal is shown in table 3 below:

Table 3: Timing specifi cations for OOB signals

Signal Burst Time Idle Time Negation Time

COMWAKE 160 OOBI 160 OOBI 280 OOBI

COMRESET/COMINIT 160 OOBI 480 OOBI 800 OOBI

COMSAS 160 OOBI 1440 OOBI 2400 OOBI Note: OOBI is a fi xed value equal to one UI of the nominal data rate

A complete OOB sequence contains six burst/idle periods followed by the negation time, where the transmitted signal is an idle. The length of the idle time is used to identify the type and speed of the OOB signal that is being transmitted. An example of a complete COMRESET OOB signal is shown in figure 5 below:

Figure 5: COMRESET OOB Signal

320 ns106 .7 ns

After a PHY reset is issued, the SATA/SAS host controller sends a COMRESET OOB signal to the device, and waits to receive a COMRESET OOB signal to be returned from the device. If a COMRESET signal is sent and received between the host and device, the host then sends a COMWAKE signal to the device and waits to receive a COMWAKE signal to be returned from the device. If the host is a SATA host, then the SATA speed negotiation procedure begins after the host receives the COMWAKE from the device. If the host is a SAS/SATA host, then the host will send a COMSAS OOB signal to the device and look for the device to return the COMSAS to the host to confirm that the host is com-municating with a SAS device. If the device returns the COMSAS to the host, then the host is configured fro SAS operation and the SAS speed negotiation process begins. If the device does not return COMSAS to the host, then the host is configured for SATA operation and begins the SATA speed negotiation procedure.

Speed negotiation takes place between the host and device in order to determine the maximum data rate that the drive can support. For SATA systems, the speed negotiation procedure starts at the slowest data rate supported by the host and then the data rate is increased until the maximum data rate is identified. For SAS systems, the speed negotiation procedure begins with the maximum data rate supported and is decreased until successful com-munication is established.

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Using the M21250 in SAS/SATA systems:Mindspeed’s M21250 is a quad-channel clock and data recovery device that supports data rates from 42 Mbps to 3.2 Gbps. Each of the four channels can be configured for operation at a different data rate and is independent from the other channels within the device. For SATA/SAS applications where the signal must travel across long backplanes, backplane connectors, and/or cables, the M21250 can be used as a signal conditioning device to reduce jitter in the signal and enable longer transmission distances and better BER performance for systems.

The M21250 can be configured to support 1.5 Gbps and 3.0 Gbps, making it compatible with first and generation SAS/SATA systems. The output rise and fall time and differential voltage levels of the M21250 are compatible with SAS/SATA transmitter specifications and the high input sensitivity and input jitter tolerance of the M21250 also fit with the use of the M21250 as a SAS/SATA receiver device.

The M21250 provides a differential output that is either set to a logic high or a logic low, so support for OOB signaling is provided through the use of AC coupling. With a 56 pf AC coupling capacitor connected to the input and output ports of the M21250, the idle portions of the OOB signals are passed through with M21250 without distorting the OOB signal burst periods. To ensure that there is no “chatter” on the device outputs during idle periods, a pull down resistor of approximately 820 ohms is connected at the input N pins for each input channel of the M21250. Some measurement data for the M21250 that was taken with SAS and SATA data is presented in the following pages.

Test Setup:

The M21250 was evaluated with three different setups to verify operability with SAS/SATA systems. The first test was a functional test with a 1.5 Gbps SATA disk drive installed in a desktop PC. The high speed data path between the host and drive was broken and the M21250 was inserted in the middle of the data path as shown in figure 6 below:

Figure 6: Test setup with a desktop PC and SATA disk drive

Host Controller

SATA Drive

M21250

With the M21250 powered up and configured for operation t 1.5 Gbps, it was verified that read and write operations to the SATA drive were successful using the desktop PC.

Another functional test was performed using a 3 Gbps SAS/SATA protocol analyzer and hard drive to verify func-tional compliance to SAS and SATA protocol when the M21250 was inserted into the data path of the signals. The setup used for this evaluation is shown in the figure 7 below.

Figure 7: Test setup with SATA/AS protocol analyzer and SAS disk drive

SATA/SAS Protocol Generator/Analyzer M21250 EVM

3 Gbps SAS Drive

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The protocol analyzer was used to verify communication between the external SAS drive and the analyzer, and including verification of OOB signaling, speed negotiation, and protocol compliance of the external drive. With the M21250 EVM inserted into the high-speed data path and configured for operation at 3.0 Gbps, the functional tests were all passed. A summary of the functional testing performed with the M21250 EVM for SAS/SATA systems is shown in table 4 below.

Table 4: Functional SATA/SAS test results summary

Test Description Test ResultFunctional test with desktop PC and 1.5 Gbps SATA drive PassedProtocol Generator/Analyzer test with 3.0 Gbps SAS Passed*Protocol Generator/Analyzer test with 3.0 Gbps SATA Passed* *Note that the M21250 does not lock to OOB signals, however OOB patterns do pass through the M21250 to allow for proper communication between initiator and host devices

Output parameter testing was performed on the outputs of the M21250 using a high speed pattern generator and high bandwidth, real oscilloscope to take eye parameter measurements on the device outputs. The setup used for this testing is shown in figure 8 below.

Figure 8: Test setup with high-speed pattern generator and real time oscilloscope

High Speed Pattern Generator

M21250 EVM Real Time Oscilloscope

Results for the testing using the above setup are presented in the following pages.

1.5 Gbps SAS testing:

A summary of the test results is below, followed by details on each test performed.

1.5G SAS Test Results Specifi cation Limits Measured Value ResultMaximum Rise Time <=273 ps 79.86 ps PASSMinimum Rise Time >=67 ps 73.79 ps PASSMaximum Fall Time <=273 ps 69.25 ps PASSMinimum Fall Time >=67 ps 65.43 ps FAILMinimum Eye Opening Zero Mask Failures 0 PASSTJ 550 mUI Max 154 mUI PASSDJ 350 mUI Max 115 mUI PASS

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Minimum Rise Time = 73.79ps, Maximum Rise Time = 79.86 ps

Minimum Fall Time = 65.43 ps, Maximum Fall Time = 69.25 ps

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Eye diagram from M21250 output showing compliance to Eye Mask Testing

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TJ = 154 mUI, DJ = 115 mUI

3.0 Gbps SAS Test Results:

Test Results for 3.0 Gbps SAS testing of the M21250 as included below.

3.0 G SAS Test Results Specifi cation Limits Measured Value ResultMaximum Rise Time <=137 ps 74.95 ps PASSMinimum Rise Time >=67 ps 69.70 ps PASSMaximum Fall Time <=137 ps 65.28 ps PASSMinimum Fall Time >=67 ps 61.66 ps FAILMinimum Eye Opening Zero Mask Failures 0 PASSTJ 550 mUI Max 111 mUI PASSDJ 350 mUI Max 51 mUI PASS

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Minimum Rise Time = 69.7 ps, Maximum Rise Time = 74.95 ps

Minimum Fall Time = 61.66 ps, Maximum Fall Time = 65.28 ps

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Eye Diagram showing compliance to eye mask testing

M21250 Bathtub Curve for 3.0 Gbps SAS testing

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Composite histogram for M21250, TJ = 111 mUI, DJ = 51 mUI

1.5 Gbps SATA Test Results:

Results from testing the M21250 with 1.5 Gbps SATA for gen 1x applications are presented below.

1.5G SATA Gen 1x Test Results Specifi cation Limits Measured Value ResultVdiff TX, Minimum TX differential output voltage >=400 mV 914 mV PASSVdiff TX, Maximum TX differential output voltage <= 50 mV 0 mV PASSTX Rise Time 67 ps to 273 ps 65.3 ps FAILTX Fall Time 67 ps to 27 3ps 61.7 ps FAILTJ after connector, clock to data, fBAUD/1667 <= 550 mUI 50 mUI PASSDJ after connector, clock to data, fBAUD/1667 <= 350 mUI 20 mUI PASSTJ at connector, clock to data, fBAUD/500 <= 470 mUI 30 mUI PASSDJ at connector, clock to data, fBAUD/500 <= 220 mUI 10 mUI

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TX Rise Time Measurements

TX Fall Time Measurements

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Bathtub curve for fBAUD/1667

Composite Histogram for fBAUD/1667

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Bathtub Curve for fBAUD/500

Composite Histogram for fBAUD/500

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3.0 Gbps SATA Test Results:

Results from testing the M21250 with 3.0 Gbps SATA for gen 2x applications are presented below.

3.0G SATA Gen 2x Test Results Specifi cation Limits Measured Value Result

Vdiff TX, Minimum TX differential output voltage >=400 mV 940 mV PASS

Vdiff TX, Maximum TX differential output voltage <= 50 mV 0 mV PASS

TX Rise Time 67 ps to 136 ps 65.2 ps FAIL

TX Fall Time 67 ps to 136ps 61.6 ps FAIL

TJ after connector, clock to data, fBAUD/1667 <= 550 mUI 50 mUI PASS

DJ after connector, clock to data, fBAUD/1667 <= 350 mUI 20 mUI PASS

TX Rise Time Measurements

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TX Fall Time Measurements

Bathtub Curve for fBAUD/1667

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In general the M21250 was compliant to output specifications for SAS and SATS 1.5 Gbps and 3.0 Gbps systems. The failures to the specifications occurred because the M21250 rise/fall times are on the fast edges of the specifications. It should be noted that the measure-ments recorded above were obtained using a high performance evaluation board, using high quality SMA connec-tors on the EVM to launch the signal from the EVM to the real time Oscil-loscope. In an actual system environ-ment, the signal at the output from the M21250 will likely travel through some backplane trace and potentially a lossy connector, this will tend to slow down the rise/fall time from the M21250 to meet SAS/SATA specifications. Composite Histogram for fBAUD/1667

OOB Signaling with the M21250

By definition, an OOB signal requires three discrete signal levels, burst high, burst low, and idle. The idle level is defined to be 0V, and is the common mode voltage level of the burst section of the OOB signal. The M21250 output buffer is a PCML digital buffer, designed to drive to either a high or low output logic level. This is compliant with normal SATA/SAS data, but is not compliant with OOB signals. To achieve the output electrical idle level from the M21250, AC coupling capacitors are installed at the device outputs, with the AC coupling capacitor value selected so that the signal level falls to the electrical idle state within an acceptable time period to allow for compliance to OOB specifications. Mindspeed recommends using an AC coupling capacitor value of 56 pF to allow the OOB signal to pass through the M21250 without distorting the signal. The following waveforms show the OOB signal at the output of the M21250 with a 56 pF AC coupling capacitor installed:

The signal shown here is the burst portion of an OOB signal, followed by the transition to the idle portion of the OOB signal. The two lines represent the differential outputs from the M21250 and are superimposed on each other. The following figure shows one side of the M21250 differential output when transitioning between idle and burst portions of the OOB signal.

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A measurement of the idle time for a COMRESET signal that has been sent through the M21250 is shown below. The idle time measured is 317 ns, compared to a “shall detect” range of 304 to 336 ns.

Due to the long idle times found in OOB signals, the M21250 will lose phase lock and will lock to the reference frequency connected to the device when OOB signals are connected to the input of the M21250. The M21250 does not achieve phase lock to the OOB signal, but the OOB burst and idle signals are passed through the M21250 with minimal distortion, and allow for compliance to SAS/SATA OOB specifications at the system level.

Summary:

The M21250 can be used in 1.5 Gbps and 3.0 Gbps SAS and SATA systems as a signal conditioner as needed. The output signals from the M21250 are compatible with SAS/SATA requirements and with the ap-propriate selection of AC coupling capacitor values, the M21250 can also support OOB signaling for SAS/SATA systems.

For additional information on the M21250, please contact your local Mindspeed representative.