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INDIAN INSTITUTE OF TECHNOLOGY ROORKEE
Introduction to VLSI Physical Design
Bishnu Prasad Das
Assistant Professor,
Department of Electronics and Communication Engineering,
IIT Roorkee
Email: [email protected]
2IEP course on High Level Design to silicon at IIT Roorkee during 24th- 27th Feb 2018
VLSI Design Cycle
• Large number of devices
• Optimization requirements for high performance
• Time-to-market competition
• Cost
3IEP course on High Level Design to silicon at IIT Roorkee during 24th- 27th Feb 2018
VLSI Design Cycle
1. System Specification
2. Architectural Design
3. Functional Design
4. Logic Design
5. Circuit Design
6. Physical Design
7. Design Verification
8. Fabrication
9. Packaging, Testing, and Debugging
4IEP course on High Level Design to silicon at IIT Roorkee during 24th- 27th Feb 2018
A Simple VLSI Design Cycle
Architectural
Design
Functional
Design
Logic Design
Circuit Design
X=(AB*CD)+(A+D)+(A(B+C))
Y=(A(B+C))+AC+D+A(BC+D))
Physical Design
Fabrication
Packaging
System
Specification
5IEP course on High Level Design to silicon at IIT Roorkee during 24th- 27th Feb 2018
Design Styles
Custom
Standard Cells
Compiled CellsMacro Cells
Cell-based
Pre-diffused
(Gate Arrays)Pre-wired
(FPGAs)
Array-based
Semicustom
Design Styles
6IEP course on High Level Design to silicon at IIT Roorkee during 24th- 27th Feb 2018
Design Styles
Parameters Custom Cell-based Pre-diffused Pre-wired
Density Very High High High Medium
Performance Very High High High Medium
Flexibility Very High High Medium Low
Design time Very High Short Short Very Short
Manufacturing
timeMedium Medium Short Very Short
Cost
(low volume)Very High High High Low
Cost
(high volume)Low Low Low High
7IEP course on High Level Design to silicon at IIT Roorkee during 24th- 27th Feb 2018
Full-Custom Design Style
8IEP course on High Level Design to silicon at IIT Roorkee during 24th- 27th Feb 2018
Standard Cell Design Style
9IEP course on High Level Design to silicon at IIT Roorkee during 24th- 27th Feb 2018
Gate Array Design Style
10IEP course on High Level Design to silicon at IIT Roorkee during 24th- 27th Feb 2018
FPGA Design Style
11IEP course on High Level Design to silicon at IIT Roorkee during 24th- 27th Feb 2018
VLSI Physical Design
• Physical Design – convert the netlist into a geometric
representation. The outcome is called a layout.
12IEP course on High Level Design to silicon at IIT Roorkee during 24th- 27th Feb 2018
Simplified Cycle of Physical IC Design
13IEP course on High Level Design to silicon at IIT Roorkee during 24th- 27th Feb 2018
Physical Design Cycle
14IEP course on High Level Design to silicon at IIT Roorkee during 24th- 27th Feb 2018
New Trends in Physical Design
There are many new trends in the industry, which seek to
significantly alter the IC design flow. The major contributing
factors are: Increasing interconnect delay
Increasing interconnect area
Increasing number of metal layers
Increasing planning requirement
Synthesis
As a result, in high performance chips, interconnect delay
must be considered from very early design stages. To
reduce interconnect delay, several methods can be
employed: Chip level signal planning
Over-the-cell routing
15IEP course on High Level Design to silicon at IIT Roorkee during 24th- 27th Feb 2018
New Physical Design Cycle
Floorplanning
and Placement
Partitioning
Routing
Is
timing, size
OK?
Routing complete
Compaction
Is
timing
OK?
Extraction and
Verification
Can
Violation be fixed
by re-floorplan
Can be
fixed by
rerouting
Physical Design
Fabrication
Circuit Design
Yes
Yes
Yes
Yes
Yes
No
No
No
NoNo
Timing, size constraint
Size violation
timing violation
16IEP course on High Level Design to silicon at IIT Roorkee during 24th- 27th Feb 2018
History of Physical Design
Board layout - started in early 60’s
Standard cell place and route - developed in 70’s
Over-the-cell routing – widely applied in 80’s
Role of physical design significantly increase in 90’s
Physical design has become a dominant force in overall
design cycle Due to the deep submicron scaling
Connection with logic synthesis expanded
Interconnect optimization is of significance
17IEP course on High Level Design to silicon at IIT Roorkee during 24th- 27th Feb 2018
Circuit Models
• Abstraction: A representation that shows relevant
features without associated details.
1. Architectural
2. Logic
3. Geometrical
• Synthesis: Generation of a circuit model from a less
detailed one.
18IEP course on High Level Design to silicon at IIT Roorkee during 24th- 27th Feb 2018
Abstractions of Circuit Model
Set of operation such as data
computation or transfer
A set of logic function
A set of geometrical objects
19IEP course on High Level Design to silicon at IIT Roorkee during 24th- 27th Feb 2018
Views of Circuit Models
Behavioral views: Describe the function of the circuit
regardless of its implementation.
Structural views: Describe a model as an interconnection of
components.
Physical views: relate to physical objects (e.g. transistors) of
a design.
20IEP course on High Level Design to silicon at IIT Roorkee during 24th- 27th Feb 2018
Level of Abstractions and Views
21IEP course on High Level Design to silicon at IIT Roorkee during 24th- 27th Feb 2018
Gajaski and Kuhn’s Y Chart
22IEP course on High Level Design to silicon at IIT Roorkee during 24th- 27th Feb 2018
Synthesis
Architecture-level or High-level synthesis
Generating structural views of a architectural-level model
Logic-level synthesis
Generating structural views of a logic-level model
Geometrical-level synthesis
Creating physical views at the geometrical level
Also called as physical synthesis
23IEP course on High Level Design to silicon at IIT Roorkee during 24th- 27th Feb 2018
Design Domains
Physical partitions
Floorplans
Cell layout
Transistor layout
Module layout
Behavioral
domain
Structural
domain
Physical domain
Top-down design methodology
24IEP course on High Level Design to silicon at IIT Roorkee during 24th- 27th Feb 2018
Synthesis
Architectural Level…
PC = PC + 1; // increment the Program Counter
FETCH(PC); // fetch next instruction
DECODE(INST); // decode the instruction
…
Logic Level
Geometrical Level
Physical view
Structural viewBehavioral view
Technology mapping
Physical design
25IEP course on High Level Design to silicon at IIT Roorkee during 24th- 27th Feb 2018
Significance of Physical Design
Many existing solutions are still very suboptimal E.g. placement
Interconnect dominates No physical layout, no accurate interconnect
More new physical and manufacturing effects pop up Crosstalk noise, etc.
OPC (manufacturability), etc.
Physical design is the key linking step between higher level
planning/optimization and lower level modeling
26IEP course on High Level Design to silicon at IIT Roorkee during 24th- 27th Feb 2018
References
1. Sherwani, N.A., “Algorithm for VLSI Physical Design
Automation”, 2nd Ed., Kluwer. 1999
2. G. De Micheli, Synthesis and Optimization of Digital
Circuits, McGraw-Hill, 1994
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