inturrept.pptx

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GROUP NAME:-

Destiny

INTERRUPT Definition:- An interrupt is an asynchronous signal indicate for an

event which needs processor’s attention immediately regardless to the instruction it executes at this moment.

It’s like a Doorbell.

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Mohd. Moinul Hoque, Lecturer, CSE, AUST

CSE 307 - Microprocessors

Hardware Interrupt

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A signal created and send to the CPU that is

cauesd by some action taken by a hardware

device is called harware interrupt .

for example :

from the keyboard we will

press the key to do some action, this

pressing of key in keyboard will generate

a signal which is given to the processor to do

action,such interrupts are called Hardware interrupts. But how does the CPU attends to it?

it is usually busy doing several other operations



• The CPU executes other program, as soon as a key is pressed, the Keyboard generates an interrupt. The CPU will response to the interrupt – read the data. After that returns to the original program. So by proper use of interrupt, the CPU can serve many devices at the “same time”

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CSE 307 - Microprocessors 7

Interrupts

• An interrupt is considered to be an emergency signal

that may be serviced.– The Microprocessor may respond to it as soon as

possible.

• What happens when microprocessor is interrupted ?– When the Microprocessor receives an interrupt signal,

it suspends the currently executing program and jumps

to an Interrupt Service Routine (ISR) to respond to the

incoming interrupt.– Each interrupt will most probably have its own ISR.



What Is Interrupt Service Routine?

• Interrupt service routine is a software routine

that hardware invokes response to an interrupt.

ISR’s examine an interrupt and determine how

to handle it .ISR’s handle the interrupt ,and the

return logical interrupt value

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Features of ISR

• The main features of the ISR are• Interrupts can occur at any time they are

asynchronous. ISR’s can call for asynchronous interrupts.

• Interrupt service mechanism can call the ISR’s from multiple sources.

• ISR’s can handle both maskable and non maskable interrupts. An instruction in a program can disable or enable an interrupt handler call.

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Features of ISR

• ISR on beginning of execution it will disable other devices interrupt services. After completion of the ISR execution it will re initialize the interrupt services.

• The nested interrupts are allowed in ISR for diversion to other ISR.

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Interrupt request

• Assume an interrupt req arrives during execution of instruction i.

• The processor first completes execution of instruction i by load the address of the first instruction of the interrupt-service routine.

• Assume this address is hardwired in the processor.• After execution of interrupt service routine , the

processor has to come back to instruction i+1.

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Contd….• Hence, when an interrupt occurs, the content of

PC, which currently point to the i+1, must be put into the temporary storage.

• At return of interrupt service routine reloads the PC from that temp storage location, causing execution to resume at instruction i+1.

• In many processor , the return address is saved on the processor stack. Alternatively, saved in temp register.

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ACK interrupt

• As part of interrupt, the processor must inform the device that its request has been recognized so that it may remove its interrupt- req signal.

• It may accomplished by special signal on the bus. • An interrupt- Acknowledge signal.

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Types of harware interrupt

Hardware interrupts can be classified into

two types • Maskable Interrupt

• Non Maskable interrupt

Maskable Interrupt

The hardware interrupt which can be delayed when when a much higest priority interrupt has occurred to the processor.it can be disabled by using interrupt mask

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Non Maskable interrupt:-

There are some interrupts which cannot be masked out or ignored by the processor. These are associated with high priority tasks which cannot be ignored (like memory parity or bus faults). In general, most processors support the Non-Maskable Interrupt (NMI). This interrupt has absolute priority, and when it occurs, the processor will finish the current memory cycle, then branch to a special routine written to handle the interrupt request.

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Interrupts can also be classified into:-

• Vectored interrupts• Non vectored interrupts

Vectored Interrupt:-

An interrupt vector is the memory location of an interrupt handler, which prioritizes interrupts and saves them in a queue if more than one interrupt is waiting to be handled.

Non Vectored interrupt:-

The address of the service routine needs to be supplied externally by the device

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Types Of Interrupt• Classification of Interrupts According to

Periodicity of Occurrence:• Periodic Interrupt: If the interrupts occurred at

fixed interval in timeline then that interrupts are called periodic interrupts

• Aperiodic Interrupt: If the occurrence of interrupt cannot be predicted then that interrupt is called aperiodic interrupt.

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Types of interrupt

• Classification of Interrupts According to the Temporal Relationship with System Clock:

• Synchronous Interrupt: The source of interrupt is in phase to the system clock is called synchronous interrupt. In other words interrupts which are dependent on the system clock. Example: timer service that uses the system clock.

• Asynchronous Interrupts: If the interrupts are independent or not in phase to the system clock is called asynchronous interrupt.

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Responding to Interrupts

• Responding to an interrupt may be immediate or delayed depending on whether the interrupt is maskable or non-maskable and whether interrupts are being masked or not.

• There are two ways of redirecting the execution to the ISR depending on whether the interrupt is vectored or non-vectored.– Vectored: The address of the subroutine is already

known to the Microprocessor– Non Vectored: The device will have to supply the

address of the subroutine to the Microprocessor



The 8085 Interrupts

• When a device interrupts, it actually wants the MP to give a service which is equivalent to asking the MP to call a subroutine. This subroutine is called ISR (Interrupt Service Routine)

• The ‘EI’ instruction is a one byte instruction and is used to Enable the interrupts.

• The ‘DI’ instruction is a one byte instruction and is used to Disable the interrupts.

• The 8085 has a single Non-Maskable interrupt.– The non-maskable interrupt is not affected by the

value of the Interrupt Enable flip flop.



Interrupt Flags Interrupt Flag (IF):- A bit that is automatically set if the interrupt source (event)

happens.

Global Interrupt Enable (GIE):- Enables (if set) all Un-masked interrupts (interrupts with IE=1) or

disables (if cleared) all interrupts.

Interrupt Enable (IE):- If the GIE was ‘1’, this bit forces the CPU to respond to the

interrupt signal when IF=1 when the waited event happens.

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interrupts• When the event (interrupt source) happens, the following steps

happen:

1) The corresponding interrupt flag (IF) will equal ‘1’.

2) If the interrupt enable (IE) was ‘1’, and the global interrupt enable (GIE) was ‘1’ also, the GIE is cleared by hardware to avoid responding any further interrupt

3) The return address is pushed into the stack and the PC is loaded with 0004h (the interrupt vector).

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Interrupts

4) In the ISR, you can determine the source of interrupt by polling the interrupt flag bits and do the required action for it.

5) At the end of the ISR, you’ve to clear the IF in software then set the GIE bit in the end of the ISR code.

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Why do we use interrupts?

If interrupts are not used, the control unit goes through the ordinary instruction cycle:

• Fetch instruction. • Decode the instruction.• Execute it.

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Contd…..• When interrupts are used in the microprocessor, the

control unit checks first if there is an interrupt signal or not.

• If the interrupt signal was ‘1’, it goes through interrupt cycle:

I. Store the current address into the stack. (the address of the next instruction which should

have been loaded if there is no interrupt).

II. Load the PC with the interrupt vector address.

III. Make the GIE=‘0’.

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Fetch

Decode

Execute

Interrupt signal?

Stack <-- return address

PC <-- Interrupt vector

GIE=0

Interrupt cycle Instruction cycle

In S.W., make IF=0

T F



The last instruction in the ISR should be:

RETFIE (return from interrupt).

This instruction makes the control unit loads the PC with the address stored in the stack so that the original program can continue.

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Issues in Implementing INTR Interrupts

• How long must INTR remain high?– The microprocessor checks the INTR line one clock cycle

before the last T-state of each instruction.– The INTR must remain active long enough to allow for the

longest instruction.– The longest instruction for the 8085 is the conditional CALL

instruction which requires 18 T-states.

• Therefore, the INTR must remain active for 17.5 T-states.

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• How long can the INTR remain high?– The INTR line must be deactivated before the EI is

executed. Otherwise, the microprocessor will be interrupted again.

– Once the microprocessor starts to respond to an INTR interrupt, INTA becomes active (=0).

Therefore, INTR should be turned off as soon as the INTA signal is received.

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• Can the microprocessor be interrupted again before the completion of the ISR?– As soon as the 1st interrupt arrives, all maskable

interrupts are disabled. – They will only be enabled after the execution of

the EI instruction.

Therefore, the answer is: “only if we allow it to”.

If the EI instruction is placed early in the ISR, other interrupt may occur before the ISR is done.

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How Interrupts Are Handled?

• Different routines handle different interrupts –called Interrupt Service Routines (ISR).

• When CPU is interrupted– It stops what it was doing, and context is saved. – A generic routine called Interrupt Handling

Routine (IHR) is run which • Examines the nature of interrupt• Calls the corresponding Interrupt Service Routine

(ISR) -- stored in lower part of memory.

• After servicing the interrupt, the saved address is loaded again to PC to resume the process again.

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• Interrupt

Processing

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There are three types ISR’s

• First Level Interrupt Handler (FLIH)

A FLIH is considered to be part of the lower half of a device driver or kernel. These interrupt handlers are platform specific, and usually service hardware requests, executing similar to Interrupt Routines (IRs) and Interrupt Requests (IRQs). They have short execution time. Their primary duty is to service the interrupt, or to record platform specific information which is only available at the time of the interrupt (As it is running in a lower level.) It may also schedule or execute a SLIH, if needed.

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• Second Level Interrupt Handler (SLIH)

These interrupt handlers are longer lived then FLIHs. In this way, it is similar to a task or process. SLIHs are normally executed and managed by a kernel program, or by FLIHs.

• Nested Interrupt Handlers

When an interrupt handler is executed and the Interrupt Flag (IF) is set, interrupts can still be executed during the current interrupt. This is known as a nested interrupt.

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Interrupt Vectors and the Vector Table

• An interrupt vector is a pointer to where the ISR is stored in memory.

• All interrupts (vectored or otherwise) are mapped onto a memory area called the Interrupt Vector Table (IVT).– The IVT is usually located in memory (0000H -

00FFH).– The purpose of the IVT is to hold the vectors that

redirect the microprocessor when an interrupt arrives.



Example Let , a device interrupts the Microprocessor

using the RST 7.5 interrupt line.– Because the RST 7.5 interrupt is vectored,

Microprocessor knows , in which memory location it has to go using a call instruction to get the ISR address. RST7.5 is knows as Call 003Ch to Microprocessor. Microprocessor goes to 003C location and will get a JMP instruction to the actual ISR address. The Microprocessor will then, jump to the ISR location

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x86 Interrupt Vector Table (IVT)

Base AddressInterrupt Number

Description

0x000 0 Divide by 0

0x004 1 Single step (Debugger)

0x008 2 Non Maskable Interrupt (NMI) Pin

0x00C 3 Breakpoint (Debugger)

0x010 4 Overflow

0x014 5 Bounds check

0x018 6 Undefined Operation Code (OPCode) instruction

0x01C 7 No coprocessor

0x020 8 Double Fault

0x024 9 Coprocessor Segment Overrun

0x028 10 Invalid Task State Segment (TSS)

0x02C 11 Segment Not Present

0x030 12 Stack Segment Overrun

0x034 13 General Protection Fault (GPF)

0x038 14 Page Fault

0x03C 15 Unassigned

0x040 16 Coprocessor error

0x044 17 Alignment Check (486+ Only)

0x048 18 Machine Check (Pentium/586+ Only)

0x05C 19-31 Reserved exceptions

0x068 - 0x3FF 32-255 Interrupts free for software use



Five hardware interrupts are:

• TRAP• RST 7.5• RST 6.5• RST 5.5• INTR

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TRAPRST7.5RST6.5RST 5.5INTRINTA

8085



TRAP (PIN-6)• Non- maskable• Has highest priority• Can not disable.• Edge & level triggered• Used for power failure & emergency shut off.

How a TRAP interrupt may be masked???

• TRAP interrupts can also be masked by resseting the microprocessor. There is no other way to mask it

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RST 7.5• Maskable interrupt.• Has 2nd highest priority.• +ve edge triggered only.• Vector address of this interrupt is 003CH

How It may be masked??

• It can also be reset or masked by reseting microprocessor. It can also be resseted by DI instruction

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RST 6.5 and 5.5

• Maskable interrupt.• 3rd highest priority.• Level triggered only.


• when RST 6.5 pin is at logic 1,INTE flip flop is set. RST 5.5 has 4th highest priority.it can be masked by giving DI instruction or by reseting microprocessor

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INTR

• Maskable interrupt.• Lowest priority.• Level triggered.


• It can be disabled by reseting the microprocessor or by DI instruction

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INTR

• The following sequence of events occurs when INTR signal goes high

• The 8085 checks the status of INTR signal during execution of each signal

• If INTR signal is high , then 8085 complete its current instruction and sends its active low interrupt acknowledge signal, if the interrupt is enabled

• On receiving the instruction, the 8085 save the address of next instruction on stack and execute received instruction

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ANY QUESTION????

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inturrept.pptx