Inveters

After completion of this lesson the reader will be able to:

(i) Identify the essential components of a voltage source inverter. (ii) Explain the principle behind dc to ac conversion. (iii) Identify the basic topology of single-phase and three-phase inverters and explain

its principle of operation. (iv) Explain the gate drive circuit requirements of inverter switches.

The word inverter in the context of power-electronics denotes a class of power conversion (or power conditioning) circuits that operates from a dc voltage source or a dc current source and converts it into ac voltage or current. The inverter does reverse of what ac-to-dc converter does (refer to ac to dc converters). Even though input to an inverter circuit is a dc source, it is not uncommon to have this dc derived from an ac source such as utility ac supply. Thus, for example, the primary source of input power may be utility ac voltage supply that is converted to dc by an ac to dc converter and then inverted back to ac using an inverter. Here, the final ac output may be of a different frequency and magnitude than the input ac of the utility supply. [The nomenclature inverter is sometimes also used for ac to dc converter circuits if the power flow direction is from dc to ac side. However in this lesson, irrespective of power flow direction, inverter is referred as a circuit that operates from a stiff dc source and generates ac output. If the input dc is a voltage source, the inverter is called a voltage source inverter (VSI). One can similarly think of a current source inverter (CSI), where the input to the circuit is a current source. The VSI circuit has direct control over output (ac) voltage whereas the CSI directly controls output (ac) current. Shape of voltage waveforms output by an ideal VSI should be independent of load connected at the output.] The simplest dc voltage source for a VSI may be a battery bank, which may consist of several cells in series-parallel combination. Solar photovoltaic cells can be another dc voltage source. An ac voltage supply, after rectification into dc will also qualify as a dc voltage source. A voltage source is called stiff, if the source voltage magnitude does not depend on load connected to it. All voltage source inverters assume stiff voltage supply at the input. Some examples where voltage source inverters are used are: uninterruptible power supply (UPS) units, adjustable speed drives (ASD) for ac motors, electronic frequency changer circuits etc. Most of us are also familiar with commercially available inverter units used in homes and offices to power some essential ac loads in case the utility ac supply gets interrupted. In such inverter units, battery supply is used as the input dc voltage source and the inverter circuit converts the dc into ac voltage of desired frequency. The achievable magnitude of ac voltage is limited by the magnitude of input (dc bus) voltage. In ordinary household inverters the battery voltage may be just 12 volts and the inverter circuit may be capable of supplying ac voltage of around 10 volts (rms) only. In such cases the inverter output voltage is stepped up using a transformer to meet the load requirement of, say, 230 volts. 33.1 How to Get AC Output From DC Input Supply? Figs. 33.1(a) and 33.1(b) show two schematic circuits, using transistor-switches, for generation of ac voltage from dc input supply. In both the circuits, the transistors work in common emitter configuration and are interconnected in push-pull manner. In order to have a single control signal

Version 2 EE IIT, Kharagpur 3

SuvraTypewritten textIntroduction to VSI

for the transistor switches, one transistor is of n-p-n type and the other of p-n-p type and their emitters and bases are shorted as shown in the figures. Both circuits require a symmetrical bipolar dc supply. Collector of n-p-n transistor is connected to positive dc supply (+E) and that of p-n-p transistor is connected to negative dc supply of same magnitude (-E). Load, which has been assumed resistive, is connected between the emitter shorting point and the power supply ground. In Fig. 33.1(a), the transistors work in active (amplifier) mode and a sinusoidal control voltage of desired frequency is applied between the base and emitter points. When applied base signal is positive, the p-n-p transistor is reverse biased and the n-p-n transistor conducts the load current. Similarly for negative base voltage the p-n-p transistor conducts while n-p-n transistor remains reverse biased. A suitable resistor in series with the base signal will limit the base current and keep it sinusoidal provided the applied (sinusoidal) base signal magnitude is much higher than the base to emitter conduction-voltage drop. Under the assumption of constant gain (hfe) of the transistor over its working range, the load current can be seen to follow the applied base signal. Fig. 33.2(a) shows a typical load voltage (in blue color) and base signal (green color) waveforms. This particular figure also shows the switch power loss for n-p-n transistor (in brown color). The other transistor will also be dissipating identical power during its conduction. The quantities in Fig. 33.2(a) are in per unit magnitudes where the base values are input supply voltage (E) and the load resistance (R). Accordingly the base magnitudes of current and power are E/R and E2/R respectively. As can be seen, the power loss in switches is a considerable portion of circuits input power and hence such circuits are unacceptable for large output power applications. As against the amplifier circuit of Fig. 33.1(a), the circuit of Fig. 33.1(b) works in switched mode. The conducting switch remains fully on having negligible on-state voltage drop and the non-conducting switch remains fully off allowing no leakage current through it. The load voltage waveform output by switched-mode circuit of Fig. 33.1(b) is rectangular with magnitude +E when the n-p-n transistor is on and E when p-n-p transistor is on. Fig. 33.2(b) shows one such waveform (in pink color). The on and off durations of the two transistors are controlled so that (i) the resulting rectangular waveform has no dc component (ii) has a fundamental (sinusoidal) component of desired frequency and magnitude and (iii) the frequencies of unwanted harmonic voltages are much higher than that of the fundamental component. The fundamental sine wave in Fig. 33.2(b), shown in blue color, is identical to the sinusoidal output voltage of Fig. 33.2(a). Both amplifier mode and switched mode circuits of Figs. 33.1(a) and 33.1(b) are capable of producing ac voltages of controllable magnitude and frequency, however, the amplifier circuit is not acceptable in power-electronic applications due to high switch power loss. On the other hand, the switched mode circuit generates significant amount of unwanted harmonic voltages along with the desired fundamental frequency voltage. As will be shown in some later lessons, the frequency spectrum of these unwanted harmonics can be shifted towards high frequency by adopting proper switching pattern. These high frequency voltage harmonics can easily be blocked using small size filter and the resulting quality of load voltage can be made acceptable.


- E

+ E

LOAD (R)S

Fig. 33.1 (a): A push-pull active amplifier circuit

- E

+ E

LOAD (R)

S

Fig. 33.1 (b): A push-pull switched mode circuit

* *


The magnitude, phase and frequency of the fundamental voltage waveform in Fig. 33.2(b) is solely determined by the magnitude of supply voltage and the switching pattern of the push-pull circuit shown in Fig. 33.1(b). Thus, as long as the transistors work in the switch-mode (fully on or fully off), the output voltage is essentially load-independent. 33.2 What If The Load Is Not Resistive? Circuit of Fig. 33.1(b) will not be able to output proper voltage waveform for a non-resistive load for the reasons mentioned below. Transistors used in the circuit of Fig. 33.1(b) are meant to carry only unidirectional current (from collector to emitter) and thus if the upper (n-p-n) transistor is on, the current must enter the star (*) marked terminal of the load and this same terminal will get connected to the positive dc supply (+E), other load terminal being at ground potential. When n-p-n transistor turns off and p-n-p type turns on, the load voltage and current polarities reverse simultaneously (p-n-p transistor can only carry current coming out of star marked end of load). Such one to one matching between the instantaneous polarities of load voltage and load current can be achieved only in purely resistive loads. For a general load the instantaneous current polarity may be different from instantaneous load-voltage polarity. As pointed out in section 33.1, the inverter switching-pattern fixes the output waveform irrespective of the load. Thus the magnitude, phase and frequency of the fundamental voltage output by a VSI is independent of the nature of load. Thus it turns out that for a non-resistive load the switches in the circuit of Fig. 33.1(b) should be able to carry bi-directional current and at the same time be controllable. [A mechanical switch realized using an electromagnetic contactor is one example of the bi-directional current carrying controllable switch. However electromagnetic contactors are not capable of operating at high frequency, in the range of kilohertz, and may not be suitable for present application.] If an anti-parallel diode is connected across each transistor switch, as shown in Fig. 33.3(a), the combination can conduct a bi-directional current. Now the transistor in anti-parallel with the diode may be considered as a single switch. [A major difference exists between this bi-directional electronic switch and a bi-directional current carrying mechanical switch. The mechanical switch can be subjected to bi-directional voltage. When off, the mechanical switch can block both positive and negative voltage across its terminals. The electronic switch of Fig. 33.3(a) can block only one polarity of voltage, the one that keeps the diode reverse biased. Under this polarity of voltage the switch can remain off as long as the base (or the gate) terminal is not given the turn-on signal. When applied voltage polarity is reversed the diode starts conducting and so the switch is not able to block the flow of reverse current.] In spite of unidirectional voltage blocking capability, the new electronic switch (similar to the one shown in Fig. 33.3(a)) suffices for the inverter application as pointed out in the following paragraphs. The push-pull circuit operation is now revisited using bi-directional current carrying switches. The modified circuit is shown in Fig. 33.3(b). It may be noted that both IGBT and BJT type transistors, when bypassed by anti-parallel diode, qualify as bi-directional current carrying switches. However, IGBT switch is controlled by gate voltage whereas the BJT


+ E

Gate (control)

Input / Output

Input / Output

Control Analogous to

Fig. 33.3(a): Bi-directional controlled switch

- E

LOAD

S

Fig. 33.3 (b): Modified push-pull circuit

*

+

_

D1

D2 Q2

Q1 SW1

SW2

switch is controlled using base current. [IGBT switches are easier to use, are much faster and are available in higher voltage and current ratings. As a result BJT switches are becoming obsolete.] In the circuit of Fig. 33.3(b), n-p-n transistor (Q1) together with diode (D1) constitutes the upper switch (SW1). Similarly lower switch (SW2) consists of p-n-p transistor (Q2) in anti-parallel with diode (D2). By applying positive base-to-emitter voltage of suitable magnitude to transistor Q1, the upper switch is turned on. Once the upper switch (diode D1or transistor Q1) is conducting star end of load is at +E potential and diode D2 of lower switch gets reverse biased. Transistor Q2 is also reverse biased due to application of positive base voltage to the transistors. Thus while switch SW1is conducting current, switch SW2 is off and is blocking voltage of magnitude 2E. Similarly when applied base voltage to the transistors is made negative, Q1 is reverse biased and Q2 is forward biased. This results in SW1 turning off and SW2 turning on. Now SW1 blocks a voltage of magnitude 2E. It may be interesting to see how diodes follow the switching command given to the transistor part of the switches. To illustrate this point some details of circuit operation with an inductive load, consisting of a resistor and an inductor in series, is considered. As is well known, current through such loads cannot change abruptly. The electrical inertial time constant of the load, given by its L (inductance) / R (resistance) ratio, may in general be large compared to the chosen switching time period of the transistor switches. Thus the transistors Q1 and Q2 may turn-on and turn-off several times before the load current direction changes. Let us consider the time instant when instantaneous load current is entering the star end of the load in Fig. 33.3(b). Now with the assumed load current direction when Q1 is given turn-on signal current flows from positive dc supply, through transistor Q1, to load. Next, when Q1 is turned-off and Q2 is turned on (but load current direction remaining unchanged) the load current finds its path through diode of lower switch (D2). Whether D2 or Q2 conducts, voltage drop across SW2 is virtually zero and it can be considered as a closed or a fully-on switch. In the following switching cycle when Q1 is turned on again (load current direction still unchanged) the load current path reverts back from D2 to Q1. It may not be difficult to see how this happens. While current flowed through D2 the load circuit got connected to negative emf (-E) of the supply. When Q1 conducts the positive (+E) emf supports the load current. The natural choice for load current is to move from D2 to Q1. In fact turning on of Q1 will make D2 reverse biased. The reader may repeat a similar exercise when the instantaneous load current comes out of the star end of load. Thus it will be evident that diodes do not need a separate command to turn on and off. Irrespective of the load current direction, turning on of Q1 makes SW1 on and


similarly turning off of Q1 (with simultaneous turn-on of Q2) makes SW2on. Q1 and Q2 are turned on in a complementary manner. It may not be difficult to see that the circuit of Fig. 33.3(b) will work satisfactorily for a purely resistive load and a series connected resistor-capacitor load too. The push-pull circuit of Fig. 33.3(b) has some technical demerits that have been discussed below. First, it needs a bipolar dc supply with identical magnitudes of positive and negative supply voltages. For practical reasons it would have been simpler if only one (uni-polar) dc source was required. In fact some circuit topologies realize a bi-polar dc supply by splitting the single dc voltage-source through capacitive potential divider arrangement. [A resistive potential divider will be terribly inefficient.] Two identical capacitors of large magnitude are put across the dc supply and the junction point of the capacitors is used as the neutral (ground) point of the bi-polar dc supply. Fig. 33.3(c) shows one such circuit where a single dc supply has been split in two halves. In such circuits the voltages across the two capacitors may not remain exactly balanced due to mismatch in the loading patterns or mismatch in leakage currents of the individual capacitors. Also, unless the capacitors are of very large magnitude, there may be significant ripple in the capacitor voltages, especially at low switching frequencies. The requirement of splitting a single dc source is eliminated if a full bridge circuit, as mentioned in the next section, is used. The second demerit of the push-pull circuit shown in Fig. 33.3(b) is the requirement of two different kinds of transistors, one n-p-n type and the other p-n-p type. The switching speeds of n-p-n and p-n-p transistors are widely different unless they are produced carefully as matched pairs. In power electronic applications, n-p-n transistors are preferred as they can operate at higher switching frequencies. Similarly n-channel MOSFETs and IGBTs are preferred over their p-channel counterparts. The difficulty in using two n-p-n transistors in the above discussed push-pull circuit is that they can no longer have a common base and a common emitter point and thus it wont be possible to have a single base drive signal for controlling both of them. The base signals for the individual transistors will then need to be separate and isolated from each other. The difficulty in providing isolated base signals for the two transistors is, often, more than compensated by the improved capability of the circuit that uses both n-p-n transistors or n-channel IGBTs. The circuit in Fig. 33.3(c) shows identical transistors (n-channel IGBTs) for both upper and lower switches. The gate drive signals of the two transistors (IGBTs) now need to be different and isolated as the two emitter points are at different potentials. The circuit in Fig. 33.3(c) is better known as a half bridge inverter.


Fig. 33.3(c): Topology of a 1-phase half bridge VSI

Edc

Q1

Q2

D1

D2

A

0.5Edc

0.5Edc

+ _

+ _

+ _ LOAD O

P

N

33.3 General Structure of Voltage Source Inverters Figs. 33.4 (a) and 33.4(b) show the typical power-circuit topologies of a single-phase and a three-phase voltage source inverter respectively. These topologies require only a single dc source and for medium output power applications the preferred devices are n-channel IGBTs. Edc is the input dc supply and a large dc link capacitor (Cdc) is put across the supply terminals. Capacitors and switches are connected to dc bus using short leads to minimize the stray inductance between the capacitor and the inverter switches. Needless to say that physical layout of positive and negative bus lines is also important to limit stray inductances. Q1, Q2, Q3 etc. are fast and controllable switches. D1, D2, D3 etc. are fast recovery diodes connected in anti-parallel with the switches. A, B and C are output terminals of the inverter that get connected to the ac load. A three-phase inverter has three load-phase terminals whereas a single-phase inverter has only one pair of load terminals. The current supplied by the dc bus to the inverter switches is referred as dc link current and has been shown as idc in Figs 33.4(a) and 33.4(b). The magnitude of dc link current often changes in step (and some times its direction also changes) as the inverter switches are turned on and off. The step change in instantaneous dc link current occurs even if the ac load at the inverter output is drawing steady power. However, average magnitude of the dc link current remains positive if net power-flow is from dc bus to ac load. The net power-flow direction reverses if the ac load connected to the inverter is regenerating. Under regeneration, the mean magnitude of dc link current is negative. [The dc link current may conceptually be decomposed into its dc and ac components. The individual roles of the dc voltage source and the dc link capacitor may be clearly seen with respect to the dc and ac components of the dc link current. For the dc component of current the capacitor acts like open circuit. As expected, under steady state, the capacitor does not supply any dc current. The dc part of bus current is supplied solely by the dc source. A practical dc voltage source may have some resistance as well as some inductance in series with its internal emf. For dc component of bus current, the source voltage appears in series with its internal resistance (effect of source inductance is not felt). But for ac component of current, the internal dc emf of source appears as short and its series impedance (resistance in series with inductance) appears in parallel with the dc-link


capacitor. Thus the ac component of current gets divided into these two parallel paths. However, the high frequency component of ac current mainly flows through the capacitor, as the capacitive impedance is lower at high frequencies. The step change in dc link current is associated with significant amount of high frequency components of current that essentially finds its path through the capacitor.] For an ideal input (dc) supply, with no series impedance, the dc link capacitor does not have any role. However a practical voltage supply may have considerable amount of output impedance. The supply line impedance, if not bypassed by a sufficiently large dc link capacitor, may cause considerable voltage spike at the dc bus during inverter operation. This may result in deterioration of output voltage quality, it may also cause malfunction of the inverter switches as the bus voltage appears across the non-conducting switches of the inverter. Also, in the absence of dc link capacitor, the series inductance of the supply line will prevent quick build up or fall of current through it and the circuit behaves differently from the ideal VSI where the dc voltage supply is supposed to allow rise and fall in current as per the demand of the inverter circuit. [It may not be possible to reduce supply line inductance below certain limit. Most dc supplies will inherently have rather significant series inductance, for example a conventional dc generator will have considerable armature inductance in series with the armature emf. Similarly, if the dc supply is derived after rectifying ac voltage, the ac supply line inductance will prevent quick change in rectifier output current. The effect of ac line inductance is reflected on the dc side as well, unless this inductance is effectively bypassed by the dc side capacitor. Even the connecting leads from the dc source to the inverter dc bus may contribute significantly to the supply line inductance in case the lead lengths are large and circuit lay out is poor. It may be mentioned here that an inductance, in series with the dc supply, may at times be welcome. The reason being that for some types of dc sources, like batteries, it is detrimental to carry high frequency ripple current. For such cases it is advantageous if the dc source has some series inductance. Due to series inductance of the source, the high frequency ripple will prefer to flow through the dc link capacitor and thus relieve the dc source.] The dc link capacitor should be put very close to the switches so that it provides a low impedance path to the high frequency component of the switch currents. The capacitor itself must be of good quality with very low equivalent series resistor (ESR) and equivalent series inductor (ESL). The length of leads that interconnect switches and diodes to the dc bus must also be minimum to avoid insertion of significant amount of stray inductances in the circuit. The overall layout of the power circuit has a significant effect over the performance of the inverter circuit.


LOAD

Edc Cdc _ +

Q1 D1

Q2 D2

Q3

Q4

D3

D4

Fig. 33.4(a): Topology of a 1-phase VSI

Edc Cdc_ +

Q1D1

Q2D2

Q3

Q4

D3

D4

Fig. 33.4(b): Topology of a 3-phase VSI

Q5

Q6

D5

D6

C B A A B

idc idc

[One of the thumb rules for good circuit layout is to put the conductor pairs carrying same magnitude but opposite direction of currents close by, the minimum distance between them being decided only by their voltage isolation requirement. Thus the positive and negative terminals of the dc bus should run close by. A twisted wire pair may be an example of two closely running wires.] The details of the inverter circuits shown in Figs. 33.4(a) and 33.4(b) are discussed in later lessons. However it may be mentioned here that these circuits are essentially extension of the half bridge circuit shown in Fig. 33.3(c). For example, the single-phase bridge circuit of Fig. 33.4(a) may be thought of as two half-bridge circuits sharing the same dc bus. Thus the single phase full-bridge (often, simply called as bridge) circuit has two legs of switches, each leg consisting of an upper switch and a lower switch. Junction point of the upper and lower switches is the output point of that particular leg. Voltage between output point of legs and the mid-potential of the dc bus is called as pole voltage referred to the mid potential of the dc bus. One may think of pole voltage referred to negative bus or referred to positive bus too but unless otherwise mentioned pole voltages are assumed to be referred to the mid-potential of the dc bus. The two pole voltages of the single-phase bridge inverter generally have same magnitude and frequency but their phases are 1800 apart. Thus the load connected between these two pole outputs (between points A and B) will have a voltage equal to twice the magnitude of the individual pole voltage. The pole voltages of the 3-phase inverter bridge, shown in Fig. 33.4(b), are phase apart by 1200 each. 33.4 Need For Isolated Gate-Control Signals For The Switches As already mentioned the switches in bridge configurations of inverters, as in Figs. 33.3(c), 33.4(a) and 33.4(b), need to be provided with isolated gate (or base) drive signals. The individual control signal for the switches needs to be provided across the gate (base) and source (or emitter) terminals of the particular switch. The gate control signals are low voltage signals referred to the source (emitter) terminal of the switch. For n-channel IGBT and MOSFET switches, when gate to source voltage is more than threshold voltage for turn-on, the switch turns on and when it is less than threshold voltage the switch turns off. The threshold voltage is generally of the order of +5 volts but for quicker switching the turn-on gate voltage magnitude is kept around +15 volts


where as turn-off gate voltage is zero or little negative (around 5 volts). It is to be remembered that the two switches of an inverter-leg are controlled in a complementary manner. When the upper switch of any leg is on, the corresponding lower switch remains off and vice-versa. When a switch is on its emitter and collector terminals are virtually shorted. Thus with upper switch on, the emitter of the upper switch is at positive dc bus potential. Similarly with lower switch on, the emitter of upper switch of that leg is virtually at the negative dc bus potential. Emitters of all the lower switches are solidly connected to the negative line of the dc bus. Since gate control signals are applied with respect to the emitter terminals of the switches, the gate voltages of all the upper switches must be floating with respect to the dc bus line potentials. This calls for isolation between the gate control signals of upper switches and between upper and lower switches. Only the emitters of lower switches of all the legs are at the same potential (since all of them are solidly connected to the negative dc bus) and hence the gate control signals of lower switches need not be isolated among themselves. As should be clear from the above discussion, the isolation provided between upper and lower switches must withstand a peak voltage stress equal to dc bus voltage. Gate-signal isolation for inverter switches is generally achieved by means of optical-isolator (opto-isolator) circuits. Fig.33.5 shows a typical opto-isolator circuit. The circuit makes use of a commercially available opto-coupler IC, shown within dotted lines in the figure. Input stage of the IC is a light emitting diode (LED) that emits light when forward biased. The light output of the LED falls on reverse biased junction of an optical diode. The LED and the photo-diode are suitably positioned inside the opto-coupler chip to ensure that the light emitted by the LED falls on the photo-diode junction. The gate control pulses for the switch are applied to the input LED through a current limiting resistor of appropriate magnitude. These gate pulses, generated by the gate logic circuit, are essentially in the digital form. A high level of the gate signal may be taken as on command and a low level (at ground level) may be taken as off command. Under this assumption, the cathode of the LED is connected to the ground point of the gate-logic card and anode is fed with the logic card output. The circuit on the output (photo-diode) side is connected to a floating dc power supply, as shown in Fig. 33.5. The control (logic card) supply ground is isolated from the floating-supply ground of the output. In the figure the two grounds have been shown by two different symbols. The schematic connection shown in the figure indicates that the photo-diode is reverse biased. A resistor in series with the diode indicates the magnitude of the reverse leakage current of the diode. When input signal to LED is high, LED conducts and the emitted light falls on the reverse biased p-n junction. Irradiation of light causes generation of significant number of electron-hole pairs in the depletion region of the reverse biased diode. As a result magnitude of reverse leakage current of the diode increases appreciably. The resistor connected in series with the photo-diode now has higher voltage drop due to the increased leakage current. A signal comparator circuit senses this condition and outputs a high level signal, which is amplified before being output. Thus an isolated and amplified gate signal is obtained and may directly be connected to the gate terminal of the switch (often a small series resistor, as suggested by the switch manufacturer, is put between the output signal and the gate terminal of the switch).


Signal comparator and power amplifier circuit

+VCC (floating)

Output

Floating Ground

Control Ground

Fig.33.5: A schematic opto-isolator circuit

Photo-diode

L E D

33.5 Classification of Voltage Source Inverters Voltage source inverters can be classified according to different criterions. They can be classified according to number of phases they output. Accordingly there are single-phase or three-phase inverters depending on whether they output single or three-phase voltages. It is also possible to have inverters with two or five or any other number of output phases. Inverters can also be classified according to their ability in controlling the magnitude of output parameters like, frequency, voltage, harmonic content etc. Some inverters can output only fixed magnitude (though variable frequency) voltages whereas some others are capable of both variable voltage, variable frequency (VVVF) output. Output of some voltage source inverters is corrupted by significant amount of many low order harmonics like 3rd, 5th, 7th, 11th, 13th order of the desired (fundamental) frequency voltage. Some other inverters may be free from low order harmonics but may still be corrupted by some high order harmonics. Inverters used for ac motor drive applications are expected to have less of low order harmonics in the output voltage waveform, even if it is at the cost of increased high order harmonics. Higher order harmonic voltage distortions are, in most ac motor loads, filtered away by the inductive nature of the load itself. Inverters may also be classified according to their topologies. Some inverter topologies are suitable for low and medium voltage ratings whereas some others are more suitable for higher voltage applications. The inverters shown in Figs. 33.3(c), 33.4(a) and 33.4(b) are two level inverters as the pole voltages may acquire either positive dc bus or negative dc bus potential. For higher voltage applications it may not be uncommon to have three level or five level inverters. Quiz Problems

1. A large capacitor, put across dc bus of a voltage source inverter, is intended to: (a) allow a low impedance path to the high frequency component of dc link current. (b) to minimize high frequency current ripple through the ideal dc source. (c) to maintain a constant dc link current. (d) to protect against switch failure.

2. A diode in anti-parallel with the controlled switch, like IGBT, is used in VSI to: (a) prevent reversal of dc link current.


(b) allow a non-unity power factor load at the output. (c) protect the circuit against accidental reversal of dc bus polarity. (d) none of the above.

3. The inverter switches work in fully-on or fully-off mode to achieve: (a) easier gate control circuit for the switching devices. (b) minimum distortion in the output voltage waveform. (c) reduced losses in the switches. (d) satisfactory operation for non-resistive load at the output.

4. Gate (base) signals to the VSI switches, using n-channel IGBTs, need to be isolated to allow:

(a) protection of switches against short at the inverter output terminals. (b) switches to be connected in bridge fashion. (c) lower losses in the gate drive circuit. (d) a dc link voltage higher than the switch voltage rating.

(Answers to the quiz problems: 1-a, 2-b, 3-c, 4-b)



(i) Explain the operating principle of a single-phase square wave inverter. (ii) Compare the performance of single-phase half-bridge and full-bridge inverters. (iii) Do harmonic analysis of load voltage and load current output by a single-phase

inverter. (iv) Decide on voltage and current ratings of inverter switches.

Voltage source inverters (VSI) have been introduced in Lesson-33. A single-phase square wave type voltage source inverter produces square shaped output voltage for a single-phase load. Such inverters have very simple control logic and the power switches need to operate at much lower frequencies compared to switches in some other types of inverters, discussed in later lessons. The first generation inverters, using thyristor switches, were almost invariably square wave inverters because thyristor switches could be switched on and off only a few hundred times in a second. In contrast, the present day switches like IGBTs are much faster and used at switching frequencies of several kilohertz. As pointed out in Lesson-26, single-phase inverters mostly use half bridge or full bridge topologies. Power circuits of these topologies are redrawn in Figs. 34.1(a) and 34.1(b) for further discussions. In this lesson, both the above topologies are analyzed under the assumption of ideal circuit conditions. Accordingly, it is assumed that the input dc voltage (Edc) is constant and the switches are lossless. In half bridge topology the input dc voltage is split in two equal parts through an ideal and loss-less capacitive potential divider. The half bridge topology consists of one leg (one pole) of switches whereas the full bridge topology has two such legs. Each leg of the inverter consists of two series connected electronic switches shown within dotted lines in the figures. Each of these switches consists of an IGBT type controlled switch across which an uncontrolled diode is put in anti-parallel manner. These switches are capable of conducting bi-directional current but they need to block only one polarity of voltage. The junction point of the switches in each leg of the inverter serves as one output point for the load. In half bridge topology the single-phase load is connected between the mid-point of the input dc supply and the junction point of the two switches (in Fig. 34.1(a) these points are marked as O and A respectively). For ease of understanding, the switches Sw1 and Sw2 may be assumed to

Fig. 34.1(a): A 1-phase half bridge VSI

Edc A

0.5Edc

0.5Edc

+ _

+ _

+ _ LOAD O

P

N

LOAD

Edc Cdc _ +

Fig. 34.1(b): A 1-phase full-bridge VSI

A B

idc P

N

C

C

Sw1 Sw1

Sw2

Sw3

Sw4 Sw2


SuvraTypewritten textAnalysis of 1-Phase,Square - Wave Voltage Source Inverter

be controlled mechanical switches that open and close in response to the switch control signal. In fact in lesson-33 (section 33.2) it has been shown that the actual electronic switches mimic the function of the mechanical switches. Now, if the switches Sw1 and Sw2 are turned on alternately with duty ratio of each switch kept equal to 0.5, the load voltage (VAO) will be square wave with a peak-to-peak magnitude equal to input dc voltage (Edc). Fig. 34.2(a) shows a typical load voltage waveform output by the half bridge inverter. VAO acquires a magnitude of +0.5 Edc when Sw1 is on and the magnitude reverses to -0.5 Edc when Sw2 is turned on. Fig. 24.2 also shows the fundamental frequency component of the square wave voltage, its peak-to-peak magnitude being equal to 4 dcE . The two switches of the inverter leg are turned on in a complementary manner. For a general load, the switches should neither be simultaneously on nor be simultaneously off. Simultaneous turn-on of both the switches will amount to short circuit across the dc bus and will cause the switch currents to rise rapidly. For an inductive load, containing an inductance in series, one of the switches must always conduct to maintain continuity of load current. In Lesson-33 (section 33.2) a case of inductive load has been considered and it has been shown that the load current may not change abruptly even though the switching frequency is very high. Such a situation, as explained in lesson-33, demands that the switches must have bi-directional current carrying capability.

34.1 Harmonic Analysis of The Load Voltage And Load Current

Waveforms The load voltage waveform shown in Fig. 34.2(a) can be mathematically described in terms of its Fouriers components as:

1,3,5,7,...,

2 sin( )dcAOn

EVn= = nwt (34.1)

,where n is the harmonic order and 2w is the frequency (f) of the square wave. f also

happens to be the switching frequency of the inverter switches. As can be seen from the expression of Eqn. 34.1, the square wave load voltage consists of all the odd harmonics and their magnitudes are inversely proportional to their harmonic order. Accordingly, the fundamental


frequency component has a peak magnitude of 2 dcE and the nth harmonic voltage (n being odd integer) has a peak magnitude of 2 dcEn . The magnitudes of very high order harmonic voltages become negligibly small. In most applications, only the fundamental component in load voltage is of practical use and the other higher order harmonics are undesirable distortions. Many of the practical loads are inductive with inherent low pass filter type characteristics. The current waveforms in such loads have less higher order harmonic distortion than the corresponding distortion in the square-wave voltage waveform. A simple time domain analysis of the load current for a series connected R-L load has been presented below to corroborate this fact. Later, for comparison, frequency domain analysis of the same load current has also been done. 34.1.1 Time Domain Analysis The time domain analysis of the steady state current waveform for a R-L load has been presented here. Under steady state the load current waveform in a particular output cycle will repeat in successive cycles and hence only one square wave period has been considered. Let t=0 be the instant when the positive half cycle of the square wave starts and let I0 be the load current at this instant. The negative half cycle of square wave starts at t=0.5T and extends up to T. The circuit equation valid during the positive half cycle of voltage can be written as below:

0.5 dcdiRi L Edt

+ = , for 0 < t < 0.5T ...(34.2) Similarly the equation for the negative half cycle can be written as

0.5 dcdiRi L Edt

+ = , for 0.5T < t < T .(34.3) , where T (=1/f) is the time period of the square wave. The instantaneous current i during the first half of square wave may be obtained by solving Eqn.(34.2) and putting the initial value of current as I0.

Accordingly, 00.5

( ) (1 )dct tE

i t e I eR

= + for 0 < t < 0.5T ..(34.4) , where = L/R is the time constant of the R-L load. The current at the end of the positive half cycle becomes the starting current for the negative half cycle.

Thus the next half cycle starts with an initial current = 00.5 2 2(1 )dc

T TE e I eR

+ . The circuit equation for the next half cycle may now be written as

0

( ) ( )2 20.5 0.5 2 2( ) (1 ) (1 )dc dc

T Tt tT TE Ei t e e I e e

R R

= + + for 0.5T

0( )20.5

( ) (1 )dc dc

Ttt tE E

i t e I e eR R

= + + + , for 0.5T < t < T .(34.5) Under steady state, the instantaneous magnitude of inductive load current at the end of a periodic cycle must equal the current at the start of the cycle. Thus putting t=T in Eqn. (34.5), one gets the expression for I0 as,

0 00.5 2(1 )dc dc

T TE EI e I e

R R

Te = + + +

or, 00.5 21 (1 )dc dc

T TE EI e e e

R R = +

1T

or, 020.5 0.51 1

2 21 1

dc dc dc

TE E E eI

TR R Re e

T

= = + + .(34.6)

Substituting the above expression for I0 in Eqn. (34.4) one gets,

20.5 1 2( )21

dc

tTE e ei t

TRe

+ = + , for 0 < t < 0.5T ....(34.7)

It may be noted from Eqn. (34.7) that the load current at the end of the positive half cycle of square wave (at t=0.5T) simply turns out to be I0. This is expected from the symmetry of the load voltage waveform. Load current expression for the negative half cycle of square wave can similarly be calculated by substituting for I0 in Eqn. (34.5). Accordingly,

( )2

0.5( )

21

dc dc

Tt

E E ei tTR R

e

= + +

, for 0.5T < t < T

or,

( )2

20.5 1 2( )21

dc

TtT

E e ei tTR

e

+ = +

, for 0.5T < t < T ............... (34.8)


The current expressions given by Eqns. (34.7) and (34.8) have been plotted in Figs. 34.2(b) to 34.2(e) for different time constants of the R-L load. The current waveforms have been

normalized against a base current of 0.5 dcER

. The square wave voltage waveform, normalized

against a base voltage of has also been plotted together with the current waveforms. It can be seen that the load current waveform repeats at fundamental frequency and the higher order harmonic distortions reduce as the load becomes more inductive. For L/R ratio of 2, the 3

0.5 dcE

rd order harmonic distortion in the load current together with its fundamental component has been shown in Fig. 34.2(e). In this case, it can be seen that the relative harmonic distortion in load current waveform is much lower than that of the voltage waveform shown in Fig. 34.2(a). The basis for calculating the magnitude of different harmonic components of load current waveform has been shown in the next subsection that deals with frequency domain analysis.

34.1.2 Frequency Domain Analysis The square shape load voltage may be taken as superposition of different harmonic voltages described by Eqn. 34.1. The load current may similarly be taken as superposition of harmonic currents produced by the different harmonic voltages. The load current may be expressed in terms of these harmonic currents. To illustrate this the series connected R-L load has once again been considered here. First the expressions for different harmonic components of load current are calculated in terms of load parameters: R and L/R (or ) and inverter parameters: dc link voltage (Edc) and time period of square wave (T).


For the fundamental harmonic frequency the load impedance (Z1) and load power factor angle (1) can be calculated to be

Z1 = 2 22

24( LR

T+ ) and 1 = 1 2tan LTR

..(34.9)

The load impedance and load power factor angle for the nth harmonic component (Zn and n respectively) will similarly be given by,

Zn = 2 2 22

24( )n LR

T+ and n = 1 2tan nLTR

..(34.10)

The fundamental and nth harmonic component of load current, (Iload)1 and (Iload)n respectively, can be found to be

(Iload)1 = 11

2sin( )dc

Ewt

Z and (Iload)n = 2

sin( )dc nn

Enwt

n Z (34.11) The algebraic summation of the individual harmonic components of current will result in the following expression for load current.

1,3,5,7,...,

2sin( )dcLoad n

n n

EI

n Z= = nwt .(34.12) From Eqns. 34.10 and 34.12 it may be seen that the contribution to load current from very higher order harmonics become negligible and hence the infinite series based expression for load current may be terminated beyond certain values of harmonic order n. For L/R ratio = 2T, the individual harmonic components of load current normalized against a base current of 0.5 dcE

Rhave been calculated below:

(Iload)1,normalized = 12

4 sin( tan 4 )1 16

wt

+

= 0.1sin( 1.491)wt


4 sin(3 tan 12 )3 1 144

wt

+

= 0.011sin(3 1.544)wt


4 sin(5 tan 20 )5 1 400

wt

+

= 0.004sin(5 1.555)wt


4 sin(7 tan 28 )7 1 784

wt

+

= 0.002sin(7 1.559)wt


4 sin(11 tan 44 )11 1 1936

wt

+

= 0.0008sin(11 1.564)wt


It may be concluded that for L/R = 2T, the contribution to load current from 13th and higher order harmonics are less than 1% of the fundamental component and hence they may be neglected without any significant loss of accuracy. Fig. 34.2(f) shows the load voltage and algebraic summation of the first five dominant harmonics (fundamental, 3rd, 5th, 7th and 11th) in the load current, the expressions for which have been given above. In Fig. 34.2(g) the load current waveforms of Fig. 34.2(e) and 34.2(f) have been superimposed for comparison. It may be seen that the load current waveform of Fig. 34.2(f) calculated using truncated series of the frequency domain analysis very nearly matches with the exact waveform of Fig. 34.2(e), calculated using time domain analysis.

34.2 Analysis Of The Single-Phase Full Bridge Inverter Single-phase half bridge inverter has already been described above. The single-phase full bridge circuit (Fig. 34.1(b)) can be thought of as two half bridge circuits sharing the same dc bus. The full bridge circuit will have two pole-voltages (VAO and VBO), which are similar to the pole voltage VAO of the half bridge circuit. Both VAO and VBO of the full bridge circuit are square waves but they will, in general, have some phase difference. Fig. 34.3 shows these pole voltages staggered in time by t seconds. It may be more convenient to talk in terms of the phase displacement angle defined as below: = (2 ) t

T Radians..(34.13)

, where t is the time by which the two pole voltages are staggered and T is the time period of the square wave pole voltages. The pole voltage VAO of the full bridge inverter may again be written as in Eqn. 34.1, used earlier for the half bridge inverter. Taking the phase shift angle into account, the pole-B voltage may be written as

1,3,5,7,...,

2 sin ( )dcBOn

EVn= = n wt (34.14)

Difference of VAO and VBO gives the line voltage VAB. In full bridge inverter the single phase load is connected between points A and B and the voltage of interest is the load voltage VAB. Taking difference of the voltage expressions given by Eqns. 34.1 and 34.14, one gets

[1,3,5,7,...,

2sin sin ( )dcAB

n

EV nwt

n= = ]n wt (34.15)


The fundamental component of VAB may be written as

[ ],1 2 4sin sin( ) cos( )sin2 2dc dcABE E

V wt wt wt = = ...(34.16)

The nth harmonic component in VAB may similarly be written as

[ ], 2 4sin sin ( ) cos ( )sin2 2dc dcAB nE E nV nwt n wt n wtn n

= = .(34.17) From Eqn. 34.16, the rms magnitude of the fundamental component of load voltage may be written as

,1( ) 0.9 sin 2AB rms dcV E = ....(34.18)

The rms magnitude of load voltage can be changed from zero to a peak magnitude of . The peak load voltage magnitude corresponds to = 180 degrees and the load voltage will be zero for = 0

0.9 dcE

0. For = 180 degrees, the load voltage waveform is once again square wave of time period T and instantaneous magnitude E. As the phase shift angle changes from zero to 1800 the width of voltage pulse in the load voltage waveform increases. Thus the fundamental voltage magnitude is controlled by pulse-width modulation. Also, from Eqns. 34.17 and 34.1 it may be seen that the line voltage distortion due to higher order harmonics for pulse width modulated waveform (except for = 1800) is less than the corresponding distortion in the square wave pole voltage. In fact, for some values of phase shift angle () many of the harmonic voltage magnitudes will drastically reduce or may even get eliminated from the load voltage. For example, for = 600 the load voltage will be free from 3rd and multiples of third harmonic.


34.3 Voltage And Current Ratings Of Inverter Switches Switches in each leg of the inverter operate in a complementary manner. When upper switch of a leg is on the lower switch will need to block the entire dc bus voltage and vice versa. Thus the switches must be rated to block the worst-case instantaneous magnitude of dc bus voltage. In practical inverters the switch voltage ratings are taken to be somewhat higher than the worst-case dc voltage to account for stray voltages produced across stray inductances, the turn-on transient voltage of a power diode etc. For a well laid out circuit a 50% margin over the dc-bus voltage may be the optimum switch voltage rating. Each switch of the inverter carries load current during half of the current cycle. Hence the switches must be rated to withstand the peak magnitude of instantaneous load current. The semiconductor switches have very small thermal time constant and they cannot withstand overheating for more than a few milli seconds. Thus even though the load current passes through the switches only in alternate half cycles, the thermal limit may be reached during half cycle of current itself. It may be pointed out that each inverter switch consists of a controlled switch in anti-parallel with a diode. The distribution of current between the diode and the controlled switch will depend on the load power factor at the operating frequency. In general both diode as well as the controlled switch should be rated to carry the peak load current. 34.4 Applications Of Square Wave Inverter The square wave voltage-source inverter discussed in this lesson finds application in many low cost ac motor drives, uninterruptible power supply units and in circuits utilizing electrical resonance between an inductor and a capacitor. Some examples of circuits utilizing resonance phenomenon are induction heating units and electronic ballasts for fluorescent lamps. Quiz Problems

1. A single-phase full bridge inverter with square wave pole voltages is connected to a dc input voltage of 600 volts. What maximum rms load voltage can be output by the inverter? How much will be the corresponding rms magnitude of 3rd harmonic voltage

(a) Approximately 270 volts of fundamental and 30 volts of 3rd harmonic voltage (b) Approx. 480 volts fundamental and 160 volts of 3rd harmonic voltage (c) Approx. 540 volts fundamental and 180 volts of 3rd harmonic voltage (d) Approx. 270 volts fundamental and 90 volts of 3rd harmonic voltage

2. How does the output power handling capacity of a single-phase half bridge inverter compare with that of a single-phase full bridge inverter when they are connected to same dc bus voltage and the peak current capability of the inverter switches is also same. Also compare their costs.

(a) The half bridge inverter can output double power but cost also doubles. (b) The half bridge inverter can output only half the power but cost is less. (c) The half bridge inverter can output only half the power but cost is nearly same (d) The output power capability is same but half bridge inverter costs less.

3. A single-phase full bridge inverter is connected to a purely resistive load. Each inverter switch consists of an IGBT in anti-parallel with a diode. For this load how does the diode conduction loss compare with the IGBT conduction loss?


(a) Diode and IGBT will have nearly same conduction loss (b) Diode conduction loss will be nearly half of the IGBT loss (c) Diode will have no conduction loss (d) IGBT will have no conduction loss

4. Using frequency domain analysis estimate the ratio of 5th and 7th harmonic currents in a purely inductive load that is connected to the output of a single phase half bridge inverter with square wave pole voltages.

(a) 5th harmonic current will be nearly double of the 7th harmonic current (b) 5th harmonic current will be 40% more than the 7th harmonic current (c) 5th harmonic current will be zero while 7th harmonic current will be present (d) Both 5th and 7th harmonic currents will be zero

(Answers to the quiz problems: 1-d, 2-b, 3-c, 4-a)



(i) Explain the operating principle of a three-phase square wave inverter. (ii) Understand the limitations and advantages of square-wave inverters. (iii) Do harmonic analysis of load voltage and load current output by the three-phase

sq. wave inverter. (iv) Decide on voltage and current ratings of inverter switches.

The basic configuration of a Voltage Source Inverter (VSI) has been described in Lesson 33. Single-phase half-bridge and full-bridge configurations of VSI with square wave pole voltages have been analyzed in Lesson 34. In this lesson a 3-phase bridge type VSI with square wave pole voltages has been considered. The output from this inverter is to be fed to a 3-phase balanced load. Fig. 35.1 shows the power circuit of the three-phase inverter. This circuit may be identified as three single-phase half-bridge inverter circuits put across the same dc bus. The individual pole voltages of the 3-phase bridge circuit are identical to the square pole voltages output by single-phase half bridge or full bridge circuits. The three pole voltages of the 3-phase square wave inverter are shifted in time by one third of the output time period. These pole voltages along with some other relevant waveforms have been plotted in Fig. 35.2. The horizontal axis of the waveforms in Fig. 35.2 has been represented in terms of t, where is the angular frequency (in radians per second) of the fundamental component of square pole voltage and t stands for time in second. In Fig. 35.2 the phase sequence of the pole voltages is taken as VAO, VBO and VCO. The numbering of the switches in Fig. 35.1 has some special significance vis--vis the output phase sequence.

Fig. 35.1: A 3-phase Voltage Source Inverter (VSI) feeding a balanced load

Edc Cdc _ +

A

idc P

n

B

Sw1

Sw2

Sw3

Sw4

C

Sw5

Sw6

A

B

C

3-phase balanced load

N


SuvraTypewritten text3-Phase Voltage Source Inverter With Square Wave Output

t

To appreciate the particular manner in which the switches have been numbered, the conduction-pattern of the switches marked in Fig. 35.2 may be noted. It may be seen that with the chosen numbering the switches turn on in the sequence:- Sw1, Sw2, Sw3, Sw4, Sw5, Sw6, Sw1, Sw2, .and so on. Identifying the switching cycle time as 360 degrees (2 radians), it can be seen that each switch conducts for 1800 and the turning on of the adjacent switch is staggered by 60 degrees. The upper and lower switches of each pole (leg) of the inverter conduct in a

0 /3 2/3 4/3 5/3 2 7/3 8/3 3 10/3 11/3 3

VAB

VAN

VBN

t

t

Edc

-Edc

1/3Edc 2/3Edc

2/3Edc

-2/3Edc

-2/3Edc

1/3Edc

-1/3Edc

-1/3Edc 0

0

0

aveforms output by a 3-phase square wave VSI Fig. 35.2: Some relevant voltage w

VAO

VBO

t

0.5Edc

- 0.5Edc t

- 0.5Edc

0.5Edc

0

0 Sw1 Sw1

Sw4 Sw4

Sw3Sw3

0.5Edc

t0

- 0.5Edc

Sw5

Sw2Sw2

Sw5

Sw6 Sw6

VCO Sw5

Sw6


complementary manner. To reverse the output phase sequence, the switching sequence may simply be reversed.

Considering the symmetry in the switch conduction pattern, it may be found that at any time three switches conduct. It could be two from the upper group of switches, which are connected to positive dc bus, and one from lower group or vice-versa (i.e., one from upper group and two from lower group). According to the conduction pattern indicated in Fig. 35.2 there are six combinations of conducting switches during an output cycle:- (Sw5, Sw6, Sw1), (Sw6, Sw1, Sw2), (Sw1, Sw2, Sw3), (Sw2, Sw3, Sw4), (Sw3, Sw4, Sw5), (Sw4, Sw5, Sw6). Each of these combinations of switches conducts for 600 in the sequence mentioned above to produce output phase sequence of A, B, C. As will be shown later the fundamental component of the three output line-voltages will be balanced. The load side phase voltage waveforms turn out to be somewhat different from the pole voltage waveforms and have been dealt with in the next section.

35.1 Determination Of Load Phase-Voltages

Fig. 35.1 shows a star connected balanced 3-phase load. The three load terminals are connected to the three output points (A, B, C) of the inverter. The neutral point N of the load is deliberately left open for some good reasons mentioned later. The load side phase voltages VAN, VBN and VCN can be determined from the conduction pattern of the inverter switches. With reference to Fig. 35.2, it may be seen that for 0t/3, switches Sw5, Sw6 and Sw1 conduct. Under the assumption of ideal switches Fig. 35.3(a) will represent the equivalent inverter and load circuit during the time interval 0t/3. In the equivalent circuit representation the non-conducting switches have been omitted and a cross (X) sign is used to represent a conducting switch. For a balanced 3-phase load the instantaneous phase voltage waveforms have been derived below for the following two cases (i) when the 3-phase load is purely resistive and (ii) when the load, in each phase, consists of a resistor in series with an inductor and a back e.m.f. In both the cases the equivalent circuit of Fig. 35.3(a) has been referred to derive the expression for load-phase voltage.

X Sw6

X Sw5

Edc + _

N

B

A

C

X Sw1

VAN = 1/3 Edc

VBN = -2/3 Edc VCN = 1/3 Edc

Fig. 35.3(a): Schematic load circuit during conduction of Sw5, Sw6 and Sw1

For case (i), when the load is a balance resistive load, it is very easy to see that the instantaneous phase voltages, for 0t/3, will be given by VAN = 1/3 Edc, VBN = -2/3 Edc, VCN = 1/3 Edc.

For case (ii), the following circuit relations hold good.


AAN A A

diV Ri L Edt

= + + , BN B dii L Edt= + +B BV R , C

CN C Cdi

i L Edt

= + +V R ...(35.1) AN BN dcV V E = , ....(35.2) AN CNV V=

where, , , are the instantaneous load-phase currents entering phases A, B and C respectively. , and are the instantaneous magnitudes of load phase-emfs. R and L are the per-phase load resistance and inductance that are connected in series with the corresponding phase-emf. Since the load is balanced (with its neutral point floating) the algebraic sum of the instantaneous phase currents and the phase emfs will be zero. Accordingly,

Ai Bi Ci

AE BE CE

Ai + + = 0 and + + = 0(35.3) Bi Ci AE BE CEFrom Eqns. 35.1 and 35.3, the following may be deduced:

( )( ) ( ) ( )A C BAN CN A C A C B B B

d i i diV V R i i L E E Ri L E V

dt dt++ = + + + + = + + = N .... (35.4)

Now from Eqns. 35.2 and 35.4 it can be easily found that VAN = 1/3 Edc, VBN = -2/3 Edc, VCN = 1/3 Edc.

Thus the instantaneous magnitudes of load phase voltages, in case of a more general (but balanced) R-L-E load are same as in case of a simple balanced resistive load.

Fig. 35.3(b) shows the equivalent circuit during /3t2/3, when the switches Sw6, Sw1 and Sw2 conduct. The instantaneous load phase voltages may be found to be VAN = 2/3 Edc, VBN = VCN = -1/3 Edc.

X

Edc + _

X

C

A

B

X

Sw1

Sw2

Sw6

N VAN = 2/3 Edc VBN = -1/3 Edc VCN = -1/3 Edc

Fig. 35.3(b): Schematic load circuit during conduction of Sw6, Sw1 and Sw2

The load phase voltage waveforms for other switching combinations may be found in a similar manner. Two of the phase voltages,V and V , along with line voltage V have been plotted over two output cycles in Fig. 35.2. It may be seen that voltage V is similar to V but lags it by one third of the output cycle period. Further, it can be verified that the load phase voltage V also has a waveform identical to the two other phase voltages but time displaced by one third of the output time period. V waveform leads V by 120 degrees in the time (t) frame. It should be obvious that the fundamental component of the phase voltage waveforms will constitute a balanced 3-phase voltage having a phase sequence A, B, C. It may also be recalled that by suitably changing the switching sequence the output phase sequence can be changed. The phase voltage waveforms of Fig. 35.2 show six steps per output cycle and are also referred as the

AN BN AB

BN AN

CN

CN AN


six-stepped waveform. A more detailed analysis of the load voltage waveforms is done in the following section. 35.2 Harmonic Analysis Of Load Voltage Waveforms

The individual pole voltage waveforms output by the 3-phase square wave inverter are identical to the output waveform of a single-phase half bridge inverter. As a consequence, the harmonic analysis of the voltage waveform presented in section 34.1 of Lesson 34 is valid here too. The expression for line voltage VAB is identical to the one given in Lesson 34 (Eqn.34.15), with of Eqn. 34.15 replaced by 2/3 radians. For convenience the expressions for pole-A voltage and line voltage are reproduced below in Eqns.35.5 and 35.6. The relevant waveforms are shown in Fig.35.2.

AOV ABV

1,3,5,7,...,

2 sin( )dcAOn

EVn= = nwt .....(35.5)

1,3,5,7,...,

2 2sin sin ( )3

dcAB

n

EV nwt n

nwt =

= ....(35.6) Using equations 35.5 and 35.6, the expressions for remaining pole and line voltages can be written simply by shifting the time (t) origin by the phase shift angle shown in Fig.35.2. Accordingly the expressions for pole voltage and line voltage are written below in Eqns. 35.7 and 35.8 respectively.

BOV BCV

1,3,5,7,...,

2 2sin ( )3

dcBO

n

EVn

n wt = = ...(35.7)

1,3,5,7,...,

2 2sin ( ) sin ( )3 3

dcBC

n

EV n wt nn

4wt = = ....(35.8)

It may be verified that difference of and leads to the expression for . The expression for a particular harmonic component in the voltage waveforms is determined simply by substituting n in above equations by the harmonic order. Accordingly the fundamental magnitude of line voltages , and can be written as:

AOV BOV ABV

ABV BCV CAV

,12 2 32sin sin( ) sin( )

3 6dc dc

ABE E

V wt wt wt = = +

,12 3

sin( )2

dcBC

EV wt = , ,1

2 3 7sin( )6

dcCA

EtV w =

The three fundamental line voltages are balanced (have identical magnitudes and are phase apart by 1200). For most practical loads only the fundamental component of the inverter output voltage is of interest. However the inverter output also contains significant amount of higher order harmonic voltages that cause undesirable distortion of the output waveform. It may, though, be noted that there are no even harmonics and the line voltages are free from 3rd and multiples of 3rd order harmonics. Also, as the harmonic order (n) increases their magnitudes decrease inversely with the harmonic order. When expressed as a fraction of fundamental voltage magnitude, the line voltage distortions are mainly due to 20% of 5th harmonic, nearly 14% of 7th, nearly 9% of


11th and nearly 8% of 13th harmonic. Since most loads are inductive in nature with a low pass filter type characteristics the effect of very high order harmonics may be neglected.

It may be noted that though the pole voltages have 3rd and multiples of 3rd order harmonic distortions, the line voltages are free from these distortions. Hence the load neutral point, rather than being connected to the mid-potential point of the input dc supply (as in a single-phase half bridge inverter), is deliberately left floating. The floating neutral point does not allow a closed path for the 3rd and multiples of 3rd harmonic currents to flow (3rd or multiples of 3rd harmonic current, if present in the load phases, have identical instantaneous magnitudes in all the three phases and their algebraic sum needs to flow in or out of the load neutral point). By keeping the load neutral point floating, not only the need for bringing out the mid-potential point of dc supply is done away with, the triplen harmonic distortions of the load current is totally eliminated. Since there are no triplen harmonic currents in the load, the load-phase voltages are also free from triplen harmonic distortions. In fact the six-stepped load-phase voltages shown in Fig. 35.2 are found to be free from triplen harmonics. It turns out that by removing all triplen harmonics from the square-shaped pole voltage waveform one can arrive at the corresponding load-phase (six-stepped) voltage waveform. Accordingly the load-phase voltages may be expressed in terms of its harmonic contents as shown below.

1,5,7,11,13...,

2 sin( )dcANn

EVn= = nwt .....(35.9)

1,5,7,11,13...,

2 2sin ( )3

dcBN

n

EVn

n wt = = ...(35.10)

1,5,7,11,13...,

2 2sin ( )3

dcCN

n

EVn

n wt = = + ...(35.11)

For a balanced three-phase load, the instantaneous magnitude of any phase current can be determined by superposition of different harmonic currents of the phase. For a simple three-phase R-L load, the phase-A current ( ) expression in terms of resistance (R) and inductance (L) of the load may be written as:

Ai

1

2 2 2 21,5,7,11,13...,

2 sin[ tan ( )]dcAn

E n Li nRn R n L

=

= + wt .....(35.12)

Phase-B and phase-C current expressions can be obtained simply by replacing t in Eqn. 35.12 by 2( )

3t and 2(

3t ) + respectively. A close look at Eqn. 35.12 will reveal that for a

purely inductive 3-phase load the 5th, 7th, 11th and 13th harmonic distortion in the load current (as a percentage of fundamental component of current) will respectively be 4%, 2.04%, 0.83% and 0.59%. These distortions are much less than the corresponding distortions in the load voltage waveforms. As a result the load current for highly inductive R-L load will have close to sinusoidal shape.


35.3 Voltage And Current Ratings Of Inverter Switches As in a single-phase square-wave inverter, switches in each leg of the three-phase inverter operate in a complementary manner. When upper switch of a leg is on the lower switch will need to block the entire dc bus voltage and vice versa. Thus the switches must be rated to block the worst-case instantaneous magnitude of dc bus voltage. An extra safety margin over the worst-case dc voltage, as discussed in Lesson-34, section 34.3, is recommended. Each inverter-switch carries load-phase current during half of the current cycle. Hence the switches must be rated to withstand the peak expected magnitude of instantaneous load-phase current. For a non-unity power factor load, the diode connected in anti-parallel with the switch will conduct part of the switch current. The distribution of current between the diode and the controlled switch will depend on the load power factor at the operating frequency. In general both diode as well as the controlled switch should be rated to carry the peak load current. These diodes also need to block a peak reverse voltage equal to worst case voltage across the switches. 35.4 Use And Limitations Of 3-Phase Square Wave Inverter

The three-phase square wave inverter as described above can be used to generate balanced three-phase ac voltages of desired (fundamental) frequency. However harmonic voltages of 5th, 7th and other non-triplen odd multiples of fundamental frequency distort the output voltage. In many cases such distortions in output voltages may not be tolerable and it may also not be practical to use filter circuits to filter out the harmonic voltages in a satisfactory manner. In such situations the inverter discussed in this lesson will not be a suitable choice. Fortunately there are some other kinds of inverters, namely pulse width modulated (PWM) inverters, discussed in the next lesson, which can provide higher quality of output voltage.

The square wave inverter discussed in this lesson may still be used for many loads, notably ac motor type loads. The motor loads are inductive in nature with the inherent quality to suppress the harmonic currents in the motor. The example of a purely inductive load discussed in the previous section illustrates the effectiveness of inductive loads in blocking higher order harmonic currents. In spite of the inherent low-pass filtering property of the motor load, the load current may still contain some harmonics. These harmonic currents cause extra iron and copper losses in the motor. They also produce unwanted torque pulsations. Fortunately the torque pulsations due to harmonic currents are of high frequencies and their effect gets subdued due to the large mechanical inertia of the drive system. The motor speed hardly changes in response to these torque pulsations. However in some cases torque pulsations of particular frequencies may cause unwanted resonance in the mechanical system of the drive. A special notch filter may then be required to remove these frequencies from the inverter output voltage.

The input dc voltage to the inverter is often derived from an ac source after rectification and filtering. A simple diode bridge rectifier followed by a filter capacitor is often the most cost-effective method to get dc voltage from ac supply. In some applications, like in un-interrupted power supplies, the dc input may be coming from a bank of batteries. In both these examples, the input dc magnitude is fairly constant. With fixed input dc voltage the square-wave inverter can output only fixed magnitude of load voltage. This does not suit the requirement in many cases where the load requires a variable voltage variable frequency (VVVF) supply. In order that ac output voltage magnitude is controllable, the inverter input voltage will need to be varied using an additional dc-to-dc converter. However a better solution will be to use a PWM inverter (to be


discussed in the next lesson), which can provide a VVVF output with enhanced output voltage quality.

In spite of the limitations, discussed above, the square wave inverter may be a preferred choice on account of its simplicity and low cost. The switch control circuit is very simple and the switching frequency is significantly lower than in PWM inverters. This results in low switching losses. The switch cost may also be lower as one may do away with slower switching devices and slightly lower rated switches. Another advantage over PWM inverter is its ability to output higher magnitude of fundamental voltage than the maximum that can be output from a PWM inverter (under the given dc supply condition). Listed below are two applications where a 3-phase square wave inverter could be used.

(i) A low cost solid-state frequency changer circuit: This circuit converts the 3-phase ac (input) voltages of one frequency to 3-phase ac (output) voltages of the desired frequency. The input ac is first converted into dc and then converted back to ac of new frequency. The square wave inverter discussed in this lesson may be used for dc to ac conversion. Such a circuit may, for example, convert 3-phase ac voltages of 50 Hz to 3-phase ac voltages of 60 Hz. The input to this circuit could as well have come from a single-phase supply, in which case the single-phase ac is first converted into dc and then converted back to 3-phase ac of the desired frequency.

(ii) An uninterrupted power supply circuit: Uninterrupted power supply circuits are used to provide uninterrupted power to some critical load. Here a critical load requiring 3-phase ac supply of fixed magnitude and frequency has been considered. In case ac mains supply fails, the 3-phase load may be electronically switched, within few milliseconds, to the output of the 3-phase square wave inverter. Input dc supply of the inverter often comes from a battery bank.

Problems

(1) A 3-phase square wave inverter feeds a balanced 3-phase resistive-inductive load. The

load phase current will contain, apart from the fundamental frequency current, the following harmonic currents:

(a) All odd multiples of fundamental (b) All odd and even multiples of fundamental (c) All even multiples of fundamental except 6th and multiples of 6th (d) All odd multiples of fundamental except 3rd and multiples of 3rd

(2) The six-stepped load phase voltage of a 3-phase square wave inverter, with a dc link

voltage of 100 volts, will have the following rms magnitudes of 1st, 3rd and 5th harmonic voltages:

(a) 10V, 30V and 50V respectively (b) 100V, 33.3V and 20V respectively (c) 90V, 30V and 0 respectively (d) 45V, 0 and 9V respectively

(3) A 3-phase square wave inverter, fed from a fixed dc input, is capable of producing the

following type of ac (fundamental component) voltages:


(a) Variable voltage variable frequency type (b) Fixed voltage variable frequency type (c) Variable voltage fixed frequency type (d) None of the above

(4) A 3-phase square wave inverter feeds a balanced 3-phase inductance type load. The

worst-case load phase current (peak magnitude) is expected to be 100 amps and the worst-case dc input voltage is expected to be 600 volts. The diodes of the inverter will be subjected to the following peak voltage and current stresses:

(a) 600V, 100A (b) 600V, 70.7A (c) 424V, 70.7A (d) 424V, 100A

(Answers: 1-d, 2-d, 3-b, 4-a)



(i) Explain the philosophy behind PWM inverters. (ii) Understand the advantages and disadvantages of PWM inverters. (iii) Compare the quality of output voltage produced by different PWM inverters (iv) Decide on voltage and current ratings of inverter switches.

Pulse width modulated (PWM) inverters are among the most used power-electronic circuits in practical applications. These inverters are capable of producing ac voltages of variable magnitude as well as variable frequency. The quality of output voltage can also be greatly enhanced, when compared with those of square wave inverters discussed in Lesson-35. The PWM inverters are very commonly used in adjustable speed ac motor drive loads where one needs to feed the motor with variable voltage, variable frequency supply. For wide variation in drive speed, the frequency of the applied ac voltage needs to be varied over a wide range. The applied voltage also needs to vary almost linearly with the frequency. PWM inverters can be of single phase as well as three phase types. Their principle of operation remains similar and hence in this lesson the emphasis has been put on the more general, 3-phase type PWM inverter. There are several different PWM techniques, differing in their methods of implementation. However in all these techniques the aim is to generate an output voltage, which after some filtering, would result in a good quality sinusoidal voltage waveform of desired fundamental frequency and magnitude. As will be discussed later in this chapter, for the inverter topology considered here, it may not be possible to reduce the overall voltage distortion due to harmonics but by proper switching control the magnitudes of lower order harmonic voltages can be reduced, often at the cost of increasing the magnitudes of higher order harmonic voltages. Such a situation is acceptable in most cases as the harmonic voltages of higher frequencies can be satisfactorily filtered using lower sizes of filter chokes and capacitors. Many of the loads, like motor loads have an inherent quality to suppress high frequency harmonic currents and hence an external filter may not be necessary. To judge the quality of voltage produced by a PWM inverter, a detailed harmonic analysis of the voltage waveform needs to be done. In the following discussions some of the results of harmonic analysis done in the previous lessons have been borrowed. In Lesson-35, while discussing the 3-phase square wave inverter it was shown that the magnitudes of fundamental components of the inverter pole voltage (voltage between the output of an inverter leg and the mid potential point of the input dc supply) and the load phase voltage are identical provided the load is a balanced 3-phase load. In fact, after removing 3rd and multiples of 3rd harmonics from the pole voltage waveform one obtains the corresponding load phase voltage waveform. The pole voltage waveforms of 3-phase inverter are simpler to visualize and analyze and hence in this lesson the harmonic analysis of load phase and line voltage waveforms is done via the harmonic analysis of the pole voltages. It is implicit that the load phase and line voltages will not be affected by the 3rd and multiples of 3rd harmonic components that may be present in the pole voltage waveforms.


SuvraTypewritten text3-Phase Pulse Width Modulated (PWM) Inverter

36.1 Nature Of Pole Voltage Waveforms Output By PWM Inverters Unlike in square wave inverters the switches of PWM inverters are turned on and off at significantly higher frequencies than the fundamental frequency of the output voltage waveform. The typical pole voltage waveform of a PWM inverter is shown in Fig. 36.1 over one cycle of output voltage. In a three-phase inverter the other two pole voltages have identical shapes but they are displaced in time by one third of an output cycle. Compared to the square pole voltage waveform seen in Lesson-35, the pole voltage waveform of the PWM inverter changes polarity several times during each half cycle. The time instances at which the voltage polarities reverse have been referred here as notch angles. It may be noted that the instantaneous magnitude of pole voltage waveform remains fixed at half the input dc voltage (Edc). When upper switch (SU), connected to the positive dc bus is on, the pole voltage is + 0.5 Edc and when the lower switch (SL), connected to the negative dc bus, is on the instantaneous pole voltage is - 0.5 Edc. The switching transition time has been neglected in accordance with the assumption of ideal switches. It is to be remembered that in voltage source inverters, meant to feed an inductive type load, the upper and lower switches of the inverter pole conduct in a complementary manner. That is, when upper switch is on the lower is off and vice-versa. Both upper and lower switches

2 0 1

2 3

4

-0.5Edc

0.5Edc

Fig.36.1: A typical pole-voltage waveform of a PWM inverter

Pole Voltage

t

/2 -4

-3 -2

-1 +1

+2 +3

+4 3/2

2-4 2-3

2-2 2-1

0

SU

SL

SU SU SU SU SU SU SU SU

SL SL SL SL SL SL SL SL

should not remain on simultaneously as this will cause short circuit across the dc bus. On the other hand one of these two switches in each pole (leg) must always conduct to provide continuity of current through inductive loads. A sudden disruption in inductive load current will cause a large voltage spike that may damage the inverter circuit and the load. 36.2 Harmonic Analysis Of Pole Voltage Waveform The pole voltage waveform shown in Fig. 36.1 has half wave odd symmetry and quarter-wave mirror symmetry. The half wave odd symmetry of any repetitive waveform f(t), repeating after every 2/ duration, is defined by f(t) = - f(+t). Such a symmetry in the waveform amounts


to absence of dc and even harmonic components from the waveform. All inverter output voltages maintain half wave odd symmetry to eliminate the unwanted dc voltage and the even harmonics. The half wave odd symmetry followed by quarter wave mirror symmetry, defined by f(t) = f(-t), results in presence of only sine components in the Fourier series representation of the waveform. It may be verified that quarter wave symmetry may not hold good once the time origin is shifted arbitrarily. However the half-wave odd symmetry is maintained in spite of shifting of time origin. This is quite expected, as by just shifting the time origin new (even) harmonic frequencies will not creep up in the voltage waveform, whereas by shifting time origin the sine wave may become cosine or may have some other phase-shift. The quarter wave symmetry talked above is not necessary for improvement of the output waveform quality; it merely simplifies the Fourier analysis of the pole voltage waveform. It may also be noted that the quarter wave symmetry is not achieved at the cost of compromising the inverters output capability (in terms of magnitude and quality of achievable output voltage). With the assumed quarter wave mirror symmetry and half wave odd symmetry the waveform shown in Fig. 36.1 may be decomposed in terms of its Fourier components as below:-

1,3,5,....sinAO n

nV b n t

= = ..(36.1)

where is the instantaneous magnitude of the pole voltage shown in Fig. 36.1 and is the peak magnitude of its n

AOV

nbth harmonic component. Because of the half wave and quarter

wave symmetry of the waveform, mentioned before, the pole voltage has only odd harmonics and has only sinusoidal components in the Fourier expansion. Thus the pole voltage will have fundamental, third, fifth, seventh, ninth, eleventh and other odd harmonics. The peak magnitude of nth harmonic voltage is given as:

1 2 32 (1 2 cos 2 cos 2 cos 2 cos )nEb n n nn 4

n = + + ..(36.2) , where 1 , 2 3 and 4 are the four notch angles in the quarter cycle ( 0 2t ) of

the waveform.

Now, as described in the beginning of this lesson, the third and multiples of third harmonics do not show up in the load phase and line voltage waveforms of a balanced 3-phase load. Most of the three phase loads of interest are of balanced type and for such loads one need not worry about triplen (3rd and multiples of 3rd) harmonic distortion of the pole voltages. The peak magnitudes of fundamental ( ) and three other lowest order harmonic voltages that matter most to the load can be written as:

1b

1 1 2 32 (1 2 cos 2 cos 2 cos 2 cos )Eb 4 = + + ...(36.3)

5 1 2 32 (1 2 cos 5 2 cos 5 2 cos 5 2 cos 5 )5Eb 4 = + + ...(36.4)

7 1 2 32 (1 2 cos 7 2 cos 7 2 cos 7 2 cos 7 )5Eb 4 = + + ..(36.5)

11 1 2 3 42 (1 2 cos11 2 cos11 2 cos11 2 cos11 )11Eb = + + ...(36.6)

It can be seen that the 3rd and 9th harmonics have been not considered, as they will not appear in the load side phase and line voltages. Most of the industrial loads are inductive in nature with an


inherent quality to attenuate currents due to higher order harmonic voltages. Thus after fundamental voltage, the other significant voltages for the load are 5th, 7th and 11th etc. Generally, only the fundamental frequency component in the output voltage is of interest and all other harmonic voltages are undesirable. As such one would like to eliminate as many low order harmonics as possible. Accordingly the fundamental voltage magnitude ( ) may be set at the desired value and the magnitudes of fifth ( ), seventh ( ) and eleventh ( ) harmonics may be set to zero. These voltage magnitudes when substituted in the expressions given by Eqns. 36.3 to 36.6 will lead to the solutions of the notch angles. One may like to eliminate many more unwanted harmonic frequencies from the load voltage waveform but this will require introduction of more notch angles per quarter cycle of the pole voltage. In fact if there are k notch angles per quarter cycle, k number of equations may be written each of which determines the magnitude of a particular harmonic voltage. Now, each time a notch angle is encountered in the pole voltage waveform, the top and bottom switches of that particular pole undergo a switching transition (on to off or vice versa). The switching frequency (f

1b

5b 7b 11b

sw) of the inverter switches can be equated to

fsw = 2 k f1 ...........(36.7) , where one turn-on and one turn-off has been taken as one switching cycle, k is the number of notches per quarter cycle and f1 is the frequency of fundamental component in the output voltage. Thus it can be seen that a better quality output waveform (in terms of elimination of more numbers of unwanted harmonic voltages) comes at the cost of increasing the switching frequency of the inverter. The switching frequency is directly proportional to the switching losses in the inverter switches. Also, the switch must be capable of being switched on and off at the required frequency. The IGBT switches used in medium power inverters are generally switched at a frequency of 20 kHz or more. With a switching frequency of 20 kHz and the output (fundamental) frequency of 50 Hz there will be up to 200 notches per quarter cycle of the output waveform. The load voltage can thus be made virtually free of low order harmonics and the load current (for an inductive load) can be expected to have a good quality sinusoidal waveform. The switching frequency of 20 kHz is important in another sense too. The range of audible noise for human beings extends from few Hertz to 20 kHz. Thus if the switching frequency is 20 kHz or beyond, the switching frequency related audible noise will not be present when the inverter operates. The inverter operation can then be very quite. If the inverter operates at low frequency, the connecting wires to the switches etc. also carry low frequency current producing low frequency vibrations (due to interaction of current with the stray magnetic field produced by other conductors etc.) and result in audible noise. Similarly low frequency current through inductors and transformers also produce audible noise. The humming or whistling type noise due to low switching frequency may at times be too annoying and unacceptable. 36.3 T

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