Digital Communication

IT 3012

For

Second Semester

Sample Question

1. What is multiplexing? Explain its application. (10 marks) 2. What are the distinct characteristics of FDM use FDM application.(20 marks) 3. Explain TDM (Time division Multiplexing) system and show TDM of analog and digital source is organized? (20 marks) 4. Describe Basic ISDN Interface. (20marks) 5. Describe primary ISDN Interface. (10 marks) 6. Explain the STS-1 overhead bit for line overhead and path overhead .(10 marks) 7. Draw the frame-format for SONET/SDH and show in the table from overhead octet

of STS-1.(10 marks) 8. Write short notes on circuit-switching network. (10 marks) 9. Describe and explain for general architectural components for public

telecommunication network. (10 marks) 10. What are the signaling functions and describe. (20 marks) 11. How many types of routing techniques in circuit-switched network? Explain them. (20marks) 12. Explain the elements of a circuit-switched node. (20marks) 13. State and explain cross-bar switch limitation. (10 marks) 14. Show the advantages of packet switching over circuit switching. (10marks) 15. Draw timing diagram for circuit-switch |& packet switching and describing and

describe three types of delay. (10 marks) 16. Using diagram, show the effect of packet size on transmission time.(10 marks) 17. Compare the different communication switching techniques by using tables. (20 marks) 18. Draw the diagrams of External and Internal virtual circuit and diagram.(10 marks) 19. Explain fixed Routing and draw the table for central routing directory for a given

packet-switched network. (20marks)

2

5

3

6

1

1

2

3 8

8

1

3 2 3 1

7

4 2

1

5

2

1

3

4 5

6

FIGURE Example packed-switched network

20. Draw the diagram of sequence of events: X.25 protocol.(20 marks) 21. Explain Frame Relay Protocol Architecture. (20marks) 22. Why the congestion ad voidance procedures are used? Explain two bits in the

address Field are used for congestion ad voidance procedure.(10 marks) 23. Draw and briefly explain the comparison of X.25 and frame relay protocol stacks.

(10 marks)

IT - 3012

DIGITAL COMMUNICATION

SAMPLE QUESTIONS & ANSWERS

CHAPTER (7) MULTIPLEXING

1. What is multiplexing? Explain its application.(8 marks) Solution: Two communicating stations will not utilize the full capacity of a data link. For efficiency, it should be possible to share that capacity, sharing is called multiplexing. Fig shows the multiplexing function in its simplest form. There are n inputs to the multiplexer. The multiplexer is connected by a single data link to a demultiplexer. The link is able to carries n separate channels of data. The multiplexer combines (multiplexes) data from the n input lines and transmits over a higher-capacity data link. The demultiplexer accepts the multiplexed data stream, separates (demultiplexes) the data according to channel, and delivers them to the appropriate output line.

FIGURE. Multiplexing

The widespread use of multiplexing in data communications can be explained by the following: 1. The higher the data rate, the more cost-effective the transmission facility. For a given application

and over a given distance, the cost per kbps declines with an increase in the data rate of the transmission facility.

2. Most individual data-communicating devices require relatively modest data-rate support. For example, for most terminal and personal computer applications, a data rate of between 9600 bps and 64 kbps is generally adequate.

2. What are the distinct characteristics of FDM use FDM application.(16 marks) Solution: FDM are possible when the useful bandwidth of the transmission medium exceeds the required bandwidth of signals to be transmitted. A number of signals can be carried simultaneously if each signal is modulated onto a different carrier frequency. Each modulated signal requires a certain bandwidth centered around its carrier frequency, referred to as a channel. To prevent interface, the channels are separated by guard bands, which are unused portions of the spectrum. The composite signal transmitted across the medium is analog. The input signals may be either digital or analog .Digital input, the input signal must be passed through modems to be converted to analog. Each input analog signal must then be modulated to the appropriate frequency band. A number of analog or digital signals [mi (t), i = 1, N ] are to be multiplexed onto the same transmission medium . Each signal mi (t) i, modulated onto a carrier frequency. The resulting modulated analog signals are then summed to produce a composite signal mc (t). The composite signal has a total bandwidth B. At the receiving end, the composite signal is passed through N band pass filters, each filter centered on frequency and having a bandwidth. The signal is again split into its component parts. Each component is then demodulated to recover the original signal.

MUX 1 link, n channel DE

MUX n outputs n inputs

3. Explain TDM (Time division Multiplexing) system and show TDM of analog and digital source is organized?

Solution Time Division Multiplexing A number of signals [mi(t) , i=1,n] are to be multiplexed onto the same transmission medium. The signals carry digital data and are generally digital signals. The incoming data from each source are briefly buffered. Each buffer is typically one bit or one character in length. The buffers are scanned sequentially to form a composite digital data stream mc (t). The digital signal mc (t) may be transmitted directly or passed through a modem so that an analog signal is transmitted. The data are organized into frames. Each frame contains a cycle of time slots. The sequence of slots dedicated to one source, from frame, is called a channel. The slot length equals the transmitter buffer length, typically a bit or a character. The character interleaving technique is used with asynchronous sources. The bit-interleaving technique is used with synchronous sources and may also be used with asynchronous sources. At the receiver, the interleaved data are demultiplexed and routed to the appropriate destination buffer. The output source which will receive the input data at the same rate.

Figure: Frequency division multiplexing

(a) Transmitter

f1f2f3

f4f5f6

chan1

chan2

chan3

chan4

chan5

chan6

Time

frequency

Sub carrier fsc 1

Sub carrier fsc 2

Sub carrier fsc N

m1 (t)

m2 (t)

mN (t)

Transmitter fc

S(t) = FDM

Mc (t)

SscN (t)

Ssc1 (t)

Ssc2 (t)

(b) Spectrum of composite signal (positive f)

( c) Receiver

Figure: Frequency Division Multiplexing

Modem

Buffer Scan operation

S (t)

m1 (t)

m2 (t)

mn (t)

me (t)

(a) Transmitter

frequencyTime

Mc f (t) 1

0 f N

Bsc 1 Bsc 2 Bsc N

f sc Nf sc 2f sc 1

Bandpass filer ,fsc 1

Bandpass filer ,fsc 2

Bandpass filer ,fsc N

S (t) Receiver

Demodulator fsc 1

Demodulator fsc 2

Demodulator fsc N

m N (t)

m 2 (t)

m 1 (t)

Figure: TDM of analog and digital sources

m2(t)

m1(t)

mn(t)

mc(t)

Buffer Scan Operation

(c) Receiver

Time slot: may be empty or occupied

(b) TDM frames

frame frame

1 11 2 N 1 2 N

FIGURE Synchronous time-division multiplexing

Pulse stuffing

Pulse stuffing

2 bit buffer

2 bit buffer

8 kbps

8 kbps source 11

7.2 kbps , digital

source 4

7.2 kbps , digital

Scan 128 kbps

TDM signal

2 bit buffer 4 bit A/D 64 kbps

TDM PCM signal

f

source 1

source 2

source 3

2kHz, analog

4kHz, analog

2kHz, analog

f - 4kHz

TDM PAM signal

16 kHz

4. Describe Basic ISDN Interface.(16marks) Solution:

Basic ISDN Interface

The basic access structure consist of two 64 kbps B channels and one 16 kbps D cannel, 144 kbps, are multiplexed over a 192 kbps interface at the S or T reference point. The remaining capacity use for various framing and synchronization purposes. The B channel is the basic user channel. It can be use to carry digital data. The D channel can be use for a data transmission connection at a lower data rate. It is also use to carry control information needed to setup and terminate the B channel connections. Each frame of 48 bits includes 16 bits from each of the two B channel, and 4 bits from the D channel: The remaining bits have the following interpretation. In the TE to NT direction. Each frame begins with a framing bit (F) that is always transmitted as a positive pulse. This is followed by a dc balancing bit (L) that is set to a negative pulse to balance the voltage. The F-L pattern thus acts to synchronize the receiver on the beginning of the frame. The next eight bits (B1) are form the first B channel this is followed by another dc balancing bit (L). Next comes a bit from the D channel, followed by its balancing bit. This is followed by the auxiliary framing bit (FA), which is set to zero unless it is to be use in a multi-frame structure. There follows another balancing bit (N), eight bits (B2) from the second B channel, and another balancing bit (L); this is follow by bits from the D channel, first B channel, D channel again, second B channel, and the D channel, again. In the NT to TE direction is similar to the frame structure for transmission in the TE-to-NT direction. The following new bits replace some of the dc balancing bits. The activation bit (A) is use to activate or deactivate a TE. The N bit is normally set to binary one. The N and M bits may be use for multi-framing. The s bit is reserved. For other future standardization requirements. There are three types of traffic:

B-channel traffic: No additional functionality is needed to control access to the two B channel is dedicated to a particular TE at any given time. D- channel traffic: The D channel is available for use by all the subscriber devices for both control signaling and packet transmission, so the potential for contention exits, There are two sub cases:

Incoming traffic: The LAPD addressing scheme is sufficient to sort out the proper destination for each data unit.

Outgoing traffic: Access must be regulated so that only one device at a time transmits. This is the purpose of the contention-resolution algorithm.

+

Fig: 7.10 from Page 18

5. Describe primary ISDN Interface.(8marks) Solution:

Primary ISDN Interface The primary interface multiplexes multiple channels across a single transmission medium. In the case of the primary interface, only a point-to-point configuration is allowed. Typically, the interface supports a digital PBX, and providing a synchronous TDM facility for access to ISDN. Two data rate are defined for the primary interface: 1.544 Mbps and 2.048 Mbps.

The ISDN interface at 1.544 Mbps is based on the North American DS-1 transmission structure, which is use on the T1 transmission service. The bit stream is structured into repetitive 193 bit frames. Each frame consists of 24, 8 bit time slots and a framing bit, which is used for synchronization and other

management purposes. At a data rate of 1.544 Mbps, frames repeat at a rate of one every 125sec, or 8000 frames per second. The transmission structure is use to support 23 B channels and 164 kbps D channel.

The line coding for the 1.544Mbps interface is AMI (Alternate Mark Inversion) using B825. The ISDN interface at 2.048 Mbps is based on the European transmission structure of the same

data rate. The bit stream is structure into repetitive 256bit frames. Each frame consists of 32,8bit time slots. The first time slot is use for framing and synchronization purposes: the remaining 32 time slots support user channels. At a data rate of 2.048Mbps, frames repeat at a rate of one every 125sec, or 8000 frames per second. The transmission structure is used to support 30B channels and 1D channel.

The line coding for the 2.048-Mbps interface is AMI using HDB3.

(a) Interface at 1.54 Mbps

(b) Interface at 2.048 Mbps

Fig: ISDN primary access frame formats

6. Explain the STS-1 overhead bit for line overhead and path overhead .(8marks) Solution:

Line overhead H1-H3: Pointer bytes used in frame alignment and frequency adjustment of payload data. B2: Bit-interleaved parity for line level error monitoring. K1, K2: Two bytes allocated for signaling between line level automatic protection switching equipment. D4-D12: 576kbps data communication cannel for alarms, maintenance, control, monitoring and administration at the line level. Z1-Z2: Reserved for future use. E2: 64kbps PCM voice channel for line level orderwire. Path overhead J1:64kps channel used to repetitively send a 64-octed fixed-length string so a receiving terminal can continuously verity the intergrity of a path; the contents of the message are user programmable. B3: Bit-interleave parity at the path level. C2: STS path signal label to designate equipped versus unequipped STS signals. G1: Status byte sent from path terminating equipment back to path originating equipment to convey status of terminating equipment and path error performance. F2: 64 kbps channel for path user. H4: Multiframe indicator for pay load needing frames that are used when packing lower rate channel. Z3-Z5:Reserved for future use.

1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8F

Time slot 1

Time slot 31

1 2 3 4 5 6 7 8

Time slot 0

1 frame =193 bits, 125 sec

1 2 3 4 5 6 7 8

Time slot 0

1 frame =256 bits, 125 sec

1 2 3 4 5 6 7 8

Time slot 32

1 2 3 4 5 6 7 8

Time slot 2

1 2 3 4 5 6 7 8

Time slot 1

framing channel

7. Draw the frame-format for SONET/SDH and show in the table from overhead octet of STS-1.(8marks)

Solution: SONET is intended to provided a specification for taking advantage of the high-speed digital transmission capacity of optical fiber.

FIGURE STS1 Frame Format

Framing A1

Framing A2

STS-ID C1

BIP-8 B2

Order Wire E1

User F1

Section overhead

Data Com D1

Data Com D2

Data Com D3

Pointer H1

Pointer H2

Pointer Action H3

BIP-8 B2

APS K1 APS K2

Data Com D4

Data Com D5

Data Com D6

Data Com D7

Data Com D8

Data Com D9

Data Com D10

Data Com D11

Data Com D12

Line overhead

Growth Z1

Growth Z2

Order wire E2

(a) Section Overhead

Synchronous payload environment(SPE)

87 octets

90 octets

Path overhead 1 octet Transport overhead 3 octets

Section overhead 8 octets

Line overhead 6 octets

Trace J1 BIP-8 B3 Signal level C2 Path status G1 User F2 Multiframe H4 Growth Z3 Growth Z3 Growth Z5

(b) Path overhead

Figure: SONET/STS-1 overhead octets

CHAPTER (8)

CIRCUIT SWITCHING

8. Write short notes on circuit-switching network.(8 marks)

Solution: Figure 8.1+ Communication via circuit switching implies that there is a dedicated communication path between two stations. That path is a connected sequence of links between network nodes. On each physical link, a logical channel is dedicated to the connection. Communication via circuit-switching involves three phases: 1. Circuit Establishment: Before any signals can be transmitted, on end-to-end circuit must be established. For example, station A sends a request to node 4 requesting a connection to station E. so, the link from A to 4 is a dedicated line. Node 4 must find the next node leading to node 6. Node 4 selects the link to node 5, and sends a message requesting connection to E. Therefore a dedicated path has been established from a through 4 to 5 and similarly, 5 to 6. Node 6 completes the connection to E. In completing the connection, a test is made to determine it E is busy or is prepared to accept the connection. 2. Data Transfer: Information can now be transmitted from A through network to E. The data may be analog or digital, depending on the nature of the network. The path is A-4 link, internal switching through 5,5-6 channel, and internal switching through 6, 6-E link, Generally, the connection is full-duplex. 3. Circuit Disconnect: After some period of data transfer, the connection is terminated, usually by the action of one of the two stations. Signals must be propagated to nodes 4,5 and 6 to de-allocate the dedicated resources.

9. Describe and explain for general architectural components for public telecommunication network. (8marks)

Solution: Four generic architectural components 1. Subscribers: The devices that attach to the network. (e g. telephone) 2. Local loop: The link between the subseriber and the network, also referred to as the subscriber loop.

Almost all local loop is in a range a few kilometers to a few tens of kilometers. 3. Exchanges: The switching canters in the network, which is directly supports subscribers is known as

an end office. An end office supports many thousands of subscribers in localized area. 4. Trunks: The branches between exchanges. Trunks carry multiple voice frequency circuits using

either FDM or synchronous TDM. Earlier, these were referred to as carrier systems.

Figure: Public- Circuit- Switching network

10. What are the signaling functions and describe.(16marks) Solution:

Signaling Functions

1. Audible communication with the subscriber, including dial tone, ringing tone, busy signal and so on.

2. Transmission of the number dialed to switching office, that will attempt to complete a connection. 3. Transmission of information between switches indicating that a call cannot be completed. 4. Transmission of information between switches indicating that a call has ended and that the path

can be disconnected. 5. A signal to make a telephone ring. 6. Transmission of information used for billing purposes. 7. Transmission of information giving the status of equipment or trunks in the network. This

information may be used for routing and maintenance purposes. 8. Transmission of information used in diagnosing and isolating system failures. 9. Control of special equipment such as satellite channel equipment.

Digital PBX

Telephone o o o o o o o o o o

o o o o o o o o o o o o o o o o o o o o

o o o o o o o o o o o o o o o o o o o o

o o o o o o o o o o

Telephone

End Office Long-Distance Office

Long-Distance Office

End Office Subscriber Loop

Connecting TrunkIntercity Trunk

Signaling can also be classified functionally as supervisory, address, call-information, and network management.

(1) Supervisory control signal

The term supervisory is generally used to refer to control function, that have a binary character C true/false; on (off) , such as request for service, answer, alerting, and return to idle; They deal with the availability of the called subscriber and of the need network resources.

(2) Address control signals

Address signals identify a subscriber, and it is generated by a calling subscriber when dialing a telephone number. The resulting address may be propagated through the network to support the routing function and to locate and ring the called subscribers phone.

(3) Call-information control signals

- provide information to the subscriber about the status of a call. - are audible tones that can be heard by the caller or operator with the proper Phone set.

(4) Network management signal - is used for maintenance, troubleshooting, and overall operator of the network. -may be in the form of message, such as a list of preplanned routes being sent to a station to update its routing tables.

11. How many types of routing techniques in circuit-switched network? Explain them.(16marks)

Solution: Two types: (1) Alternate Routing

(2) Adaptive Routing (1) Alternate Routing The essence of alternate-routing scheme is that possible routes to be used between two end offices are predefined. It is the responsibility of the originating switch to select the appropriate route for each call. Each switch is given a set of pre-planned routes for each destination, in order of preference C i.e, a direct link connection between two switches. If this trunk is unavailable, then the second choice is to be tired, and so on. The routing sequence are based on historical traffic patterns and designed to optimize the use of network resources. There are two types of Alternate-Routing Scheme.

(a) Fixed-alternate Routing If there is only one routing scheme defined for each source-destination pair, the scheme is known as a fixed-alternate-routing scheme.

(b) Dynamic Alternate-routing A different set of pre-planned routes is used for different time periods. The routing decision is based both on current traffic status and historical traffic patterns. (2) Adaptive Routing An adaptive-routing scheme is designed to enable switches to react to changing traffic patterns on the network. Such schemes require greater management overhead, as the switches must exchange information to learn of network conditions. Dynamic traffic Management (DTM) is a routing capability. DTM uses a central controller to find the best alternate route choices depending on congestion in the network. The central controller collects the status data from each switch in the network every 10 seconds to determine preferred alternate routes. Each

call is first attempted on the direct path, if any exits, between source and destination switches. If the call is blocked, it is attempted on a two-link alternate-path.

12. Explain the elements of a circuit-switched node.(16marks) Elements of a circuit-switch node are:

(1) digital switch (2) network interface element (3) control unit

(1) Digital switch The function of the digital switch is to provide a transparent signal path between any pair of attached devices, and to connect directly between them by using full-duplex transmission.

(2) Network-Interface Element The network-interface elements the functions and hardware needed to connect digital device, such as data processing devices and digital telephone, to the network. Analog telephone can also be attached if the network interface contains the logic for converting to digital signals. It provide the links for constructing multiple-node networks.

(3) Control unit The control unit performs three general tasks. First, it establishes connections. To establish the connection, the control unit must handle and acknowledge the request, determine it the switch. Second, the control unit must maintain the connection. Third, the control unit must tear down the connection.

Control unit 0 0 0 0 0 Digital 0 Switch 0 0 0 0 0 0 0 0

Network Interface

Full-

dupl

ex li

nes

To a

ttach

ed d

evic

es

FIGURE Elements of a circuit switch note

13. State and explain cross-bar switch limitation.(8marks)

Figure shows a simple crossbar matrix with 20 full-duplex I/O lines. The matrix has 10 inputs and 10 outputs, each station attaches to the matrix via one input and one output line. Interconnection is possible between any two lines by enabling the appropriate crosspoint.

Crossbar switch limitations

The number of crosspoints grows with the square of the number of attached stations. This is costly for a large switch.

The lost of crosspoint prevents connection between the two devices whose lines intersect at that crosspoint.

The crosspoints are inefficiently utilized, even when all of the attached devices are active, only a small fraction of the crosspoints are engaged.

CHAPTER (9) PACKET SWITCHING

14. Show the advantages of packet switching over circuit switching.(8marks) Solution: Advantages of Packet-switching Line efficiency is greater, as a single node-to-node link, can be dynamically shared by many packets

over time. The packets are queued up an transmitted as rapidly as possible over the link. A packet switching network can perform data-ra15te conversion. Two stations of different data rates can exchange packets because each connects to its node at its proper data rate. When traffic becomes heavy on a packet-switching network, packets are still accepted, but delivery delay increases.

Output Lines

FIGURE Space-division switch

Inpu

t Lin

es

Priorities can be used. Thus, if a node has a number of packets queued for transmission , it can transmit the higher-priority packets first. Because these packets will less delay than lower-priority packets.

15. Draw timing diagram for circuit-switch |& packet switching and describing and describe three types of delay. (8 marks)

FIGURE Event timing for circuit-switching and packet switching In figure , there types of delay are occurred;

(1) Propagation delay: The time it takes a signal to propagate from one node to the next. This time is generally negligible.

(2) Transmission Time: The time it takes for a transmitter to send out a block of data. (3) Node delay: The time it takes for a node to perform the necessary processing as it switches data. For circuit-switching, There is a processing delay at each node during the call request but is not needed the call-accept because the connection is already set-up. For Virtual-circuit packet switching, the processing delay at each node in both call request and call

accept packet. Because this packet is queued at each node and must wait its turn for retransmission, although the route is established.

Datagram packet switching does not require a call setup. It will be faster than the above two switching techniques in short messages but the processing time may be longer than virtual-circuit packets in long messages.

User Data

3 3

Propagation delay Processing

delay Call request

signal

Call accept signal

Call request packet

Acknow-ledgement

signal

Call accept packet

Acknow-ledgement

packet

Link Link Link

pkt 1

pkt 2

pkt 3 pkt 1

pkt 2

pkt 3 pkt 1

pkt 2

pkt 3

pkt 1

pkt 2

pkt 3 pkt 1

pkt 2

pkt 3 pkt 1

pkt 2

pkt 3

16. Using diagram, show the effect of packet size on transmission time.(8marks)

Y

(a ) 1 packet message

(b ) 2 packet message

(c ) 5 packet message

Data

Data

Data

Data 1 Data 2

Data 1 Data 2

Data 1 Data 2

1 2 3 4 5

1 2 3 4 5

1 2 3 4 5

X a b Y

X a b Y

X a b

( d ) 10- packet message Header

Figure : Effect of packet size on transmission time

1 2 3 4 5 6 7 8 9

10

1 2 3 4 5 6 7 8 9

10

1 2 3 4 5 6 7 8 9

10

X a b Y

17. Compare the different communication switching techniques by using tables.(16marks)

Solution: Comparison of communication switching techniques

Circuit switching Datagram packet switching

Virtual-circuit packet switching

Dedicated transmission path Continuous transmission of data Fast enough for interactive Messages are not stored The path is established for entire conversation Call setup delay; negligible transmission delay Busy signal if called party busy Overload may block call setup; no delay for established calls Electromechanical or computerized switching nodes User responsible for message loss protection Usually no speed for or code conversion Fixed bandwidth transmission No overhead bits after call setup

No dedicated path Transmission of packets Fast enough for interactive Packets may be stored until delivered Route established for each packet Packet transmission delay Sender may be notified if packet not delivered Overload increases packet delay: Small switching nodes Network may be responsible for individual packets Speed and code conversion Dynamic use of bandwidth Overhead bits in each message

No dedicated path Transmission of packets Fast enough for interactive Packets stored until delivered Route established for entire conversation Call setup delay; packet transmission delay Sender notified of connection denial Overload may block call setup; increases packet delay Small switching nodes Network may be responsible for packet sequences Speed and code conversion Dynamic use of bandwidth Overhead bits in each packet

18. Draw the diagrams of External and Internal virtual circuit and diagram.(8marks) Solution:

A

1. 3 1. 2 1. 1

2. 3 2. 2 2. 1

Packet-switched network

C

1. 3 1. 2 1. 1 B

2. 3 2. 2 2. 1

(a) External vertical circuit. A logical connection is setup between two stations. Packets are labeled with a vertical circuit number and a sequence number. Packets arrive in sequence.

(b) External datagram. Each packet is transmitted independently. Packets are labeled with the destination address and may arrive out of sequence.

(c)Internal virtual circuit: A route for packets between two stations is defined and labeled. All packet for the virtual circuit follow the same route and arrive in sequence.

(d) Internal datagram: Each packet is treated independly by the network. Packets are labeled with the destination address and may arrive at the destination node out of sequence.

FIGURE External and Internal virtual circuits and diagram.

A

B. 3 B. 2 B. 1

C. 3 C. 2 C. 1

Packet-switched network

C

B. 1 B. 3 B. 2 B

C. 2 C. 1 C. 3

A C

B

VC # 1

1

2 3

4 5

6

VC # 2

A C

B

1

2 3

4 5

6 3 3

2 1

2 1

19. Explain fixed Routing and draw the table for central routing directory for a given packet-switched

network.(16marks) Fixed Routing For Fixed Routing, a route is selected for each source-destination pair of nodes in the network. The routes are fixed, with the exception that they might change if there is movement in the topology of the network. Thus, the link costs used in designing routes could be based on expected traffic or capacity. Figure shows how fixed routing might be implemented. A certain routing matrix is created at a network control center. The matrix shows, for each source-destination pair of nodes, the identity of the next node on the route. At each node along a route, it is only necessary to know the identity of the next node, not the entire route. Ea With fixed routing, there is no difference between routing for data-grams and virtual circuits.

Advantage: It is simplicity and it work well in a reliable network with a stable Load. Disadvantage: It has lack of flexibility and it does not react to network congestion or failures.

CENTRAL ROUTING DIRETORY

From Node

- 1 5 2 4 5 2 - 5 2 4 5 4 3 - 5 3 5 4 4 5 - 4 5 4 4 5 5 - 5 4 4 5 5 6 -

2

5

3

6

1

1

2

3 8

8

1

3 2 3 1

7

4 2

1

5

2

1

3

4 5

6

FIGURE Example packed-switched network

1 2 3 4 5 6 1

2

3

4

5

6

To Node

Node 1 Directory Node 2 Directory Node 3 Directory Destination Next Node Destination Next Node Destination Next Node

2 2 1 1 1 5 3 4 2 3 2 5 4 4 4 4 4 5 5 4 5 4 5 5 6 4 6 4 6 5 Node 4 Directory Node 5 Directory Node 6 Directory

Destination Next Node Destination Next Node Destination Next Node

1 2 1 4 1 5 2 2 2 4 2 5 3 5 3 3 3 5 5 5 4 4 4 5 6 5 6 6 5 5

20. Draw the diagram of sequence of events: X.25 protocol.

Call Request

Call Connected

Incoming Call

Call Accepted

Data R=0 , S=0

Data R=2, S=0

Data R= 0, S =2

Data R=2, S =0

Data R=1, S=3

Data R=2 , S=4

Receive Ready R=3

Data R=5, S=1

Clear Request

Data R=0, S=0

Data R=0 , S =1

Data R=0 , S =1

Receive Ready 3

Data R=1, S =3

Network User Network Interface

User System B

User Network Interface

User System A

Data R=0, S=2

Data R=5, S =1

Clear Comfirmation

Clear Indication

Clear Confirmation

Data R=1 , S =4

A initiates clearing Of the virtual call

When A is informed That the call is connected , it can begin to sent data packet

A initiate a virtual call to B

B accepts the call

The packets are delivered in sequence

B has no data packet With which to acknowledege packets S= 2 . it sends a control packet

Figure Sequence Of events : X .25 protocol

CHAPTER (10)

FRAME RELAY

21. Explain Frame Relay Protocol Architecture.(16marks)

Solution: Frame relay protocol architecture Two separate planes of operation are needed in the frame-mode bearer service. Control Plane (C) The control plane for frame-mode bearer services is similar to that for common-channel signaling in circuit-switching services, in that a separate logical channel is used for control information. In the case of ISDN, control signaling is done over the D-channel, to control the establishment and termination of frame-mode virtual calls on the D, B and H channels. User Plane (U) For the actual transfer of information between end users, the user-plane protocol is LAPF C link Access Procedure for Frame-Mode Barrier Service, Only the core functions of LAPP are used for frame relay: Frame delimiting, alignment, and transparency. Frame multiplexing, demultiplexing using the address field. Inspection of the frame to ensure that it consists of an integral number of octets prior to zero-bit

extraction. Inspection of the frame to ensure that it is neither too long not too short. Detection of transmission errors Congestion control functions

Control Plane User Plane Q.931/Q.933

User-selectable TE function

LAPD (Q.922)

LAPF core (Q.922)

User (TE) User Plane Control Plane

Q.931/Q.933

LAPF control (Q.922) LAPF core (Q.922)

LAPD (Q.921)

Network (NT) FIGURE User-network interface protocol architecture.

22. Why the congestion ad voidance procedures are used? Explain two bits in the address Field are used

for congestion ad voidance procedure.(8marks)

Solution: Congestion avoidance procedures are used at the onset of congestion to minimize the effect on the network.

The two bits are Backward explicit congestion notification (BECN) Notifies the user that congestion avoidance procedures should be initiated where applicable for traffic in the opposite direction of the received frame. The notification indicates that the frames transmitted by the user on this logical connection may encounter congested resource. Forward explicit congestion notification (FECN) Notifies the user that congestion avoidance procedures should be initiated where applicable for traffic in the same direction of the received frame. The notification indicates that this frame, on this logical connection, has encountered congested resource.

23. Draw and briefly explain the comparison of X.25 and frame relay protocol stacks.(8 marks) Solution:

-User data is transmitted in frames with virtually no processing by the intermediate nodes, other than to check for errors and to route based on connection number.

- The packed handling functions of X.25 operate at layer 3 of OSI model. At layer 2, LABB is used. - The processing burden on the network for X.25 considerably higher than for frame relay.

X.25 Packet level

LAPB

Physical Layer

(a) X.25

LAPF control LAPF core Physical layer

(b) Frame relay

Figure Comparison of X.25 and Frame Relay protocol stacks

Implement by end system and network

Implement by end system and network

Implement by end system but not network

Digital Design

IT (3013)

For

Second Semester

Sample Question

1. Write down the goals of UDM. (10 marks) 2. Draw the design flow of UDM-PD (10 marks) 3. Describe the specification of UDM-PD and discuss any four. (20-marks) 4. Write down the following specification of UDM-PD (20-marks)

(a)External Block Diagram (b)Internal Block Diagram (c)Timing Estimates (d)Gate Count Estimate

5. Write down the following of specification of UDM-PD. (20-marks) (a)Package Type (b)Power consumption Target (c)Price Target (d)Test Procedure

6. (i) Describe the rules of UDM-PD design. (10-marks) (ii). A design specification should include the following (select all that apply). (10 marks) 7. What steps are contained in verification? (10 marks) 8. Express top-down design and write down any three. (20-marks) 9. Express the steps contain in verification? Write short note for these.

(a)Resimulation and formal verification (b)Place and route

What steps are contained in verification? (20-marks) 10. Discuss the followings ( 20-marks ) (a) Reusability (b) Place and route (c) Timing Estimate (d) Allocating resources 11. Explain Hardware Description Language and give an example of multiplication for two unsigned 4-bit number. ( 20 marks ) 12. Express top-down design with its spects. (10-marks) 13. Write down five rules of synchronous design. (10-marks) 14. Explain the race condition of problems and its solution with figure. (20-marks) 15. Explain delay dependent logic with figure. (10-marks) 16. Write down the hold time violation of problems and with figure. (20-marks) 17. Write down the glitches with diagram. (20-marks) 18. Explain gated clocking with diagram. (10 marks) 19. Explain floating nodes with diagram. (10-marks) 20. Discuss bus contention with diagram. (10-marks) 21. How many types of scan techniques and explain all of them. (20-marks) 22. Write verilog code for the following diagram (20 marks)

CLK

D Q

S1

SYNC-IN

CLK

DQ

G1

G2

FF1

FF2

B

CLK

CLK

OUT1

FF31

A D Q

Fig : Asynchronous: Race condition. 23. Write verilog code for the follow figure.(fig 5.12).(20 marks)

Figure:Synchronous: logic gating

24. Write the verilog code for the following figure.(20marks)

ASYNC-IN 1

OUT

DATA

GATE

CLK

10

11

D Q

SIG1

SIG2

OUT

CLK

CLR

D

SIG1

SIG2

OUT

Figure: Metastability- the solution

25(i). Match the model level on the left with the correct description on the right.(20 marks) (a) Algorithmic (A) Describes a design in terms of mathematical functionally (b) Architectural (B) Describes a design in terms of basic logic, such as NANDs and NORs. (c) Register transfer (C) Describes a design in terms of Level transistors and basic electronic components. (d) Gate level (D) Describes a design in terms of functional blocks. (e) Switch level (E) Describe a design in terms of Boolean logic and storage devices. (ii). Select all of the statements that are true about top-down design.

(a) Allow better allocation of resources (b) Allow each small function to be simulated independently. (c) Speeds up simulations. (d) Facilitates behavioral modeling of the device. (e) Results in lower power consumption designs. (f) Allows a design to be split efficiently among the various team members.

26.Express top-down design and Write down following . (20-marks)

(a)Use of Hardware Design languages (b)Written specifications

27.What is UDM and UDMPD? And then write down the goals of UDM? (20-marks) 28.Express top-down design and write down the following. (20-marks)

SYNC-IN

ASYNC-IN

CLK

IN

A

B

OUT1

OUT2

(a)Allocate resources (b)Reusability

29.Express top-down design and write down the following. (16-marks) (a)Verification (b)Know the Architecture

30(i). Which of the following HDL levels are considered behavioral levels? (a) Switch level (b) Algorithmic level (c) Gate level (d) Architectural level (e) Register transfer level (ii). Select all of the statements that are true about top-down design.

(a) Allow better allocation of resources (b) Allow each small function to be simulated independently. (c) Speeds up simulations. (d) Facilitates behavioral modeling of the device. (e) Results in lower power consumption designs. (f) Allows a design to be split efficiently among the various team members.(10marks)

31.What is the specification of UDM-PD? Describe them. (10-marks)

1

Digital Design

IT (3013)

For

Second Semester

Sample Answer & Question

2

1. Write down the goals of UDM. (10 marks)

The goals of universal design methodology are these: --Design a device that --Is free from manufacturing defects --Works reliably over the lifetime of the device. --Functions correctly in your system --Design this device efficiently, meaning --In the least amount of time --Using the least amount of resources, including person --Plan the design efficiently, meaning --Create a reasonable schedule as early in the process as possible --Know all necessary resources up front and allocate them as early in the process as possible.

2. Draw the design flow of UDM-PD (10 marks) 3. Describe the specification of UDM-PD and discuss any four. (20-marks)

Specification Review

Design

Simulate

Ship product!

System Integration and Test

Final Review

Simulate Formal V ifi i

Place and Route

Synthesize

Write a specification

Design Review

Choose chip and Tools

Verificatio

3

The specification of UDM_PD should include the following information: External block diagram showing how the chip fits into the system Internal block diagram showing each major functional section Description of the I\O pins, including,

o Output drive capability o Input threshold level

Timing estimates, including: o Setup and hold times for input pins o Propagation times for output pins o Clock cycle time

Gate count estimate Package type Power consumption target Price target Test procedures

_ External Block Diagram The external block diagram must show how the device fits into the system. This diagram will help describe the overall functionality of the device and will be a good reference for the system designers, PC board designers, designers of other chips in the system, and software developers. _ Internal Block Diagram The internal block diagram will be the starting point for the behavioral description of the device .As the behavioral HDL code changes, these changes must be incorporated into the internal block diagram. As other factors necessitate changes in the internal block diagram, these changes can also be incorporated easily into the behavioral HDL code. _ Timing Estimates Timing estimates are needed to determine which devices, vendors, and technologies can be used. You should have a good understanding of the clock frequency required for the design and also the setup and hold time requirements of the I\O. Remember to identify all asynchronous input signals. You can then discuss metastability issue with the vendors that you are considering. _ Gate Count Estimates As you gain experience designing programmable devices, estimating gate counts will become easier. For your first few designs, talk to various vendors you are considering. They will be able to help you construct reasonable estimates and determine which of their devices are appropriate for your design. 4. Write down the following specification of UDM-PD (20-marks)

(a)External Block Diagram

4

(b)Internal Block Diagram (c)Timing Estimates (d)Gate Count Estimate

(a) External Block Diagram The external block diagram must show how the device fits into the system. This diagram will help describe the overall functionality of the device and will be a good reference for the system designers, PC board designers, designers of other chips in the system, and software developers. (b) Internal Block Diagram The internal block diagram will be the starting point for the behavioral description of the device .As the behavioral HDL code changes, these changes must be incorporated into the internal block diagram. As other factors necessitate changes in the internal block diagram, these changes can also be incorporated easily into the behavioral HDL code. (c) Timing Estimates Timing estimates are needed to determine which devices, vendors, and technologies can be used. You should have a good understanding of the clock frequency required for the design and also the setup and hold time requirements of the I\O. Remember to identify all asynchronous input signals. You can then discuss metastability issue with the vendors that you are considering. (d) Gate Count Estimates As you gain experience designing programmable devices, estimating gate counts will become easier. For your first few designs, talk to various vendors you are considering. They will be able to help you construct reasonable estimates and determine which of their devices are appropriate for your designs. 5. Write down the following of specification of UDM-PD. (20-marks)

(a)Package Type (b)Power consumption Target (c)Price Target (d)Test Procedure

(a)Package Type Package type is often a very large percentage of the entire cost of an FPGA .Understand the package options offered by different vendors. Also you will need to understand the capabilities of your PC board layout designers and fabrication facilities to work with the different package types. (b)Power consumption Target Be certain you understand the variable that affect the devices s power consumption .You must also understand how the devices operation will affect overall board and system power consumption .Finally ,whoever is designing or choosing the power supply will need to know how much power, typical case and worst case, each chip in the system will require.

5

(c)Price Target For most projects, you will need a realistic price target. This target can help you determine the necessary tradeoffs between pin count, functionality, speed, package type, and other factors. (d)Test Procedure Test procedure must know at a very early stage of the design flow. Too often, design teams leave test procedures for the end of the design flow at which time they discover that the device cannot be tested completely or accurately. If the tests require software, the software team must begin planning the test very early, and they must have input into the hardware design so that testability is built in from the beginning. 6. (i) Describe the rules of UDM-PD design. (6-marks)

The rules of UDM-PD design When designing the chip, remember to design according to the rules, These are:

Use top-down design Work with the device architecture Do synchronous design Protect against metastability Avoid floating nodes Avoid bus contention

(ii). A design specification should include the following (select all that apply). (a) The name of the FPGA vendor. (b) A description of the I/O pins, including output drive capabilities and input

threshold levels. (c) The estimated gate count. (d) The target power consumption. (e) Test procedures, including in-system test requirements. (f) An external block diagram showing how the FPGA fits into the system. (g) A notice that the document, once approved, cannot be changed. (h) An internal block diagram showing each major functional section.

(i) Timing estimates, including setup and hold times for input pins, propagation times for output pins, and the clock cycle time.

(j) The target price. (k) The package type. (iii)Here is the design flow with each phase in the correct order. (c)Write a specification (e) Specification review (g) Choose device and tools (k) Design (h) Simulate (j) Design review (l) Synthesis (i) Place and route

6

(f) Resimulation (d) Final review (b) System integration and test (a) Ship product 7. What steps are contained in verification? (10 marks)

Verification is a super-phase because it consists of several other phase of the design process. Which exact phases that makes up verification is open to argument, but generally verification can be broken into several phases, each of which is essential to the entire process. These steps consists of ---Simulation ---Design review ---Synthesis ---Place and route ---Formal verification 8. Express top-down design and write down any three. (20-marks)

Top-Down Design Top-down design is the design methodology whereby high level functions are defined first, and the lower level implementation details are filled in later. The top level block represents the entire chip. The next lower level blocks also represents the entire chip but divided into the major function blocks of the chip. Intermediate level contains only gates and macro functions.

Figure. Top- down design

_ Allocating Resources

Gat

e

1

2 4 3

6 5 8 7 10 9

1 1 1 1 1 1 1 1 1 2 2 2 2

Behavioral

RTL

7

Chips typically incorporate a large number of gates and a very high level of functionality. A top. down approach simplifies the design task and allows more than one engineer, when necessary, to design the chip. For example, the lead designer or the system architect may be responsible for the specification and the top-level blocks, depending on their strength, experience, and abilities. An experienced ALU designer may be responsible for the ALU block and several other blocks .A junior engineer can work on a smaller block, such as a bus controller. Each engineer can work in parallel, writing code and simulating, until it is time to integrate the pieces into a single design. No one person can slow down the entire design. _Design Partitioning If you are the only engineer designing the chip, this methodology allows you to break the design into simpler function that you can design and simulate independently from the rest of the design. A large, complex design becomes a series of independent smaller ones that are easier to design and simulate. _Reusability CPLDs and FPGAs contains so much logic that reusing any function from a previous design can save days,weeks,or months of design time. When one group has already designed a certain function, say a fast, efficient 64-bit multiplier, HDLs allow you to take the design and reuse it in your design. If you need a 64-bit multiplier, you cam simply take the designed, verified code and plop it into your design. Or you can purchase the code from a third party. But it will only fit easily into your design if you have used a top-down approach to break the design into smaller pieces, one of which is 64-bit multiplier. 9. Express the steps contain in verification? Write short note for these. (20-marks)

(a)Resimulation and formal verification (b)Place and route

_ What steps are contained in verification? Verification is a super-phase because it consists of several other phase of the

design process. Which exact phases that makes up verification is open to argument, but generally verification can be broken into several phases, each of which is essential to the entire process. These steps consists of ---Simulation ---Design review ---Synthesis ---Place and route ---Formal verification

(a)Resimulation and formal verification

At this stage, design team must check the results of synthesis to make sure that

8

the RTL design that was fully simulated is functionally equivalent to the gate level design that was produced after synthesis some case ,it may also be necessary to show that the configuration of the programmable device behaves identically to the RTL description. There are two ways to do this: by resimulation the lowest level design or by using formal verification. In some case, both techniques can be used for further certainty.

(b)Place and route The next step is to lay out the chip, resulting in a real layout for a real chip. This

involves using the vendors software tools to place various functions into the available blocks in the device and to route the blocks together. The software will figure out the bits needed to program the chip to implement the design. If you cannot successfully place the design into the device and route it you may need to tweak the design. In some cases, you will need to make radical changes, such as eliminating some functionality or using a larger device. If you have followed all of the procedures outlined in this book, the chances of a major problem at this stage, resulting in a major design change, will be minimized.

Once the place and route is successful, the design team must perform timing analysis. 10. Discuss the followings ( 20-marks ) (a) Reusability (b) Place and route (c) Timing Estimate (d) Allocating resources (a)Reusability CPLDs and FPGAs contains so much logic that reusing any function from a previous design can save days,weeks,or months of design time. When one group has already designed a certain function, say a fast, efficient 64-bit multiplier, HDLs allow you to take the design and reuse it in your design. If you need a 64-bit multiplier, you cam simply take the designed, verified code and plop it into your design. Or you can purchase the code from a third party. But it will only fit easily into your design if you have used a top-down approach to break the design into smaller pieces, one of which is 64-bit multiplier. (b)Place and route

The next step is to lay out the chip, resulting in a real layout for a real chip. This involves using the vendors software tools to place various functions into the available blocks in the device and to route the blocks together. The software will figure out the bits needed to program the chip to implement the design. If you cannot successfully place the design into the device and route it you may need to tweak the design. In some cases, you will need to make radical changes, such as eliminating some functionality or using a larger device. If you have followed all of the procedures outlined in this book, the

9

chances of a major problem at this stage, resulting in a major design change, will be minimized.

Once the place and route is successful, the design team must perform timing analysis. (c) Timing Estimates Timing estimates are needed to determine which devices, vendors, and technologies can be used. You should have a good understanding of the clock frequency required for the design and also the setup and hold time requirements of the I\O. (d) Allocating Resources Chips typically incorporate a large number of gates and a very high level of functionality. A top. down approach simplifies the design task and allows more than one engineer, when necessary, to design the chip. For example, the lead designer or the system architect may be responsible for the specification and the top-level blocks, depending on their strength, experience, and abilities. An experienced ALU designer may be responsible for the ALU block and several other blocks .A junior engineer can work on a smaller block, such as a bus controller. Each engineer can work in parallel, writing code and simulating, until it is time to integrate the pieces into a single design. No one person can slow down the entire design. 11. Explain Hardware Description Language and give an example of multiplication for two unsigned 4-bit number. ( 20 marks ) Design teams can use a hardware description language to design at any level of abstraction, from high level architectural models to low-level switch models. These levels, from least amount of detail to mist amount of detail are as follows: Behavioral models

Algorithmic Architectural

Structural models Register Transfer Level (RTL) Gate level Switch level

No hardware implementation is implied in an algorithmic model. The algorithmic model is coded to be fast, efficient, and mathematically correct. An algorithmic model of a circuit can be simulated to test that the basic specification of the design is correct.

Architectural models specify the blocks that implement the algorithms. Architectural models may be divided into blocks representing PC boards, ASICs, FPGAs, or other major hardware components of the system.

Sample behavioral level HDL code always @(posedge multiply_en) begin

10

Product

11

Figure. Top- down design

13. Write down five rules of synchronous design. (10-marks)

Five Rules of Synchronous Design Five rules to define synchronous design for a single clock domain. ( A single clock domain means that all logic is clocked by a single clock signal.

1. All data is passed through combinational logic, and through delay elements, typically flip-flops, that are synchronized to a signal clock.

2. Delay is always controlled by delay elements, not combinatorial logic. 3. No signal that is generated by combinatorial logic can be fed back to the same

combinatorial logic without first going through a synchronizing delay element. 4. Clocks cannot be gated; clocks must go directly to the clock inputs of the delay

elements without going through any combinatorial logic. 5. Data signals must go only to combinatorial logic or data inputs of delay elements.

14. Explain the race condition of problems and its solution with figure. (20-marks) How does this logic behave? When SIG2 is low, the flip-flop is reset to a low state. On the rising edge of SIG2, the designer wants the output, OUT, to change to reflect the current state of the input, SIG1. Because we do not know the exact internal timing of the flip-flop or the routing delay of the reset input, we cannot know which signal will effectively arrive at the appropriate logic first- the clock or the reset. This is a race condition. If the clock rising edge arrives first, the output will remain low. If the

Gat

e

1

2 4 3

6 5 8 7 10 9

1 1 1 1 1 1 1 1 1 2 2 2 2

Behavioral

RTL

12

reset signal arrives first, the output will go high. A slight change in temperature, voltage, or process may cause a chip that works correctly to suddenly work incorrectly because the order of arrival of the two signals changes. When creating a synchronous design, or converting an asynchronous design to a synchronous one, is to draw a state diagram. The state diagram for this function is shown in Figure (a). From this diagram, it is easy to design the more reliable, synchronous solution shown in Figure (b). Here their flip-flop is reset synchronously on the rising edge of a fast clock. Ive introduced a new signal, STATE, that together with the OUT signal. This circuit performs the correct function, and as long as SIG1 and SIG2 are produced synchronously- they change only after the rising edge of CLK- there is no race condition. The synchronous design uses more logic adding delay and using up expensive die space. They may also argue that the fast clock means that this design will consume more power. The design introduces extra signals that require more routing resources, add delay and again, that consume precious die space. All of this is true. This design, however will work reliably and the previous design will not.

Figure (a) Synchronous state diagram

SIG2 & SIG1

STATE 0 OUT 0

STATE 0 OUT 0

STATE 0 OUT 0

SIG2 & SIG1

SIG2 SIG2

13

Figure (b) Synchronous No race condition 15. Explain delay dependent logic with figure. (10-marks) Figure (a) shows an asynchronous circuit used to create a pulse. The pulse width depends very explicitly on the delay of the individual logic gates. If the semiconductor process used to manufacture the chip should change, making the delay shorter, the pulse width will shorten also, to the point where the logic that it feeds may not recognize it at all. A synchronous version of a pulse generator is shown in Figure(b). This pulse depends only on the clock period. As our rule number 2 of synchronous design states,

CLK

CLK

CLK

SIG2

STATE

SIG1

OUT

0

0

STATE

OUT

SIG1

SIG2

OUT

14

delay must always be controlled by delay elements. Changes to the semiconductor process will not cause any significant change in the pulse width for this design.

Figure (a) Asynchronous : Delay dependent logic

Figure (b) Synchronous: Delay independent logic

CLK

A 0 0

CLKA

Z

Z

Pulse width

Z

A3

A

A ZA1 A2 A3

15

16. Write down the hold time violation of problems and with figure. (20-marks)

Hold Time Violations Figure(a) shows an asynchronous circuit with a hold time violation. Hold time violations occur when data changes around the same time as the clock edge; it is uncertain which value will be registered by the clock the value of the data input right before the clock edge or the value right after the clock edge. It all depends on the internal characteristics of the flip-flop. This can also result in met stability. The circuit in figure (b) fixes this problem by putting both flip-flop on the same clock and using a flip-flop with an enable input. A pulse generator creates a palse, signal Dp3,by ANDing signal D3 and a signal D3d,which is D3 delay by a signal clock cycle. The pulse D3p enables the flip-flop for one clock cycle. The pulse generator also turns out to be very useful for synchronous design, when you want to clock data into a flip-flop after a particular event.

Figure (a) Asynchronous: Hold time violation

CLK

0 0

0 0

D2

D1

CLK

D1

D2

D3

D4

Hold time violation

16

Figure (b) Synchronous: No hold time violation

17. Write down the glitches with diagram. (20-marks) A glitch can occur due to small delays in a circuit, such as that shown in Figure. The output would be high no matter what the value of the select input, One should be able to change the select input from how to high and back to low again and still get a high value out. In practice, trough, the multiplexer produces a glitch when switching the select input. This is because of the internal design of the multiplexer, as shown in Figure. Due to the delay of the inverter on the select input, there is a short time when signals SEL and SELn are both low. Thus neither input is selected, casing the output to go low.

Synchronizing this output by sending it through a flip-flop, as shown in Figure (b), ensure that this glitch will not appear on the output and will not affect logic further down stream. As long as the timing calculation have been performed correctly, the entire design is synchronous, and the device is operated below the maximum clock frequency for the design, glitches such as this one will settle before the next clock edge.

D4

D3p

D3d D3

CLK

CLK

CLK

D 0 ENA

D 0

CLK

D 0

D2

D1

D1

D2

D3

D3d

D3p

D4

17

Figure Asynchronous

Figure (b) Synchronous : No glitch

18. Explain gated clocking with diagram. (10 marks)

Figure (a) shows as an example of gated clocking. This violates the fourth and fifth rules of synchronous design This kind of clock gating will produce problems that will particularly bad in FPGAs, because the GATE signals can easily be delayed so that the clock signals rise before the GATE signals can prevent it.

SEL SELn

CLK

01

00

01

SEL

SELn

Zp

0 0

Z

Z

CLK

SELn

CLK

01

SEL

Z

00

01

SEL

SELn

Z

glitch

18

The correct way to enable and disable outputs is not buy putting logic on the clock input, as shown in Figure(b). In this synchronous design, the flip-flop is always being clocked directly by the CLK signal. The GATE input controls the mux on the input, to determine whether the new data gets clocked in or the old data gets clocked back in.

Figure (a) Asynchronous Clock gating

Figure (b) Synchronous Logic gating 19. Explain floating nodes with diagram. (10-marks) Floating nodes are internal nodes of a circuit that are not driven to a logic 0 or logic 1 If signals SEL_A and SEL_B are both not asserted, signal OUT will float to an unknown level. Downstream logic may interpret OUT a login 1 or logic 0, or the floating signal may create a metastable state. In particular, any CMOS circuit that uses signal OUT as an input will use up power because CMOS dissipates power when the input is in

0 0DATA

GATE

CLK

OUT

OUT 0 0

10 11 DATA

GATE

CLK

19

the threshold region. The signal OUT will typically float somewhere in the threshold region. If downstream logic is not using this signal, the signal can bounce up and down, causing noise and inducing noise in surrounding signals. Two solutions to the floating node problem are shown in figure (b).At the top, signal OUT is pulled up using an internal pull-up resistor. This simple fix ensures that when both signals are not asserted, OUT will be pulled to a good logic level. The pull up represented in the picture may be an active pull up circuit that can be faster and more power conservative. The other solution is to make sure that something is driving at all times. A third select signal is created that drives the OUT signal to a good level when neither of the other normal select signals are asserted.

Figure (a) Floating nodes the problem

NOTE: SEL_A and SEL_B are mutually exclusive

Figure (b) Floating nodes solutions NOTE: SEL_A and SEL_B are mutually exclusive

B

SEL_B

SEL_A

A

OUT

B

SEL_B

SEL_A

A

B

SEL_B

SEL_A

A

OUT

OUT

Pull up

20

20. Discuss bus contention with diagram. (10-marks)

Bus contention

Bus contention occurs when two outputs drive the same signal at the same time as shown in fig(b).This reduce the reliability of the chip because it has multiple drivers fighting each other to drive a common output. If bus contention occurs regularly, even for short time, the possibility of damage to the drivers increases. One place where this can occurs, and that is ignored, is during the turn around of the bus. In a synchronous bus, when one device is driving the bus during one clock cycle and a different device is driving during the next clock cycle, there is a short time when both devices may be driving the bus, as shown in fig(a). To avoid contention problems, the designer must ensure that both drivers cannot be asserted simultaneously. This can be accomplished by inserting additional logic, as shown in fig (c).The logic for each buffer enable has been modified so that a buffer is not turned on until its select line is asserted and all other select lines have been de.asserted.Due to routing delays, some contention may still occurs, but this circuit has reduced it significantly. The best solution may be to find better implementations. Other solutions involve designing the system so that there is always a clock cycle where nothing is driving the bus.

21. How many types of scan techniques and explain all of them. (20-marks)

Scan Techniques

Scan techniques sample the internal nodes of the chip serially so that they can be observed externally. The scan enable input (SE) is low; the normal data input gets clocked into the flip-flop. In san mode, through the scan enable input is high, causing the scan data (SD) to get clocked into the flip-flop. There are two main scan techniques, full scan and boundary scan. Full scan involves creating scan chain from every flip-flop in the design.Boundry scan involves using only flip-flops that are connected to I\O pins in the scan chains.

21

Figure (a) Scan flip-flop

Figure(b) Scan Chain

_ Full scan When performing full scan, the entire chip is put into the scan mode, and the scan enable inputs to the scan flip-flop are asserted. Testers can examine the state of each flip-flop in the design. This technique of scanning patterns into and out of the the chip is used for finding physical defects in ASICs after production. Because FPGAs are not tested after production, expect manufacture, the use of scan is restricted to functional testing of FPGAs, if it is used at all. During debugging, if the chip malfunction, it can be halted, put into the scan mode, and the state of each flip-flop can be read via the scan. These bits can be loaded into a simulation of

CLK

SE

SD

10 11

D 0 0

D

OUT1

SCAN

D 0

SD

SE

D 0

SD

SE

IN1

SCAN_IN

SCAN

CLK

IN2

CLK

OUT2

22

the design to help figure out what went wrong. The simulation data can be scanned back into the chip to put the chip into a know starting state. The major problem with using this kind of technique for functional testing is that scanning requires a lot of software development. Each flip-flop bit must be stored, and the software must know what to do with it. If the state is to be loaded into a simulators, there must be software to convert the state information to the simulators format and back again. If states are scanned into the chip, one must be careful not to scan in illegal states. There are other considerations, such as what to do with the clock and what to do with the rest of the system while the chip is being scanned. Avoiding these problems require not only a certain level of sophistication in the software, may also require extra hardware. _ Boundary Scan Boundary scan is somewhat easier to implement and does not to add as much logic to the design. Boundary scan reads only nodes around the boundary of the chip, not internal node. Limiting the scan to boundary nodes avoids internal contentionproblems, but not contention problems with the rest of the system .Boundary scan is useful for testing the rest of your system, because testers can toggles the chip outputs and observe the effect on the rest of the system.Boundary scan can be used to check for defective solder joints or other physical connections between the chip and the printed circuit board or between the chip and other chips in the system. The Institute of Electrical and Electronic Engineer (IEEE) has created a standard for boundary scan called JTAG, or IEEE 1149.1.It covers pin definitions and signaling. 22. Write verilog code for the following diagram (20 marks)

Fig : Asynchronous: Race condition.

SIG1

SIG2

OUT

CLK

CLR

D

SIG1

SIG2

OUT

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//how to synthesize it into a synchronous circuit // /* * * * * * * * * * * * * / //DEFINES //TOP MODULE module arace( sig 1, sig 2, out); //PARAMETERS //INPUTS

input sig1; input sig2;

//OUTPUTS output out;

//INOUTS //SIGNAL DECLARATIONS

wire sig1; wire sig2; reg out;

//ASSIGN STATEMENTS //MAIN CODE //Reset condition

always @ (negedge sig2)out

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//ASSIGN STATEMENTS //MAIN CODE endmodule //arace

always @ (posedge sig2) out

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// //FILE NAME : not_gated.v //VERSION : 1.0 //DATE : June 1,2002 //AUTHOR : Bob Zeidman , Zeidman Consulting // //DESCRIPTION : This module defines a circuit without a //gated clock . This is an enable flip-flop. // /* * * * * * * * * * * * * * */ //DEFINES //TOP MODULE module not_gated( clk, data, e, out); //PARAMETERS //DEFINES //TOP MODULE module less-meta( clk; async_in, out1, out2); //PARAMETERS //INPUTS input clk; input async_in; //OUTPUTS output out1; output out2; //INOUTS //SIGNAL DECLARATIONS wire clk; wire async_in;

reg in; reg out1; reg out2;

//ASSIGN STATEMENTS //MAIN CODE // clocked condition

always @ (posedge clk) begin sync_in < = async_in;

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CLK

D Q

S1

SYNC-IN

CLK

DQ

G1

G2

FF1

FF2

B

CLK

CLK

OUT1

FF31

A D Q

in

27

//VERSION : 1.0 //DATE : June1,2002 //AUTHOR : Bob Zeidman, Zeidman Consulting // //CODE TYPE : RTL // //DESCRIPTION : This module defines a circuit that an asynchronous input. It uses a synchronizing flip-flop to lessen the chance of //metastability. // //* * * * * * * * * * * * * * * */ //ASSIGN STATEMENTS assign d3p=d3 & ~d3d; //MAIN CODE //Clocked condition always @ (posedge clk) begin d3< = d1; d3d< = d3; if (d3p) d4

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defines a circuit that can /* * * * * * * * * * * * */ //MODULE : less metastable circuit // //FILE NAME: less_meta.v //VERSION : 1.0 //DATE : June1,2002 //AUTHOR : Bob Zeidman, Zeidman Consulting // //CODE TYPE : RTL // //DESCRIPTION : This module defines a circuit that an asynchronous input. It uses a synchronizing flip-flop to lessen the chance of //metastability. // //* * * * * * * * * * * * * * * */ //ASSIGN STATEMENTS assign d3p=d3 & ~d3d; //MAIN CODE //Clocked condition always @ (posedge clk) begin d3< = d1; d3d< = d3; if (d3p) d4

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(c) Register transfer (C) Describes a design in terms of Level transistors and basic electronic components. (d) Gate level (D) Describes a design in terms of functional blocks. (e) Switch level (E) Describe a design in terms of Boolean logic and storage devices. (a) Algorithmic (A) Describes a design in terms of mathematical functionally (b) Architectural (D) Describes a design in terms of functional blocks. ( c )Register transfer (E) Describe a design in terms of Boolean Level logic and storage devices (ii). Select all of the statements that are true about top-down design.

(a) Allow better allocation of resources (b) Allow each small function to be simulated independently. (c) Speeds up simulations. (d) Facilitates behavioral modeling of the device. (e) Results in lower power consumption designs. (f) Allows a design to be split efficiently among the various team members.

(a) Allow better allocation of resources (b) Allow each small function to be simulated independently. (c) Speeds up simulations. (d) Facilitates behavioral modeling of the device. (f) Allows a design to be split efficiently among the various team members. 26.Express top-down design and Write down following . (20-marks)

(a)Use of Hardware Design languages (b)Written specifications

Top-Down Design

Top-down design is the design methodology whereby high level functions are defined first, and the lower level implementation details are filled in later. The top level block represents the entire chip. The next lower level blocks also represents the entire chip but divided into the major function blocks of the chip. Intermediate level contains only gates and macro functions.

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Figure. Top-Down design (a)Use of Hardware Design languages Top-down design methodology lands itself particular well to using HDLs,the accepted method of designing complex CPLDs and FPGAs .Each block in the design corresponds to the code for a self-contained module. The top-level block corresponds to the behavioral models that comprise the chip. The intermediate levels correspond to the RTL models that will become input to the synthesis process. The lowest level of the hierarchy corresponds to gate level code which is output from the synthesis software and which directly represents logic structures within the chip. (b)Written specifications The specification must include general aspects of the design, including the major functional blocks. The highest blocks of top-down design are behavioral level models that correspond to the major functional blocks described in the specification .Using a top-down design approach, the specification becomes a starting point for the actual HDL code. Specification change can immediately be turned into HDL design change, and design change can be quickly and easily translated back to the specification, keeping the specification accurate and up to date. 27.What is UDM and UDMPD? And then write down the goals of UDM? (20-marks) _What is UDM and UDM-PD?

It would have to be one methodology that applied universally to large and small companies in any industry. Rather than being a method that describes very specific steps,

Gat

e

1

2 4 3

6 5 8 7 10 9

1 1 1 1 1 1 1 1 1 2 2 2 2

Behavioral

RTL

31

it would need to a methodology that could be generally applied to different design. We called this methodology the Universal Design Methology. As technology changed, the methodology was adopted. The different types of devices required slightly different methodologies. ASICs and printed circuit boards required slightly different methodologies than FPGAs and CPLDs. The methodology described here is specifically for programmable devices and call it UDM-PD. _ Write down the goals of UDM.

The goals of universal design methodology are these: --Design a device that --Is free from manufacturing defects --Works reliably over the lifetime of the device. --Functions correctly in your system

--Design this device efficiently, meaning 28.Express top-down design and write down the following. (20-marks)

(a)Allocate resources (b)Reusability

Top-Down Design

Top-down design is the design methodology whereby high level functions are defined first, and the lower level implementation details are filled in later. The top level block represents the entire chip. The next lower level blocks also represents the entire chip but divided into the major function blocks of the chip. Intermediate level contains only gates and macro functions.

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Figure:Top-Down design

(a) Allocating Resources Chips typically incorporate a large number of gates and a very high level of functionality. A top. down approach simplifies the design task and allows more than one engineer, when necessary, to design the chip. For example, the lead designer or the system architect may be responsible for the specification and the top-level blocks, depending on their strength, experience, and abilities. An experienced ALU designer may be responsible for the ALU block and several other blocks .A junior engineer can work on a smaller block, such as a bus controller. Each engineer can work in parallel, writing code and simulating, until it is time to integrate the pieces into a single design. No one person can slow down the entire design. (b) Reusability CPLDs and FPGAs contains so much logic that reusing any function from a previous design can save days,weeks,or months of design time. When one group has already designed a certain function, say a fast, efficient 64-bit multiplier, HDLs allow you to take the design and reuse it in your design. If you need a 64-bit multiplier, you cam simply take the designed, verified code and plop it into your design. Or you can purchase the code from a third party. But it will only fit easily into your design if you have used a top-down approach to break the design into smaller pieces, one of which is 64-bit multiplier.

Gat

e

1

2 4 3

6 5 8 7 10 9

1 1 1 1 1 1 1 1 1 2 2 2 2

Behavioral

RTL

33

29.Express top-down design and write down the following. (16-marks) (a)Verification (b)Know the Architecture

Top-Down Design Top-down design is the design methodology whereby high level functions are defined first, and the lower level implementation details are filled in later. The top level block represents the entire chip. The next lower level blocks also represents the entire chip but divided into the major function blocks of the chip. Intermediate level contains only gates and macro function

Figure:Top-Down design

(a)Verification Top-down design is one important means for improving verification. A top-down design approach allows each module to be simulated independently from the rest of the design. This is important for complex designs where an entire design can take weeks to simulate and days to debug. By using a top-down approach, design teams can efficiently perform behavioral, RTL, and gate level simulation and use the results to verify functionality at each lave of design. Top down design facilitates these good design practices:

Use of hardware design languages Writing accurate and up-to-date specifications Allocation of resources for the design task Simplification and easy partitioning of the design task Flexibility in experimenting with different designs and optimizing the design Reusing previous designs

Gat

e

1

2 4 3

6 5 8 7 10 9

1 1 1 1 1 1 1 1 1 2 2 2 2

Behavioral

RTL

34

Floor planning Improved the verification and less time spent on verification (b)Know the Architecture

Look at the particular architecture for the CPLDs or FPGAs that you are using to determine which logic devices fit best into it. Many FPGA and CPLD vendors include specialized logic functions in their devices. For example, vendors may offer a device with a built-in digital signal (DSP).This device will not be useful, and is the wrong choice, if your design does not use a DSP.On the other hand, if you are implementing signal processing functions, you should make sure you use this DSP function as much as possible throughout the design. The vendor will be able to offer advice about their device architecture and how to efficiently utilize it. 30(i). Which of the following HDL levels are considered behavioral levels? (a) Switch level (b) Algorithmic level (c) Gate level (d) Architectural level (e) Register transfer level (b) Algorithmic level (d) Architectural level (ii). Select all of the statements that are true about top-down design.

(a) Allow better allocation of resources (b) Allow each small function to be simulated independently. (c) Speeds up simulations. (d) Facilitates behavioral modeling of the device. (e) Results in lower power consumption designs. (f) Allows a design to be split efficiently among the various team members.

(a) Allow better allocation of resources (b) Allow each small function to be simulated independently. (c) Speeds up simulations. (d) Facilitates behavioral modeling of the device. (f) Allows a design to be split efficiently among the various team members 31.What is the specification of UDM-PD? Describe them. (8-marks)

The specification of UDM_PD should include the following information:

External block diagram showing how the chip fits into the system Internal block diagram showing each major functional section Description of the I\O pins, including,

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o Output drive capability o