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Joint Variable Partitioning and Bank Selection Instruction Optimization on
Embedded Systems with Multiple Memory Banks
Liu Tiantian, Minming Li, Chun Jason XueCity University of Hong Kong
2010.1.19
2
Outline of this talkOutline of this talk
Background & Related work
What the problem is? Variable partitioning & BSL insertion
How to solve the problem?For speedFor space
Experimental results
3
BackgroundBackground
88--bit microcontrollersbit microcontrollersAbout 55% of all CPUs sold in the world are 8-bit microcontrollersCan access limited memory with few buses and smaller address registers
Partitioned memory architecturePartitioned memory architectureZilog Z80 and MOS6502 series:
16 bit address registers can only addressa maximum of 64 KB memory=> support more than 64 KB memory by partitioning it into banks
Bank SwitchingBank Switching::Only can access one bank at a time, bank registerbank register.
Bank selection instructions (Bank selection instructions (BSLsBSLs)): instructions needed to be inserted into the original programs to modify the bank register to point to the wanted bank.
Their insertions increase both code size and runtime overheadcode size and runtime overhead.
4
What we focus on?What we focus on?
to minimize the size and time overhead introduced by minimize the size and time overhead introduced by BSLsBSLs. . Speed overheadSpeed overhead (means runtime increase) minimization
Space overheadSpace overhead (means code size increase) minimization
Variable partitioningVariable partitioningCurrent techniques aim at achieving the maximum instruction level parallelism for architectures which allow multiple banks to be accessed simultaneously
BSL insertionBSL insertionCurrent compilers provide limited support to generate bank switching code optimally.
The two process are related to each other and affect the overhead.
5
Related WorkRelated WorkBSL minimization
Bernhard Scholz, Bernd Burgstaller, Jingling Xue, ”Minimal Placement of Bank Selection Instructions for Partitioned Memory Architectures,” ACM Transactions on Embedded Computing Systems (TECS), Vol. 7, No. 2: 1-32, 2008.Bernhard Scholz, Bernd Burgstaller, Jingling Xue, ”Minimizing Bank Selection Instructions for Partitioned Memory Architectures,” CASES06: 201-211, 2006.
assume the variables have already been assignedassume the variables have already been assigned to memory banks present an optimization technique that minimizes the overhead of BSLs.
Yuan Mengting, Wu Guoqing, Yu Chao, ”Optimizing Bank Selection Instructions by Using Shared Memory,” ICESS2008: 447-450, 2008.
assume the variables have already been partitionedassume the variables have already been partitioned into banks. consider using the architecture with a shared memory bank
Variable partitioning: most aim at achieving the maximum instruction level parallelism for architectures which allow multiple banks to be accessed simultaneously.
transform the variable partitioning problem to an Interference Graph (IG)to an Interference Graph (IG) or Variable Variable Independence Graph (VIG)Independence Graph (VIG) to find the parallelism between variablescombined with instruction scheduling problemscheduling problem for multi-core DSP architecturesoptimizing energy consumptionenergy consumption: try to determine when to power some banks down
There is no variable partitioning techniques for BSL overhead miThere is no variable partitioning techniques for BSL overhead minimizationnimization which is important for embedded systems with multiple memory banks.
6
Outline of this talkOutline of this talk
Background & Related work
What the problem is? Variable partitioning & BSL insertion
How to solve the problem?For speedFor space
Experimental results
7
(a) Multi-bank architecture (b) Application model: DFG
v1
v2 v3
v4 v5 v6
v8
v7
60 40320
33 27 40
402733
100
a1
a2 a4
a1
a6a3
a5
a4
8-bit micro-controller
MemoryBank 1
(B1)
MemoryBank 2
(B2)
MemoryBank k
(Bk)
Bank register
Variables: a1, a2, …, an
……
0
m-1
0
m-1
0
m-1
What the problem is? Variable partitioningWhat the problem is? Variable partitioning
BBii: a memory bank,size of m
aaii: a variable, size of 1B(aB(aii)): the memory
bank storing ai
vvii: a node, is a basic data accessing block
A(vA(vii)): the variable accessed by vi
DFGDFG: Data Flow Graph, to model an embedded application
e(ue(u, v), v): an edge, the control flow of code
w(e(uw(e(u, v)), v)): the execution frequency of e(u, v)
In the system, we have in total:k banks: B1 ,… Bk , each of size mn variables: v1 ,… vn , each of size 1k*m>=n
The n variables need to be partitioned into the k banks
8
Wha
t the
pro
blem
is?
BSL
Inse
rtio
nW
hat t
he p
robl
em is
? B
SL In
sert
ion
Whe
n a
node
u a
nd o
ne o
f its
chi
ldre
n v
acce
ss v
aria
bles
that
are
in
diffe
rent
ban
ks, a
BS
L ne
eds
to b
e in
serte
d.Th
ere
are
thre
e po
ssib
le p
ositi
ons
to in
sert
this
BS
L:
at th
e ex
it of
nod
e u
at th
e ex
it of
nod
e u;
at e
dge
at e
dge
e(u
e(u ,
v)
, v);
at th
e en
tranc
e of
nod
e v
at th
e en
tranc
e of
nod
e v.
The
thre
e po
sitio
ns h
ave
diffe
rent
impa
cts
on s
peed
and
spa
cedi
ffere
nt im
pact
s on
spe
ed a
nd s
pace
over
head
s.
u v
u ac
cess
es a
1,a1
is s
tore
d in
B1
v ac
cess
esa2
,a2
is s
tore
d in
B2
BS
L
BS
L
BS
L
Inse
rting
at t
he e
xit o
f no
de v
3 is
not
a
good
sol
utio
n fo
r sp
eed.
Inse
rting
at t
he
entra
nce
of n
ode
v7 is
a g
ood
solu
tion
for s
pace
.
320
v 3 v 6
a 4 a 6
v 4v 5
v 6
v 7
4027
33
a 1
a 6a 4
a 3
40BSL BSL
BSL
BSL
BSL
BSL
BSL
BSL
BSL
BSL
(a)
For S
peed
(
b) F
or S
pace
9
Mot
ivat
iona
l Exa
mpl
eM
otiv
atio
nal E
xam
ple
Ass
ume
we
have
a d
ual-b
ank
arch
itect
ure
and
each
ban
k ha
s a
size
of t
hree
.
The
varia
ble
parti
tioni
ng te
chni
ques
und
er
com
paris
on a
re:
Equ
ally
par
titio
ning
acc
ordi
ng to
re
fere
nce
orde
rP
artit
ioni
ng fo
r par
alle
lism
[8]
The
prop
osed
alg
orith
ms
for s
peed
The
prop
osed
alg
orith
ms
for s
pace
v 1
v 2v 3
v 4v 5
v 6
v 8v 7
6040
320
3327
40
4027
33
100
a 1
a 2a 4
a 1
a 6a 3
a 5a 4
10
Mot
ivat
iona
l Exa
mpl
eM
otiv
atio
nal E
xam
ple --
Res
ults
Res
ults Th
e pr
opos
ed a
lgor
ithm
fo
r spa
ce a
lso
offe
rs a
n op
timal
so
lutio
n fo
r spe
ed
of 2
00 B
SL-
cycl
es
Even
for s
uch
a sm
all
exam
ple,
we
can
achi
eve
sign
ifica
nt
impr
ovem
ents
!
(a) P
artit
ion
equa
lly a
ccor
ding
to re
fere
nce
orde
r.
(b) P
artit
ion
usin
g m
etho
d in
[8].
(c)
Parti
tion
usin
g al
gorit
hm fo
r spe
ed.
(d
) Par
titio
n us
ing
algo
rithm
for s
pace
.
40
40
40a 1
a 6
a 5a 4B
1 B
2
a 1
a 4
a 2
a 5
a 3
a 6
S
peed
: 234
Spac
e: 4
v 1
v 2v 3
v 4v 5
v 6
v 8v 7
6032
0
3327
27
33
100
a 1
a 2a 4
a 3B
1
B2
a 1
a 2
a 3
a 4
a 6
a 5
S
peed
: 300
Spac
e: 5
v 1
v 2v 3
v 4v 5
v 6
v 8v 7
6032
0
3327
27
33
100
a 1
a 2a 4
a 3
a 1 a 5
40
4040 a 6a 4
BSL
BSL BSL
BSL
BSL
BSL
BSL
BSL
BSL
33a 3
a 1 a 5a 4B
1 B
2
a 1
a 2
a 4
a 3
a 5
a 6
S
peed
: 200
Spac
e: 4
v 1
v 2v 3
v 4v 5
v 6
v 8v 7
6032
0
27
27
33
100
a 1
a 2a 4
40
4040 a 6B
SLB
SL
BSL
BSL
320
a 3a 6
B1
B2
a 1
a 3
a 2
a 4
a 5
a 6
S
peed
: 200
Spac
e: 3
v 1
v 2v 3
v 4v 5
v 6
v 8v 7
60
3327
27
33
100
a 1
a 2a 4
a 1 a 5
40
4040
a 4
BSL
BSL
BSL
11
Out
line
of th
is ta
lkO
utlin
e of
this
talk
Bac
kgro
und
& R
elat
ed w
ork
Wha
t the
pro
blem
is?
Var
iabl
e pa
rtitio
ning
& B
SL
inse
rtion
How
to s
olve
the
prob
lem
?Fo
r spe
edFo
r spa
ce
Exp
erim
enta
l res
ults
12
For S
peed
For S
peed
-- pat
tern
spa
ttern
sN
eed
to c
onsi
der t
he e
xecu
tion
cycl
es o
f ins
erte
d co
nsid
er th
e ex
ecut
ion
cycl
es o
f ins
erte
d B
SLs
BS
Ls.
One
inse
rtion
of B
SL
may
lead
to m
any
exec
utio
ns c
ycle
s in
runt
ime.
Fo
ur b
asic
kin
ds o
f par
ent-c
hild
pat
tern
s
Pat
tern
(a).
One
to o
ne: i
nser
ting
one
BS
L at
thre
e po
sitio
ns a
re th
e sa
me.
Pat
tern
(b).
One
to o
ne w
ith s
elf-l
oops
: ins
ertin
g on
e B
SL
at p
ositi
on ②
or ③
is b
ette
r tha
n ①
. Nev
er in
serti
ng
Nev
er in
serti
ng B
SLs
BSLs
at n
odes
with
sel
fat
nod
es w
ith s
elf -- l
oop
loop
.P
atte
rn (c
). O
ne to
man
y: N
o m
atte
r whi
ch p
ositi
ons
BS
Lsar
e in
serte
d at
, th
ey w
ill be
exe
cute
d in
tota
l
BS
L-cy
cles
.P
atte
rn (d
). M
any
to o
ne: N
o m
atte
r whi
ch p
ositi
ons
BS
Lsar
e in
serte
d at
, the
y w
ill be
exe
cute
d in
tota
l
B
SL-
cycl
es.
Con
clus
ion:
afte
r par
titio
ning
, alw
ays
inse
rting
in
serti
ng B
SLs
BS
Lsat
edg
es w
hen
at e
dges
whe
n ne
eded
need
ed.
∑∈
],2[
1))
,(
(n
ii v
ve
w
[1,
1](
(,
))i
ni
nw
ev
v∈
−∑
13
For S
peed
For S
peed
-- Alg
orith
m(1
)A
lgor
ithm
(1)
An
Acc
essi
ng G
raph
(AG
)A
cces
sing
Gra
ph (A
G)G
’(V’,
E)’
is c
onst
ruct
ed to
pre
sent
the
adja
cent
acce
ssin
g re
latio
nshi
ps b
etw
een
varia
bles
.an
und
irect
ed g
raph
v’: a
nod
e re
pres
ents
a u
niqu
e va
riabl
e e’
(u’,
v’):
an e
dge
repr
esen
ts th
e ad
jace
nt a
cces
sing
rela
tions
hip
betw
een
the
two
varia
bles
u’a
ndv’
. w
’(e’(u
’, v’
)), w
here
((
,))
we
uv
=∑
(,
)&
(((
)'&
()
')||(
()
'&(
)'))
DFG
eu
vE
Au
uA
vv
Au
vA
vu
∈=
==
=
DFG
->A
G
A va
riabl
e
w’(e
’(u’,v
’)) g
ives
the
exec
utio
n tim
es o
f the
inse
rted
BS
L if
u’an
d v’
are
in d
iffer
ent b
anks
a 1
a 2 a 3
a 4
a 5a 6
60 33
3327
40100
4067
14
For S
peed
For S
peed
-- Alg
orith
m(1
)A
lgor
ithm
(1)
The
prob
lem
bec
omes
: we
wan
t to
parti
tion
the
n no
des
into
k p
arts
parti
tion
the
n no
des
into
k p
arts
so th
at th
e si
ze o
f eac
h pa
rt do
es n
ot e
xcee
d m
and
the
tota
l wei
ght o
f th
e cr
oss
edge
s be
twee
n pa
rts a
re m
inim
ized
.
kk --ba
lanc
ed p
artit
ioni
ngba
lanc
ed p
artit
ioni
ngpr
oble
m
prov
ed to
be
an N
PN
P-- H
ard
Har
dpr
oble
mso
me
theo
retic
al w
orks
abo
ut th
is p
robl
em
A p
olyn
omia
l heu
ristic
alg
orith
m: g
reed
y
Com
bine
two
varia
bles
Com
bine
two
varia
bles
who
se c
ombi
natio
n ca
n m
axim
ize
the
spee
d sa
ving
in e
ach
itera
tion.
Th
e co
mpl
exity
is O
(n2
log
n).
B1:
a1,
a4,
a5
B2:
a2,
a3,
a6
a 1
a 2 a 3
a 4
a 5a 6
60 33
3327
40100
4067
15
Out
line
of th
is ta
lkO
utlin
e of
this
talk
Bac
kgro
und
& R
elat
ed w
ork
Wha
t the
pro
blem
is?
Var
iabl
e pa
rtitio
ning
& B
SL
inse
rtion
How
to s
olve
the
prob
lem
?Fo
r spe
edFo
r spa
ce
Exp
erim
enta
l res
ults
16
For S
pace
For S
pace
-- pat
tern
spa
ttern
s
Onl
y ca
re a
bout
the
tota
l num
ber o
f th
e to
tal n
umbe
r of B
SLs
BS
Lsin
serte
din
serte
din
to th
e or
igin
al c
ode
uppe
r bou
nd :
|V|-1
(ins
ertin
g at
ent
ranc
e w
hen
need
ed e
xcep
t roo
t).Fo
ur b
asic
kin
ds o
f par
ent-c
hild
pat
tern
s
Pat
tern
(a):
inse
rting
one
BS
L at
the
thre
e po
sitio
ns a
re th
e sa
me.
P
atte
rn (b
): in
serti
ng o
ne B
SL
at th
e th
ree
posi
tions
are
the
sam
e.P
atte
rn (c
): th
e nu
mbe
r of B
SLs
is a
t mos
t the
num
ber o
f chi
ldre
n. In
serti
ng a
t In
serti
ng a
t th
e ex
it of
the
bran
chin
g pa
rent
the
exit
of th
e br
anch
ing
pare
ntm
ay s
ave
som
e BS
Ls.
Pat
tern
(d):
at m
ost o
ne B
SL n
eeds
to b
e in
serte
d, a
nd in
serti
ng a
t the
in
serti
ng a
t the
en
tranc
e of
the
mer
ging
chi
lden
tranc
e of
the
mer
ging
chi
ld-- n
ode
node
will
alw
ays
be a
n op
timal
sol
utio
n.
Con
clus
ion:
for n
odes
with
mor
e th
an o
ne in
com
ing
or o
utgo
ing
node
s w
ith m
ore
than
one
inco
min
g or
out
goin
g ed
ges
edge
s , fu
rther
redu
ctio
n of
BS
Lsca
n be
ach
ieve
d w
hen
cons
ider
ing
the
inse
rting
pos
ition
s an
d va
riabl
e po
sitio
nsBSL
17
For S
pace
For S
pace
-- diff
icul
ties
diffi
culti
es
Eve
n th
ough
we
know
som
e st
rate
gies
abo
ut B
SL
inse
rtion
on
the
basi
c pa
ttern
s, th
ere
is n
o fix
ed b
est s
trate
gy li
ke w
hen
optim
izin
g fo
r spe
ed.
som
e ba
sic
patte
rns
coul
d in
terv
ene
basi
c pa
ttern
s co
uld
inte
rven
ean
d cr
eate
com
plex
pat
tern
sa
bette
r BS
L in
serti
on p
ositi
on a
lso
depe
nds
on th
e va
riabl
esde
pend
s on
the
varia
bles
’’po
sitio
nspo
sitio
ns
If a3
, a4
and
a5 a
rein
the
sam
e ba
nk,
this
met
hod
is th
e be
st s
olut
ion
But
if y
ou fi
rst
cons
ider
this
pat
tern
(d),
you
may
inse
rt a
BS
L at
th
e en
tranc
e of
v4
at fi
rst
If a3
, a4
and
a5 a
re n
ot in
the
sam
e ba
nk, a
lway
s ne
eds
thre
e B
SLs
.Th
is m
etho
d is
the
one
of
the
best
sol
utio
n
BSL
18
For S
pace
For S
pace
-- alg
orith
mal
gorit
hm
The
spac
e m
inim
izat
ion
prob
lem
is a
lso
NP
NP
-- Har
dH
ard.
Eve
n if
the
varia
bles
hav
e al
read
y be
en p
artit
ione
d in
to b
anks
, the
B
SL
inse
rting
pro
blem
is s
till N
P-H
ard.
We
prop
ose
a he
uris
tic a
lgor
ithm
:S
tep0
: Par
titio
n D
FG in
to p
atte
rns;
Ste
p1: P
artit
ion
varia
bles
usi
ng A
G;
Ste
p2: I
nser
t BS
Lsba
sed
on p
atte
rns.
19
For S
pace
For S
pace
-- alg
orith
m: S
tep
0al
gorit
hm: S
tep
0
Ste
p0. P
artit
ion
DFG
: Alg
orith
m P
CD
FG to
kee
p tra
ck o
f eac
h ba
sic
patte
rn a
nd p
artit
ion
a D
FG in
to b
asic
pat
tern
s.if
one
child
-nod
e of
v h
as in
-deg
ree(
v) >
1 th
en re
turn
FA
LSE
Ret
urn
fals
e
v 2
v 5v 4
v 1v 3
v 2
v 5v 4
v 1
v 3
Ret
urn
fals
e
Ret
urn
fals
e
v 1
v 2v 3
v 4v 5
v 6
v 8v 7
6040
320
3327
40
4027
33
100
a 1
a 2a 4
a 1
a 6
a 5a 4a 3
20
For S
pace
For S
pace
-- alg
orith
m: S
tep
1al
gorit
hm: S
tep
1
Ste
p1. P
artit
ion
varia
bles
: co
nstru
ct A
G G
’(V’,
E’)
for s
pace
Cal
cula
te e
dges
’wei
ghts
w’(e
’(u’,
v’))
:–
1. s
umm
ate
the
num
ber
sum
mat
e th
e nu
mbe
rof e
dges
who
se v
ertic
es a
cces
s u’
and
v’:
–2.
For
pat
tern
(c),
enha
nce
enha
nce
edge
s e’
(A(c
hild
x), A
(chi
ldy)
):w
’(e’(A
(chi
ldx)
, A(c
hild
y)))
+ +
; –
3. F
or p
atte
rn (d
), sl
ack
slac
ked
ges
e’(A
(par
entx
), A
(chi
ld)):
w
’(e’(A
(par
entx
), A
(chi
ld))
--;
–4.
Rem
ove
the
edge
s w
ith w
eigh
t no
bigg
er th
an z
ero
Use
the
prop
osed
alg
orith
m to
par
titio
n va
riabl
es
child
ypare
nt
child
x…
child
i
pare
nty
child
pare
nt i
…
pare
ntx
(,
)&
()
'&(
)'
'('(
','))
1D
FGe
uv
EA
uu
Av
vw
eu
v∈
==
=∑
We
expe
ct m
ore
child
ren
are
inth
e sa
me
bank
It do
esn'
t mat
ter
too
muc
hw
heth
er o
r not
pa
rent
s an
d ch
ildar
e in
the
sam
eba
nk
21
For S
pace
For S
pace
-- alg
orith
m: S
tep
2al
gorit
hm: S
tep
2
Ste
p2. I
nser
t BS
Ls:
base
d on
pat
tern
s
For e
ach
basi
c pa
ttern
For e
ach
basi
c pa
ttern
, gi
ve it
an
optim
al in
serti
on s
olut
ion.
Fo
r pat
tern
(a),
(b) a
nd (d
): in
sert
one
BS
L at
the
entra
nce
of th
e ch
ild-n
ode
if ne
eded
;
For p
atte
rn (c
):w
hile
(var
iabl
es a
cces
sed
by s
ome
child
-nod
es a
re in
the
sam
e ba
nk) d
oIn
sert
one
BS
L at
the
exit
of th
e pa
rent
-nod
e fo
r the
se c
hild
-nod
es if
ne
eded
;en
d w
hile
Inse
rt on
e B
SL
at th
e en
tranc
e of
the
child
-nod
e fo
r eac
h of
the
othe
r chi
ld-
node
s if
need
ed;
For t
he o
ther
kin
ds o
f pat
tern
sFo
r the
oth
er k
inds
of p
atte
rns,
BS
Lsar
e al
way
s in
serte
d at
the
entra
nce
of th
e ch
ild-n
ode.
vBS
L
u
yx
BS
L
BS
L
xy
22
Out
line
of th
is ta
lkO
utlin
e of
this
talk
Bac
kgro
und
& R
elat
ed w
ork
Wha
t the
pro
blem
is?
Var
iabl
e pa
rtitio
ning
& B
SL
inse
rtion
How
to s
olve
the
prob
lem
?Fo
r spe
edFo
r spa
ce
Exp
erim
enta
l res
ults
23
Expe
rimen
tsEx
perim
ents
-- ben
chm
arks
benc
hmar
ks
A fo
urfo
ur-- b
anks
ba
nks
arch
itect
ure
is u
sed
for b
ench
mar
ks w
ith v
aria
bles
no
mor
e th
an 3
0A
nei
ght
eigh
t -- ban
ksba
nks
arch
itect
ure
for t
he o
ther
s.
24
Expe
rimen
tsEx
perim
ents
-- res
ults
re
sults
for s
peed
for s
peed
The
parti
tioni
ng te
chni
ques
und
er c
ompa
rison
are
:
(a) e
qual
lyeq
ually
parti
tioni
ng a
ccor
ding
to re
fere
nce
orde
r,
(b) a
par
alle
lpa
ralle
lpar
titio
ning
met
hod
[8],
(c) e
qual
ly p
artit
ioni
ng w
ith s
hare
dsh
ared
-- ban
k ba
nk a
djus
tmen
t [6]
, (d
) the
pro
pose
d al
gorit
hm fo
r spe
ed.
This
met
hod
offe
rs th
e w
orst
solu
tions
This
met
hod
achi
eves
2-
16%
ove
rhea
dre
duct
ion
Our
met
hod
achi
eves
19-
29%
over
head
redu
ctio
n
25
Expe
rimen
tsEx
perim
ents
-- res
ults
re
sults
for s
pace
for s
pace
For s
pace
, diff
eren
t BS
L pl
acem
ent m
etho
ds a
re a
lso
com
pare
d,
beca
use
they
als
o af
fect
the
solu
tions
. B
SL
P
art
Par
titio
ning
(a)
Par
titio
ning
(b)
Par
titio
ning
(c)
AG
Opt
[2][3
]Ba
sis
Par
Alg
[8]
&O
ptB
SL
Sha
redA
lg[6
]&
Opt
BS
LV
PA
B&
Opt
BS
L
Our
sV
PA
B&
BIA
Spa
ceTh
is m
etho
dof
fers
the
wor
stso
lutio
ns
This
met
hod
achi
eves
2-
10%
ove
rhea
dre
duct
ion
Eve
n co
mbi
ned
with
the
optim
al B
SL
plac
emen
t, th
e ot
her
parti
tioni
ng a
lgor
ithm
sst
ill ca
nnot
obt
ain
bette
r res
ults
than
the
prop
osed
alg
orith
m
can
obta
in th
ebe
st s
olut
ions
for s
ome
case
s
Onl
y 2%
wor
seth
an th
e op
timal
solu
tions
.
26
Con
clus
ion
Con
clus
ion
Arc
hite
ctur
e: 88
-- bit
mic
robi
t mic
ro-- c
ontro
llers
cont
rolle
rs&
par
titio
ned
bank
s &
ban
k &
par
titio
ned
bank
s &
ban
k sw
itchi
ngsw
itchi
ng
Obj
ectiv
e: m
inim
ize
the
size
and
tim
e ov
erhe
ads
over
head
sin
trodu
ced
by B
SLs
Thro
ugh:
opt
imiz
ing
the
varia
ble
parti
tioni
ngva
riabl
e pa
rtitio
ning
in d
iffer
ent b
anks
and
elab
orat
ely
plac
ing
plac
ing
BS
LsB
SLs
in p
rogr
ams.
NP
-Har
d pr
oble
ms
Diff
eren
t pos
ition
s to
inse
rt B
SLs
Diff
eren
t pat
tern
s
Heu
ristic
alg
orith
ms
are
prop
osed
.
Futu
re w
ork
Com
bini
ng m
ultip
le o
bjec
tives
Spe
cial
cas
es: o
ptim
al s
olut
ions
Than
ks!
Than
ks!
Q &
AQ
& A