KL27 Sub-Family Reference Manual - NXP …€¦ · KL27 Sub-Family Reference Manual Supports: MKL27Z128VFM4, MKL27Z256VFM4, MKL27Z128VFT4, MKL27Z256VFT4, MKL27Z128VMP4, MKL27Z256VMP4,

KL27 Sub-Family Reference ManualSupports: MKL27Z128VFM4, MKL27Z256VFM4, MKL27Z128VFT4,

MKL27Z256VFT4, MKL27Z128VMP4, MKL27Z256VMP4,MKL27Z128VLH4, MKL27Z256VLH4

Document Number: KL27P64M48SF6RMRev. 5.1, 07/2016

KL27 Sub-Family Reference Manual, Rev. 5.1, 07/2016

2 NXP Semiconductors

Contents

Section number Title Page

Chapter 1About This Document

1.1 Overview.......................................................................................................................................................................39

1.1.1 Purpose...........................................................................................................................................................39

1.1.2 Audience........................................................................................................................................................ 39

1.2 Conventions.................................................................................................................................................................. 39

1.2.1 Numbering systems........................................................................................................................................39

1.2.2 Typographic notation..................................................................................................................................... 40

1.2.3 Special terms.................................................................................................................................................. 40

Chapter 2Introduction

2.1 Overview.......................................................................................................................................................................41

2.1.1 Sub-family introduction................................................................................................................................. 41

2.2 Module functional categories........................................................................................................................................42

2.2.1 ARM Cortex-M0+ core modules................................................................................................................... 43

2.2.2 System modules............................................................................................................................................. 43

2.2.3 Memories and memory interfaces..................................................................................................................44

2.2.4 Clocks.............................................................................................................................................................44

2.2.5 Security and integrity modules...................................................................................................................... 45

2.2.6 Analog modules............................................................................................................................................. 45

2.2.7 Timer modules............................................................................................................................................... 45

2.2.8 Communication interfaces............................................................................................................................. 46

2.2.9 Human-machine interfaces............................................................................................................................ 47

2.3 Module to module interconnects...................................................................................................................................47

2.3.1 Interconnection overview...............................................................................................................................47

2.3.2 Analog reference options............................................................................................................................... 49

Chapter 3Core Overview


NXP Semiconductors 3


3.1 ARM Cortex-M0+ core introduction............................................................................................................................51

3.1.1 Buses, interconnects, and interfaces.............................................................................................................. 51

3.1.2 System tick timer........................................................................................................................................... 51

3.1.3 Debug facilities.............................................................................................................................................. 51

3.1.4 Core privilege levels...................................................................................................................................... 52

3.2 Nested vectored interrupt controller (NVIC) ...............................................................................................................52

3.2.1 Interrupt priority levels.................................................................................................................................. 52

3.2.2 Non-maskable interrupt..................................................................................................................................52

3.2.3 Interrupt channel assignments........................................................................................................................52

3.3 AWIC introduction....................................................................................................................................................... 55

3.3.1 Wake-up sources............................................................................................................................................ 55

Chapter 4Memory Map

4.1 Introduction...................................................................................................................................................................57

4.2 Flash memory............................................................................................................................................................... 57

4.2.1 Flash memory map.........................................................................................................................................57

4.2.2 Flash security................................................................................................................................................. 58

4.2.3 Flash modes....................................................................................................................................................58

4.2.4 Erase all flash contents...................................................................................................................................58

4.2.5 FTFA_FOPT register..................................................................................................................................... 59

4.3 SRAM........................................................................................................................................................................... 59

4.3.1 SRAM sizes....................................................................................................................................................59

4.3.2 SRAM ranges.................................................................................................................................................59

4.3.3 SRAM retention in low power modes............................................................................................................60

4.4 System Register file...................................................................................................................................................... 60

4.5 System memory map.....................................................................................................................................................61

4.6 Bit Manipulation Engine...............................................................................................................................................62

4.7 Peripheral bridge (AIPS-Lite) memory map.................................................................................................................62

4.7.1 Read-after-write sequence and required serialization of memory operations................................................62




4.7.2 Peripheral bridge (AIPS-Lite) memory map..................................................................................................63

Chapter 5Clock Distribution

5.1 Introduction...................................................................................................................................................................67

5.2 Programming model......................................................................................................................................................67

5.3 High-level device clocking diagram............................................................................................................................. 67

5.4 Clock definitions...........................................................................................................................................................68

5.4.1 Device clock summary...................................................................................................................................69

5.5 Internal clocking requirements..................................................................................................................................... 71

5.5.1 Clock divider values after reset......................................................................................................................72

5.5.2 VLPR mode clocking.....................................................................................................................................72

5.6 Clock gating..................................................................................................................................................................73

5.7 Module clocks...............................................................................................................................................................73

5.7.1 PMC 1-kHz LPO clock.................................................................................................................................. 74

5.7.2 COP clocking................................................................................................................................................. 74

5.7.3 RTC clocking................................................................................................................................................. 75

5.7.4 RTC_CLKOUT and CLKOUT32K clocking................................................................................................ 75

5.7.5 LPTMR clocking............................................................................................................................................76

5.7.6 TPM clocking.................................................................................................................................................77

5.7.7 USB FS device only controller clocking........................................................................................................77

5.7.8 LPUART clocking......................................................................................................................................... 78

5.7.9 FlexIO clocking..............................................................................................................................................79

5.7.10 I2S/SAI clocking............................................................................................................................................80

Chapter 6Reset and Boot

6.1 Introduction...................................................................................................................................................................81

6.2 Reset..............................................................................................................................................................................81

6.2.1 Power-on reset (POR).................................................................................................................................... 82

6.2.2 System reset sources...................................................................................................................................... 82




6.2.3 MCU resets.................................................................................................................................................... 85

6.2.4 RESET pin .................................................................................................................................................... 86

6.3 Boot...............................................................................................................................................................................86

6.3.1 Boot sources...................................................................................................................................................87

6.3.2 FOPT boot options......................................................................................................................................... 87

6.3.3 Boot sequence................................................................................................................................................ 89

Chapter 7Power Management

7.1 Introduction...................................................................................................................................................................91

7.2 Clocking modes............................................................................................................................................................ 91

7.2.1 Partial Stop.....................................................................................................................................................91

7.2.2 DMA Wakeup................................................................................................................................................ 92

7.2.3 Compute Operation........................................................................................................................................ 93

7.2.4 Peripheral Doze..............................................................................................................................................94

7.2.5 Clock gating................................................................................................................................................... 95

7.3 Power modes.................................................................................................................................................................95

7.4 Entering and exiting power modes............................................................................................................................... 97

7.5 Module operation in low-power modes........................................................................................................................ 98

Chapter 8Security

8.1 Introduction...................................................................................................................................................................103

8.1.1 Flash security................................................................................................................................................. 103

8.1.2 Security interactions with other modules.......................................................................................................103

Chapter 9Debug

9.1 Introduction...................................................................................................................................................................105

9.2 Debug port pin descriptions..........................................................................................................................................105

9.3 SWD status and control registers..................................................................................................................................106

9.3.1 MDM-AP Control Register............................................................................................................................107

9.3.2 MDM-AP Status Register.............................................................................................................................. 108




9.4 Debug resets..................................................................................................................................................................110

9.5 Micro Trace Buffer (MTB)...........................................................................................................................................110

9.6 Debug in low-power modes.......................................................................................................................................... 111

9.7 Debug and security....................................................................................................................................................... 112

Chapter 10Pinouts and Packaging

10.1 Introduction...................................................................................................................................................................113

10.2 Signal multiplexing integration.................................................................................................................................... 113

10.2.1 Clock gating................................................................................................................................................... 114

10.2.2 Signal multiplexing constraints......................................................................................................................114

10.3 KL27 Signal Multiplexing and Pin Assignments......................................................................................................... 114

10.4 KL27 Family Pinouts....................................................................................................................................................117

10.5 Module Signal Description Tables................................................................................................................................120

10.5.1 Core modules................................................................................................................................................. 120

10.5.2 System modules............................................................................................................................................. 120

10.5.3 Clock modules................................................................................................................................................121

10.5.4 Analog............................................................................................................................................................121

10.5.5 Timer Modules...............................................................................................................................................122

10.5.6 Communication interfaces............................................................................................................................. 123

10.5.7 Human-machine interfaces (HMI)................................................................................................................. 126

Chapter 11Port Control and Interrupts (PORT)

11.1 Chip-specific PORT information..................................................................................................................................127

11.2 Port control and interrupt summary.............................................................................................................................. 128

11.3 Introduction...................................................................................................................................................................129

11.4 Overview.......................................................................................................................................................................129

11.4.1 Features.......................................................................................................................................................... 129

11.4.2 Modes of operation........................................................................................................................................ 130

11.5 External signal description............................................................................................................................................131




11.6 Detailed signal description............................................................................................................................................131

11.7 Memory map and register definition.............................................................................................................................131

11.7.1 Pin Control Register n (PORTx_PCRn).........................................................................................................137

11.7.2 Global Pin Control Low Register (PORTx_GPCLR).................................................................................... 140

11.7.3 Global Pin Control High Register (PORTx_GPCHR)...................................................................................140

11.7.4 Interrupt Status Flag Register (PORTx_ISFR).............................................................................................. 141

11.8 Functional description...................................................................................................................................................141

11.8.1 Pin control...................................................................................................................................................... 141

11.8.2 Global pin control.......................................................................................................................................... 142

11.8.3 External interrupts..........................................................................................................................................142

Chapter 12System Integration Module (SIM)

12.1 Chip-specific SIM information.....................................................................................................................................145

12.1.1 COP clocks.....................................................................................................................................................145

12.2 Introduction...................................................................................................................................................................145

12.2.1 Features.......................................................................................................................................................... 145


12.3.1 System Options Register 1 (SIM_SOPT1).................................................................................................... 147

12.3.2 SOPT1 Configuration Register (SIM_SOPT1CFG)......................................................................................148





12.3.7 System Device Identification Register (SIM_SDID).....................................................................................156

12.3.8 System Clock Gating Control Register 4 (SIM_SCGC4)..............................................................................158




12.3.12 System Clock Divider Register 1 (SIM_CLKDIV1).....................................................................................164




12.3.13 Flash Configuration Register 1 (SIM_FCFG1)............................................................................................. 166

12.3.14 Flash Configuration Register 2 (SIM_FCFG2)............................................................................................. 167

12.3.15 Unique Identification Register Mid-High (SIM_UIDMH)............................................................................168

12.3.16 Unique Identification Register Mid Low (SIM_UIDML)............................................................................. 169

12.3.17 Unique Identification Register Low (SIM_UIDL)........................................................................................ 169

12.3.18 COP Control Register (SIM_COPC)............................................................................................................. 170

12.3.19 Service COP (SIM_SRVCOP).......................................................................................................................171


12.4.1 COP watchdog operation............................................................................................................................... 172

Chapter 13Kinetis ROM Bootloader

13.1 Chip-Specific Information............................................................................................................................................ 175

13.2 Introduction...................................................................................................................................................................175

13.3 Functional Description..................................................................................................................................................177

13.3.1 Memory Maps................................................................................................................................................ 177

13.3.2 The Kinetis Bootloader Configuration Area (BCA)...................................................................................... 178

13.3.3 Start-up Process..............................................................................................................................................179

13.3.4 Clock Configuration.......................................................................................................................................181

13.3.5 Bootloader Entry Point...................................................................................................................................182

13.3.6 Bootloader Protocol....................................................................................................................................... 183

13.3.7 Bootloader Packet Types............................................................................................................................... 188

13.3.8 Bootloader Command API.............................................................................................................................195

13.3.9 Bootloader Exit state......................................................................................................................................210

13.4 Peripherals Supported................................................................................................................................................... 211

13.4.1 I2C Peripheral................................................................................................................................................ 211

13.4.2 SPI Peripheral................................................................................................................................................ 213

13.4.3 USB peripheral...............................................................................................................................................215

13.5 Get/SetProperty Command Properties..........................................................................................................................219

13.5.1 Property Definitions.......................................................................................................................................220




13.6 Kinetis Bootloader Status Error Codes.........................................................................................................................222

13.7 Bootloader errata...........................................................................................................................................................223

Chapter 14System Mode Controller (SMC)

14.1 Chip-specific SMC information....................................................................................................................................225

14.2 Introduction...................................................................................................................................................................225

14.3 Modes of operation....................................................................................................................................................... 225

14.4 Memory map and register descriptions.........................................................................................................................227

14.4.1 Power Mode Protection register (SMC_PMPROT).......................................................................................228

14.4.2 Power Mode Control register (SMC_PMCTRL)...........................................................................................229

14.4.3 Stop Control Register (SMC_STOPCTRL)...................................................................................................230

14.4.4 Power Mode Status register (SMC_PMSTAT)............................................................................................. 232


14.5.1 Power mode transitions..................................................................................................................................232

14.5.2 Power mode entry/exit sequencing................................................................................................................ 235

14.5.3 Run modes......................................................................................................................................................236

14.5.4 Wait modes.................................................................................................................................................... 238

14.5.5 Stop modes.....................................................................................................................................................239

14.5.6 Debug in low power modes........................................................................................................................... 242

Chapter 15Power Management Controller (PMC)

15.1 Introduction...................................................................................................................................................................243

15.2 Features.........................................................................................................................................................................243

15.3 Low-voltage detect (LVD) system................................................................................................................................243

15.3.1 LVD reset operation.......................................................................................................................................244

15.3.2 LVD interrupt operation.................................................................................................................................244

15.3.3 Low-voltage warning (LVW) interrupt operation......................................................................................... 244

15.4 I/O retention..................................................................................................................................................................245

15.5 Memory map and register descriptions.........................................................................................................................245




15.5.1 Low Voltage Detect Status And Control 1 register (PMC_LVDSC1).......................................................... 246

15.5.2 Low Voltage Detect Status And Control 2 register (PMC_LVDSC2).......................................................... 247

15.5.3 Regulator Status And Control register (PMC_REGSC)................................................................................ 248

Chapter 16Miscellaneous Control Module (MCM)

16.1 Introduction...................................................................................................................................................................251

16.1.1 Features.......................................................................................................................................................... 251

16.2 Memory map/register descriptions............................................................................................................................... 251

16.2.1 Crossbar Switch (AXBS) Slave Configuration (MCM_PLASC)..................................................................252

16.2.2 Crossbar Switch (AXBS) Master Configuration (MCM_PLAMC).............................................................. 252

16.2.3 Platform Control Register (MCM_PLACR)..................................................................................................253

16.2.4 Compute Operation Control Register (MCM_CPO)..................................................................................... 256

Chapter 17Crossbar Switch Lite (AXBS-Lite)

17.1 Chip-specific AXBS-Lite information..........................................................................................................................259

17.1.1 Crossbar-light switch master assignments..................................................................................................... 259

17.1.2 Crossbar switch slave assignments................................................................................................................ 259

17.2 Introduction...................................................................................................................................................................259

17.2.1 Features.......................................................................................................................................................... 260

17.3 Memory Map / Register Definition...............................................................................................................................260


17.4.1 General operation...........................................................................................................................................260

17.4.2 Arbitration......................................................................................................................................................261

17.5 Initialization/application information........................................................................................................................... 263

Chapter 18Low-Leakage Wakeup Unit (LLWU)

18.1 LLWU interrupt............................................................................................................................................................ 265

18.1.1 Wake-up Sources........................................................................................................................................... 265

18.2 Introduction...................................................................................................................................................................266

18.2.1 Features.......................................................................................................................................................... 266





18.2.3 Block diagram................................................................................................................................................ 268

18.3 LLWU signal descriptions............................................................................................................................................ 269

18.4 Memory map/register definition................................................................................................................................... 269

18.4.1 LLWU Pin Enable 1 register (LLWU_PE1)..................................................................................................270




18.4.5 LLWU Module Enable register (LLWU_ME).............................................................................................. 274

18.4.6 LLWU Flag 1 register (LLWU_F1)...............................................................................................................276



18.4.9 LLWU Pin Filter 1 register (LLWU_FILT1)................................................................................................ 281

18.4.10 LLWU Pin Filter 2 register (LLWU_FILT2)................................................................................................ 282


18.5.1 LLS mode.......................................................................................................................................................284

18.5.2 VLLS modes.................................................................................................................................................. 284

18.5.3 Initialization................................................................................................................................................... 284

Chapter 19Peripheral Bridge (AIPS-Lite)

19.1 Chip-specific AIPS-Lite information............................................................................................................................285

19.1.1 Number of peripheral bridges........................................................................................................................ 285

19.1.2 Memory maps................................................................................................................................................ 285

19.2 Introduction...................................................................................................................................................................285

19.2.1 Features.......................................................................................................................................................... 285



19.3.1 Master Privilege Register A (AIPS_MPRA)................................................................................................. 286

19.3.2 Peripheral Access Control Register (AIPS_PACRn).....................................................................................288




19.3.3 Peripheral Access Control Register (AIPS_n)............................................................................................... 0


19.4.1 Access support............................................................................................................................................... 293

Chapter 20Direct Memory Access Multiplexer (DMAMUX)

20.1 Chip-specific DMAMUX information......................................................................................................................... 295

20.1.1 DMA MUX Request Sources........................................................................................................................ 295

20.1.2 DMA transfers via PIT trigger....................................................................................................................... 297

20.2 Introduction...................................................................................................................................................................297

20.2.1 Overview........................................................................................................................................................297

20.2.2 Features.......................................................................................................................................................... 298


20.3 External signal description............................................................................................................................................299


20.4.1 Channel Configuration register (DMAMUXx_CHCFGn)............................................................................ 299


20.5.1 DMA channels with periodic triggering capability........................................................................................301

20.5.2 DMA channels with no triggering capability.................................................................................................303

20.5.3 Always-enabled DMA sources...................................................................................................................... 303

20.6 Initialization/application information........................................................................................................................... 305

20.6.1 Reset...............................................................................................................................................................305

20.6.2 Enabling and configuring sources..................................................................................................................305

Chapter 21DMA Controller Module

21.1 Introduction...................................................................................................................................................................309

21.1.1 Overview........................................................................................................................................................309

21.1.2 Features.......................................................................................................................................................... 310

21.2 DMA Transfer Overview..............................................................................................................................................311

21.3 Memory Map/Register Definition.................................................................................................................................312




21.3.1 Source Address Register (DMA_SARn)....................................................................................................... 313

21.3.2 Destination Address Register (DMA_DARn)............................................................................................... 314

21.3.3 DMA Status Register / Byte Count Register (DMA_DSR_BCRn)...............................................................315

21.3.4 DMA Control Register (DMA_DCRn)..........................................................................................................317


21.4.1 Transfer requests (Cycle-Steal and Continuous modes)................................................................................ 321

21.4.2 Channel initialization and startup.................................................................................................................. 322

21.4.3 Dual-Address Data Transfer Mode................................................................................................................ 323

21.4.4 Advanced Data Transfer Controls: Auto-Alignment..................................................................................... 324

21.4.5 Termination....................................................................................................................................................325

Chapter 22Reset Control Module (RCM)

22.1 Introduction...................................................................................................................................................................327

22.2 Reset memory map and register descriptions............................................................................................................... 327

22.2.1 System Reset Status Register 0 (RCM_SRS0).............................................................................................. 328

22.2.2 System Reset Status Register 1 (RCM_SRS1).............................................................................................. 329

22.2.3 Reset Pin Filter Control register (RCM_RPFC)............................................................................................ 330

22.2.4 Reset Pin Filter Width register (RCM_RPFW)............................................................................................. 331

22.2.5 Force Mode Register (RCM_FM)..................................................................................................................333

22.2.6 Mode Register (RCM_MR)........................................................................................................................... 333

22.2.7 Sticky System Reset Status Register 0 (RCM_SSRS0).................................................................................334

22.2.8 Sticky System Reset Status Register 1 (RCM_SSRS1).................................................................................335

Chapter 23Analog-to-Digital Converter (ADC)

23.1 Chip-specific ADC information....................................................................................................................................337

23.1.1 ADC instantiation information.......................................................................................................................337

23.1.2 DMA Support on ADC.................................................................................................................................. 337

23.1.3 ADC0 connections/channel assignment.........................................................................................................338

23.1.4 ADC analog supply and reference connections............................................................................................. 339




23.1.5 Alternate clock............................................................................................................................................... 339

23.2 Introduction...................................................................................................................................................................340

23.2.1 Features.......................................................................................................................................................... 340

23.2.2 Block diagram................................................................................................................................................ 341

23.3 ADC signal descriptions............................................................................................................................................... 342

23.3.1 Analog Power (VDDA)................................................................................................................................. 342

23.3.2 Analog Ground (VSSA).................................................................................................................................342

23.3.3 Voltage Reference Select............................................................................................................................... 342

23.3.4 Analog Channel Inputs (ADx)....................................................................................................................... 343

23.3.5 Differential Analog Channel Inputs (DADx).................................................................................................343

23.4 Memory map and register definitions........................................................................................................................... 343

23.4.1 ADC Status and Control Registers 1 (ADCx_SC1n).....................................................................................345

23.4.2 ADC Configuration Register 1 (ADCx_CFG1).............................................................................................348

23.4.3 ADC Configuration Register 2 (ADCx_CFG2).............................................................................................349

23.4.4 ADC Data Result Register (ADCx_Rn).........................................................................................................350

23.4.5 Compare Value Registers (ADCx_CVn)....................................................................................................... 352

23.4.6 Status and Control Register 2 (ADCx_SC2)..................................................................................................353

23.4.7 Status and Control Register 3 (ADCx_SC3)..................................................................................................355

23.4.8 ADC Offset Correction Register (ADCx_OFS).............................................................................................356

23.4.9 ADC Plus-Side Gain Register (ADCx_PG)...................................................................................................357

23.4.10 ADC Minus-Side Gain Register (ADCx_MG).............................................................................................. 357

23.4.11 ADC Plus-Side General Calibration Value Register (ADCx_CLPD)........................................................... 358

23.4.12 ADC Plus-Side General Calibration Value Register (ADCx_CLPS)............................................................359

23.4.13 ADC Plus-Side General Calibration Value Register (ADCx_CLP4)............................................................ 359





23.4.18 ADC Minus-Side General Calibration Value Register (ADCx_CLMD).......................................................362




23.4.19 ADC Minus-Side General Calibration Value Register (ADCx_CLMS)....................................................... 362

23.4.20 ADC Minus-Side General Calibration Value Register (ADCx_CLM4)....................................................... 363






23.5.1 Clock select and divide control......................................................................................................................366

23.5.2 Voltage reference selection............................................................................................................................367

23.5.3 Hardware trigger and channel selects............................................................................................................ 367

23.5.4 Conversion control.........................................................................................................................................368

23.5.5 Automatic compare function..........................................................................................................................376

23.5.6 Calibration function....................................................................................................................................... 377

23.5.7 User-defined offset function.......................................................................................................................... 379

23.5.8 Temperature sensor........................................................................................................................................ 380

23.5.9 MCU wait mode operation.............................................................................................................................381

23.5.10 MCU Normal Stop mode operation............................................................................................................... 381

23.5.11 MCU Low-Power Stop mode operation........................................................................................................ 382

23.6 Initialization information.............................................................................................................................................. 383

23.6.1 ADC module initialization example.............................................................................................................. 383

23.7 Application information................................................................................................................................................385

23.7.1 External pins and routing............................................................................................................................... 385

23.7.2 Sources of error..............................................................................................................................................387

Chapter 24Comparator (CMP)

24.1 Chip-specific CMP information....................................................................................................................................393

24.1.1 CMP instantiation information.......................................................................................................................393

24.1.2 CMP input connections..................................................................................................................................393

24.1.3 CMP external references................................................................................................................................394




24.1.4 CMP trigger mode..........................................................................................................................................394

24.2 Introduction...................................................................................................................................................................395

24.2.1 CMP features..................................................................................................................................................395

24.2.2 6-bit DAC key features.................................................................................................................................. 396

24.2.3 ANMUX key features.................................................................................................................................... 396

24.2.4 CMP, DAC and ANMUX diagram................................................................................................................396

24.2.5 CMP block diagram....................................................................................................................................... 397

24.3 Memory map/register definitions..................................................................................................................................399

24.3.1 CMP Control Register 0 (CMPx_CR0)......................................................................................................... 399

24.3.2 CMP Control Register 1 (CMPx_CR1)......................................................................................................... 400

24.3.3 CMP Filter Period Register (CMPx_FPR).....................................................................................................401

24.3.4 CMP Status and Control Register (CMPx_SCR)...........................................................................................402

24.3.5 DAC Control Register (CMPx_DACCR)...................................................................................................... 403

24.3.6 MUX Control Register (CMPx_MUXCR).................................................................................................... 403


24.4.1 CMP functional modes...................................................................................................................................405

24.4.2 Power modes.................................................................................................................................................. 408

24.4.3 Startup and operation..................................................................................................................................... 409

24.4.4 Low-pass filter............................................................................................................................................... 410

24.5 CMP interrupts..............................................................................................................................................................412

24.6 DMA support................................................................................................................................................................ 412

24.7 CMP Asynchronous DMA support...............................................................................................................................412

24.8 Digital-to-analog converter...........................................................................................................................................413

24.9 DAC functional description.......................................................................................................................................... 413

24.9.1 Voltage reference source select......................................................................................................................413

24.10 DAC resets....................................................................................................................................................................414

24.11 DAC clocks...................................................................................................................................................................414

24.12 DAC interrupts..............................................................................................................................................................414

24.13 CMP Trigger Mode.......................................................................................................................................................414




Chapter 2512-bit Digital-to-Analog Converter (DAC)

25.1 Introduction...................................................................................................................................................................415

25.2 Features.........................................................................................................................................................................415

25.3 Block diagram...............................................................................................................................................................415


25.4.1 DAC Data Low Register (DACx_DATnL)................................................................................................... 417

25.4.2 DAC Data High Register (DACx_DATnH).................................................................................................. 417

25.4.3 DAC Status Register (DACx_SR)................................................................................................................. 418

25.4.4 DAC Control Register (DACx_C0)............................................................................................................... 419

25.4.5 DAC Control Register 1 (DACx_C1)............................................................................................................ 420

25.4.6 DAC Control Register 2 (DACx_C2)............................................................................................................ 420


25.5.1 DAC data buffer operation.............................................................................................................................421

25.5.2 DMA operation.............................................................................................................................................. 423

25.5.3 Resets............................................................................................................................................................. 423

25.5.4 Low-Power mode operation...........................................................................................................................423

Chapter 26Voltage Reference (VREFV1)

26.1 Introduction...................................................................................................................................................................425

26.1.1 Overview........................................................................................................................................................426

26.1.2 Features.......................................................................................................................................................... 426

26.1.3 Modes of Operation....................................................................................................................................... 426

26.1.4 VREF Signal Descriptions............................................................................................................................. 427

26.2 Memory Map and Register Definition..........................................................................................................................427

26.2.1 VREF Trim Register (VREF_TRM)..............................................................................................................428

26.2.2 VREF Status and Control Register (VREF_SC)............................................................................................429


26.3.1 Voltage Reference Disabled, SC[VREFEN] = 0........................................................................................... 430




26.3.2 Voltage Reference Enabled, SC[VREFEN] = 1............................................................................................ 430

26.4 Internal voltage regulator..............................................................................................................................................432

26.5 Initialization/Application Information..........................................................................................................................432

Chapter 27Multipurpose Clock Generator Lite (MCG_Lite)

27.1 Introduction ..................................................................................................................................................................435

27.1.1 Features ......................................................................................................................................................... 435

27.1.2 Block diagram ............................................................................................................................................... 436


27.2.1 MCG Control Register 1 (MCG_C1).............................................................................................................437

27.2.2 MCG Control Register 2 (MCG_C2).............................................................................................................438

27.2.3 MCG Status Register (MCG_S).................................................................................................................... 439

27.2.4 MCG Status and Control Register (MCG_SC)..............................................................................................439

27.2.5 MCG Miscellaneous Control Register (MCG_MC)......................................................................................440


27.3.1 Clock mode switching ...................................................................................................................................441

27.3.2 LIRC divider 1 .............................................................................................................................................. 442

27.3.3 LIRC divider 2 .............................................................................................................................................. 442

27.3.4 Enable LIRC in Stop mode ........................................................................................................................... 442

27.3.5 MCG-Lite in Low-power mode .................................................................................................................... 442

27.3.6 HIRC USB recovery ..................................................................................................................................... 443

Chapter 28Oscillator (OSC)

28.1 Chip-specific OSC information.................................................................................................................................... 445

28.1.1 OSC modes of operation with MCG_Lite and RTC......................................................................................445

28.2 Introduction...................................................................................................................................................................445

28.3 Features and Modes...................................................................................................................................................... 445

28.4 Block Diagram..............................................................................................................................................................446

28.5 OSC Signal Descriptions.............................................................................................................................................. 447




28.6 External Crystal / Resonator Connections.................................................................................................................... 447

28.7 External Clock Connections......................................................................................................................................... 449

28.8 Memory Map/Register Definitions...............................................................................................................................449

28.8.1 OSC Memory Map/Register Definition.........................................................................................................450


28.9.1 OSC module states......................................................................................................................................... 451

28.9.2 OSC module modes....................................................................................................................................... 453

28.9.3 Counter...........................................................................................................................................................455

28.9.4 Reference clock pin requirements..................................................................................................................455

28.10 Reset..............................................................................................................................................................................455

28.11 Low power modes operation.........................................................................................................................................456

28.12 Interrupts.......................................................................................................................................................................456

Chapter 29Timer/PWM Module (TPM)

29.1 Chip-specific TPM information....................................................................................................................................457

29.1.1 TPM instantiation information.......................................................................................................................457

29.1.2 Clock options................................................................................................................................................. 458

29.1.3 Trigger options...............................................................................................................................................458

29.1.4 Global timebase..............................................................................................................................................459

29.1.5 TPM interrupts............................................................................................................................................... 459

29.2 Introduction...................................................................................................................................................................460

29.2.1 TPM Philosophy............................................................................................................................................ 460

29.2.2 Features.......................................................................................................................................................... 460


29.2.4 Block diagram................................................................................................................................................ 461

29.3 TPM Signal Descriptions..............................................................................................................................................462

29.3.1 TPM_EXTCLK TPM External Clock...................................................................................................... 462

29.3.2 TPM_CHn TPM Channel (n) I/O Pin....................................................................................................... 463

29.4 Memory Map and Register Definition..........................................................................................................................463




29.4.1 Status and Control (TPMx_SC)..................................................................................................................... 465

29.4.2 Counter (TPMx_CNT)................................................................................................................................... 466

29.4.3 Modulo (TPMx_MOD).................................................................................................................................. 467

29.4.4 Channel (n) Status and Control (TPMx_CnSC).............................................................................................468

29.4.5 Channel (n) Value (TPMx_CnV)...................................................................................................................470

29.4.6 Capture and Compare Status (TPMx_STATUS)........................................................................................... 470

29.4.7 Channel Polarity (TPMx_POL)..................................................................................................................... 472

29.4.8 Configuration (TPMx_CONF).......................................................................................................................473


29.5.1 Clock domains................................................................................................................................................476

29.5.2 Prescaler......................................................................................................................................................... 477

29.5.3 Counter...........................................................................................................................................................477

29.5.4 Input Capture Mode....................................................................................................................................... 480

29.5.5 Output Compare Mode...................................................................................................................................481

29.5.6 Edge-Aligned PWM (EPWM) Mode.............................................................................................................482

29.5.7 Center-Aligned PWM (CPWM) Mode.......................................................................................................... 484

29.5.8 Registers Updated from Write Buffers.......................................................................................................... 486

29.5.9 DMA.............................................................................................................................................................. 486

29.5.10 Output triggers............................................................................................................................................... 487

29.5.11 Reset Overview.............................................................................................................................................. 487

29.5.12 TPM Interrupts...............................................................................................................................................488

Chapter 30Periodic Interrupt Timer (PIT)

30.1 Chip-specific PIT information...................................................................................................................................... 489

30.1.1 PIT/DMA periodic trigger assignments ........................................................................................................489

30.1.2 PIT/ADC triggers...........................................................................................................................................489

30.1.3 PIT/TPM triggers........................................................................................................................................... 489

30.1.4 PIT/DAC triggers...........................................................................................................................................489

30.2 Introduction...................................................................................................................................................................490




30.2.1 Block diagram................................................................................................................................................ 490

30.2.2 Features.......................................................................................................................................................... 490

30.3 Signal description..........................................................................................................................................................491

30.4 Memory map/register description................................................................................................................................. 491

30.4.1 PIT Module Control Register (PIT_MCR).................................................................................................... 492

30.4.2 PIT Upper Lifetime Timer Register (PIT_LTMR64H)................................................................................. 493

30.4.3 PIT Lower Lifetime Timer Register (PIT_LTMR64L)................................................................................. 493

30.4.4 Timer Load Value Register (PIT_LDVALn).................................................................................................494

30.4.5 Current Timer Value Register (PIT_CVALn)............................................................................................... 494

30.4.6 Timer Control Register (PIT_TCTRLn)........................................................................................................ 495

30.4.7 Timer Flag Register (PIT_TFLGn)................................................................................................................496



30.5.2 Interrupts........................................................................................................................................................ 498

30.5.3 Chained timers............................................................................................................................................... 498

30.6 Initialization and application information.....................................................................................................................498

30.7 Example configuration for chained timers....................................................................................................................499

30.8 Example configuration for the lifetime timer................................................................

Documents

KL27 Sub-Family Reference Manual - NXP …€¦ · KL27 Sub-Family Reference Manual Supports: MKL27Z128VFM4, MKL27Z256VFM4, MKL27Z128VFT4, MKL27Z256VFT4, MKL27Z128VMP4, MKL27Z256VMP4,