Klaus Wetzig, Claus M. Schneider (Eds.)

Metal Based Thin Films for Electronics

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Klaus Wetzig, Claus M. Schneider (Eds.)

Metal Based Thin Films for Electronics

Klaus Wetzig, Claus M. Schneider (Eds.)

Metal Based Thin Films for Electronics

This book was carefully produced. Nevertheless, editors, authors, and publisher do not warrant the information contained therein to be free of errors.Readers are advised to keep in mind that statements,data, illustrations, procedural details or other items may inadvertently be inaccurate.

Editors

Klaus WetzigIFW Dresden, Germanye-mail: k.wetzig@ifw-dresden.de

Claus M. SchneiderInst. f. Festkörperforschung, Forschungszentrum Jülich GmbH, Germanye-mail: c.m.schneider@fz-juelich.de

1st edition

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© 2003 WILEY-VCH GmbH & Co. KGaA, Weinheim

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Printed in the Federal Republic of Germany

Printed on acid-free paper

Composition B. Prässler-Wüstling, V. Haase, and C. Singer

Printing Strauss Offsetdruck GmbH, Mörlenbach

Bookbinding Großbuchbinderei J. Schäfter GmbH & Co. KG, Grünstadt

ISBN 3-527-40365-5

List of Contributors

Dipl.-Phys. Stefan Braun (2.5, 4.6, 5.4)FhI Werkstoff- und Strahltechnik (IWS) Abt. EUV- und Röntgenoptiken Winterbergstraße 28 D-01277 Dresden

Dr. rer. nat. habil. Winfried Brückner (3.5)IFW Dresden Institut für Festkörperforschung Abt. Dünnschichtsysteme und Nanostrukturen Helmholtzstraße 20 D-01069 Dresden

Dr. rer. nat. Dieter Elefant (4.5)IFW Dresden Institut für Festkörperforschung Abt. Dünnschichtsysteme und Nanostrukturen Helmholtzstraße 20 D-01069 Dresden

Dr. rer. nat. Michael Hecker (3.3)IFW Dresden Institut für Festkörperanalytik und Strukturforschung Abt. Röntgenstrukturforschung Helmholtzstraße 20 D-01069 Dresden

Dr. rer. nat. habil. Hermann Mai (2.5, 4.6, 5.4)FhI Werkstoff- und Strahltechnik (IWS) Abt. EUV- und Röntgenoptiken Winterbergstraße 28 D-01277 Dresden

Dr.-Ing. Siegfried Menzel (4.3)IFW Dresden Institut für Festkörperanalytik und Strukturforschung Abt. Oberflächen- und Mikrobereichs-analytik Helmholtzstraße 20 D-01069 Dresden

PD Dr. rer. nat. habil. Claus M. Schneider (1, 2.4, 4.4, 6)FZ Jülich Institut für Festkörperforschung D-52425 Jülich

Dr. rer. nat. Joachim Schumann (2.3, 4.7, 5.5)IFW Dresden Institut für Festkörperforschung Abt. Dünnschichtsysteme und Nanostrukturen Helmholtzstraße 20 D-01069 Dresden

VI List of Contributers

Dr. rer. nat. Ralph Spolenak (2.1, 4.1)MPI für Metallforschung Abt. Prof. Dr. E. Arzt Heisenbergstraße 3 D-70569 Stuttgart

Dr. rer. nat. Jürgen Thomas (3.2, 4.4, 4.7)IFW Dresden Institut für Festkörperanalytik und Strukturforschung Abt. Oberflächen- und Mikrobereichs-analytik Helmholtzstraße 20 D-01069 Dresden

Dr. rer. nat. Christoph Treutler (5.3)Robert-Bosch GmbH Zentralbereich Forschung und Vorausentwicklung PF 106050 D-70059 Stuttgart

Dr. rer. nat. Hartmut Vinzelberg (4.5)IFW Dresden Institut für Festkörperforschung Abt. Dünnschichtsysteme und Nanostrukturen Helmholtzstraße 20 D-01069 Dresden

Dr. rer. nat. habil. Manfred Weihnacht (2.2, 5.2)IFW Dresden Institut für Festkörperforschung Abt. Oberflächen und Grenzschichten Helmholtzstraße 20 D-01069 Dresden

Dr. rer. nat. Horst Wendrock (4.1)IFW Dresden Institut für Festkörperanalytik und Strukturforschung Abt. Oberflächen- und Mikrobereichs-analytik Helmholtzstraße 20 D-01069 Dresden

Dr. rer. nat. Christian Wenzel (3.1)TU Dresden Institut für Halbleiter- und Mikrosystemtechnik Mommsenstraße 13 D-01069 Dresden

Prof. Dr. rer. nat. habil. Klaus Wetzig (1, 3.2, 3.4, 4.1, 4.3, 6)IFW Dresden Institut für Festkörperanalytik und Strukturforschung Helmholtzstraße 20 D-01069 Dresden

Dr. rer. nat. habil. Ehrenfried Zschech (2.1, 4.2, 5.1)AMD Saxony Manufacturing GmbH Materials Analysis Department PF 110110 D-01330 Dresden

Contents

1 Introduction ........................................................................................................... 1 Klaus Wetzig, Claus M. Schneider

2 Thin Film Systems: Basic Aspects ....................................................................... 72.1 Interconnects for Microelectronics ...................................................................... 7

Ralph Spolenak, Ehrenfried Zschech2.1.1 Introduction ............................................................................................................. 72.1.2 Metallization Layers................................................................................................ 82.1.3 Materials Science of Metallic Interconnects ......................................................... 12 2.1.4 Function of Barrier and Nucleation Layers and Materials Selection..................... 23 2.2 Metallization Structures in Acoustoelectronics ................................................ 25

Manfred Weihnacht2.2.1 Introduction ........................................................................................................... 252.2.2 Fundamentals of Surface Acoustic Waves ............................................................ 262.2.3 Interdigital Transducers (IDTs)............................................................................. 36 2.2.4 Reflector Gratings ................................................................................................. 402.2.5 Waveguides, Energy Trapping ............................................................................. 41 2.2.6 Multistrip Couplers .............................................................................................. 41 2.3 Silicide Layers for Electronics............................................................................ 42

Joachim Schumann2.3.1 Introduction ........................................................................................................... 422.3.2 The Basic Chemical and Physical Properties ........................................................ 43 2.3.3 Preparation of Silicides ........................................................................................ 492.3.4 Silicides with Metallic Conductivity ..................................................................... 56 2.3.5 Semiconducting Silicides ...................................................................................... 58 2.3.6 Heterogeneously Disordered Silicide Films .......................................................... 62 2.4 Complex Layered Systems for Magnetoelectronics ......................................... 65

Claus M. Schneider2.4.1 Introduction ........................................................................................................... 652.4.2 Magnetism: A Primer ............................................................................................ 66 2.4.3 Magnetic Coupling Phenomena ............................................................................ 68 2.4.4 Electric Transport in Layered Magnetic Systems.................................................. 76 2.4.5 Functional Thin Film Systems .............................................................................. 85 2.5 Multilayer and Single-Surface Reflectors for X-Ray Optics ........................... 93

Hermann Mai, Stefan Braun2.5.1 Introduction ........................................................................................................... 932.5.2 Refraction and Reflection at Single Boundaries.................................................... 94 2.5.3 BRAGG Reflection at 1D Lattice Systems ........................................................... 99 2.5.4 Multilayer Preparation......................................................................................... 108 References .......................................................................................................... 112

VIII Contens

3 Thin Film Preparation and Characterization Techniques 3.1 Thin Film Preparation Methods ...................................................................... 121

Christian Wenzel3.1.1 Introduction ......................................................................................................... 121 3.1.2 Physical Vapor Deposition.................................................................................. 123 3.1.3 Chemical Vapor Deposition ................................................................................ 133 3.1.4 Non-Vacuum Based Deposition.......................................................................... 136 3.1.5 Outlook................................................................................................................ 1403.2 Electron Microscopy and Diffraction .............................................................. 140

Klaus Wetzig, Jürgen Thomas3.2.1 Transmission Electron Microscopy (TEM) - Imaging ........................................ 140 3.2.2 TEM - Selected Area Electron Diffraction.......................................................... 148 3.2.3 In situ-SEM Methods .......................................................................................... 150 3.2.4 Electron Backscatter Diffraction ......................................................................... 155 3.3 X-Ray Scattering Techniques........................................................................... 158

Michael Hecker3.3.1 Wide Angle Diffraction....................................................................................... 159 3.3.2 Reflectometry...................................................................................................... 169 3.3.3 Soft X-Rays and Magnetic Scattering ................................................................. 172 3.4 Spectroscopic Techniques................................................................................. 175

Klaus Wetzig3.4.1 Element Distribution Analysis ............................................................................ 175 3.4.2 Element Depth Profile Analysis .......................................................................... 183 3.5 Stress Measurement Techniques...................................................................... 189

Winfried Brückner3.5.1 Stress and Strain .................................................................................................. 190 3.5.2 Substrate Curvature ............................................................................................. 193 3.5.3 Measurement Techniques.................................................................................... 195

References .......................................................................................................... 200

4 Challenges for Thin Film Systems Characterization and Optimization....... 205 4.1 Electromigration in Metallization Layers ....................................................... 205

Ralph Spolenak, Horst Wendrock, Klaus Wetzig4.1.1 Fundamentals ...................................................................................................... 205 4.1.2 Methods for Quantitative Damage Analysis ....................................................... 208 4.1.3 Al Interconnects .................................................................................................. 211 4.1.4 Cu Interconnects.................................................................................................. 215 4.2 Barrier and Nucleation Layers for Interconnects .......................................... 222

Ehrenfried Zschech4.2.1 Introduction ......................................................................................................... 222 4.2.2 PVD Barrier Layers for Copper Interconnects .................................................... 223 4.2.3 Barrier/Seed Microstructure and Step Coverage ................................................. 229 4.2.4 New Barrier/Seed Concepts using CVD and ALD ............................................. 233 4.2.5 Atomic Layer Deposition (ALD) ........................................................................ 234 4.3 Acoustomigration in Surface Acoustic Waves Structures ............................. 235

Siegfried Menzel, Klaus Wetzig

Contens IX

4.3.1 General Remarks ................................................................................................. 235 4.3.2 Acoustomigration Mechanism ............................................................................ 236 4.3.3 Metallization Concepts for Power SAW Structures ............................................ 237 4.3.4 Experimental Set-up............................................................................................ 240 4.3.5 Acoustomigration Experiments........................................................................... 243 4.4 Thermal Stability of Magnetoresistive Layer Stacks ..................................... 251

Claus M. Schneider, Jürgen Thomas4.4.1 Metallic Multilayers as GMR Model Systems .................................................... 252 4.4.2 Co/Cu Multilayers ............................................................................................... 252 4.4.3 Ni80Fe20/Cu Multilayers ...................................................................................... 260 4.5 Functional Magnetic Layers for Sensors and MRAMs.................................. 263

Hartmut Vinzelberg, Dieter Elefant4.5.1 Magnetic Multilayers: Layer Thickness Dependence of the GMR Parameters .. 263 4.5.2 Spin Valves ......................................................................................................... 268 4.5.3 Magnetic Tunnel Junctions ................................................................................. 2734.6 Multilayers for X-Ray Optical Purposes ......................................................... 277

Hermann Mai, Stefan Braun4.6.1 Multilayers as Reflectors for X-Rays .................................................................. 277 4.6.2 Real Structure of nm-Multilayers........................................................................ 279 4.6.3 High-Resolution Multilayers............................................................................... 287 4.6.4 Multilayers with Uniform and Graded Period Thickness.................................... 291 4.7 Functional Electric Layers ............................................................................... 292

Joachim Schumann, Jürgen Thomas4.7.1 Resistance Layers................................................................................................ 292 4.7.2 Thermoelectic Thin Films ................................................................................... 301

References .......................................................................................................... 308

5 Devices ............................................................................................................... 317 5.1 Devices Related Aspects for Si Based Electronics .......................................... 317

Ehrenfried Zschech5.1.1 Interconnect Technology and Materials Trends for Memory and Logic Products317 5.1.2 Copper Inlaid Process: Process Integration and Materials Related Topics ......... 318 5.1.3 Wiring Hierarchy for Copper/Low-K on-Chip Interconnects ............................. 319 5.1.4 New Global Interconnect Concepts..................................................................... 321 5.2 SAW High Frequency Filters, Resonators and Delay Lines.......................... 321

Manfred Weihnacht5.2.1 Introduction ......................................................................................................... 321 5.2.2 Transversal Filters ............................................................................................... 322 5.2.3 Resonators ........................................................................................................... 325 5.2.4 Filters with Spread Spectrum .............................................................................. 328 5.2.5 Delay Lines ......................................................................................................... 329 5.3 Sensor Devices ................................................................................................... 330

Christoph Treutler5.3.1 Introduction ......................................................................................................... 330 5.3.2 Requirements for Thin Films to be Used as Transducers.................................... 330 5.3.3 Thin Film Strain Gauges for Pressure Sensors and Force Meters ....................... 331

X Contens

5.3.4 Thin Film Thermometer in a Micromachined Air-Mass Flow Meter for Automotive Applications .................................................................................... 333

5.3.5 Magnetic Thin Films for Measuring Position, Angle, Rotational Speed and Torque .............................................................................. 334 5.3.6 Conclusions and Outlook .................................................................................... 341 5.4 X-Ray Optical Systems ..................................................................................... 342

Hermann Mai, Stefan Braun 5.4.1 Basic Properties of the Combination of X-Ray Optical Elements....................... 342 5.4.2 X-Ray Astronomy ............................................................................................... 343 5.4.3 X-Ray Microscopy .............................................................................................. 345 5.4.4 Extreme Ultraviolet Lithography (EUVL) .......................................................... 346 5.4.5 X-Ray Reflectometry and Diffractometry........................................................... 348 5.5 Thermoelectric Sensors and Transducers....................................................... 349

Joachim Schumann5.5.1 Introduction ......................................................................................................... 349 5.5.2 Thermoelectric Energy Conversion - Some Basic Considerations...................... 350 5.5.3 Thermoelectric Sensors ....................................................................................... 350 5.5.4 Thermoelectric Transducers ................................................................................ 356 5.5.5 Outlook................................................................................................................ 361

References .......................................................................................................... 361

6 Outlook............................................................................................................... 365 Klaus Wetzig, Claus M. Schneider

Index................................................................................................................... 371

1 Introduction

Prologue

Electronic devices have found widespread use in our everyday lives. The applications cover many areas such as consumer electronics, information technology, engineering, automotive application, transportation, medical diagnostics and treatments, etc. The construction of these devices and their building blocks involves elaborate fabrication processes which are based on a thorough understanding of materials science and solid state physics. The device functional-ity may involve conventional microelectronic, acoustoelectronic, optoelectronic, or future spinelectronic elements, or a combination of these (Figure 1.1). The functionality is achieved by a carefully engineered and complex combination of metallic, semiconducting, and insulat-ing layers. These layers are often micro- and nanostructured by sophisticated lithography techniques in order to achieve the desired properties. Sometimes, as in the case of micro-processors, the structuring involves several levels. The individual feature sizes created by the structuring processes may be as small as 100 nm and are expected to become even smaller in the future in leading edge applications.

Figure 1.1: The application regimes of metal-based thin films in the microelectronics area

2 1 Introduction

The fabrication of these electronic devices requires a very good control of the materials properties. This concerns not only the physical material parameters, but also the film struc-ture and morphology. The latter are largely determined by the details of the deposition proc-ess and postgrowth processing procedures. In addition, the interfaces between different mate-rials and material classes are also becoming of crucial importance. In this situation, a wide variety of analysis tools must be used to ensure a reliable process control and – if necessary – a precise failure analysis. These tools include not only different real space (microscopy) and reciprocal space (diffraction) techniques, but also spectroscopic techniques, electrical trans-port measurements, stress and strain analyses, migration investigations, etc.

Novel device technologies are often closely linked to the use of new materials or material classes. One recent example is the replacement of the conventional Al interconnects in mi-croprocessors by Cu ones. This step not only involves new fabrication procedures, such as the “damascene” technique, but also requires new barrier layers to avoid the mixing of Cu and Si. Another example is the emerging technology of magneto- or spinelectronics. In its present state it employs complex magnetic units composed of metal or metal/insulator layer stacks. In addition to the electrical properties, the layers must also provide a distinct mag-netic functionality. Since all of the classical ferromagnets Fe, Co, Ni and many antiferro-magnets used in magnetoelectronics are metals, this adds another and very exciting facet to the application of metal-based films in electronics. From the above considerations follows quite clearly that metal-based thin films play a central role in the different steps of the fabrication and for the specific functionality of elec-tronic devices. The most evident use concerns conducting lines and interconnects. Less obvi-ous is their employment as barrier layers against interdiffusion and segregation. Also very important are metallization layers, for example, in acoustoelectronic devices. In chemically complex systems, the physical properties can be conveniently changed by the chemical com-position. This is particularly true for the conductivity and is exploited in silicides for ther-moelectric applications. Metal-based films are also very important for X-ray optical tech-niques used to fabricate (X-ray lithography) and analyze (X-ray diffraction and spectros-copy) electronic device structures. Since metal-based films have such a widespread use in the different areas of microelec-tronics, knowledge of the respective properties and phenomena is distributed over various fields of physics and materials science. As a consequence, one usually has to consult many different sources in order to get the desired piece of information or a broader overview of a specific issue. Considering the importance of metal-based films in the field of electronics it is thus justified to describe and discuss these systems, the associated effects and phenomena, and their applications in one place.

Organization, Aim and Content of This Book

The main purpose of this book is two-fold. On the one hand, it is meant to serve as a com-pendium for metal-based thin film systems and their usage in electronics technology. As such, it addresses both the scientist and the research engineer. On the other hand, the book also includes a more tutorial part which is intended to bridge the gap between fundamental phenomena and their technological applications. It may therefore also serve as a textbook for advanced students in solid state physics, materials science, and electronics engineering.

Organization, Aim and Content of This Book 3

The book is organized into several chapters covering the range from principal aspects and phenomena over contemporary challenges in materials science to actual device concepts and applications. We thereby mainly concentrate on the relevant fields of interconnects, acousto-electronics, thermoelectrics, magnetoelectronics, and X-ray optics. In Chapter 2 we review the various fundamental aspects of metal and metal-based films with respect to the individual fields and applications addressed in this book. This chapter is mainly intended to convey background information for the advanced student in a more tuto-rial form. It forms a basis for the discussion of the future challenges and the device-related topics in the subsequent chapters. The first section is devoted to a key aspect in microelec-tronics, namely the means to transfer and distribute information and power in a microelec-tronic device, for example, in a microprocessor. This is achieved by means of metallic inter-connects which are usually arranged in very complicated and delicate three-dimensional networks. The contribution discusses both Al and Cu-based technologies for interconnects and highlights the specific implications and problems associated with each technology. A somewhat less familiar, though not less eminent area of microelectronics is acoustoelectron-ics. Acoustoelectronic devices are based on the exploitation of phenomena involving the generation, transport, and filtering of surface acoustic waves. Their functionality is largely determined by the interaction between a piezoelectric substrate and a metallic film serving as an electrode. Surface acoustic wave devices play a strategic role in telecommunication and other high frequency applications. A rather novel facet of microelectronics is called magne-toelectronics or “spintronics” which is the topic of the third section of Chapter 2. Spintronics is still an emerging technology which is based on the transport of spins and charges, rather than just charges. It thus combines magnetic functionalities and materials with established microelectronics concepts. Current spintronics applications concern read heads in hard disk drives, magnetocouplers, or nonvolatile magnetic random access memories (MRAM). In the long run, reprogrammable magnetic logic circuits or active magnetoelectronic devices, such as a spin transistor, may be expected. The section reviews the fundamental aspects of spin-dependent transport and magnetic coupling phenomena in thin films and layer stacks. It also discusses the basic thin film arrangements and their specific properties with respect to a particular device functionality. Thermoelectricity exploits the conversion of thermal energy into electrical energy and vice versa for power generators, cooling devices, and temperature or radiation sensors. The particular relevance of thermoelectrical systems for microelectron-ics arises – among other reasons – from the increasing need for efficient thermal and power management of chip devices. The implementation of Peltier elements in the chip architecture can provide on-chip cooling facilities. The recovery of excess heat and its conversion into electrical energy may help to reduce the overall power consumption and represents a step towards future self-sufficient systems. The different material systems and thermoelectric concepts which are currently under consideration are treated in the fourth section. Particular emphasis is put on the role of the various materials properties with respect to the thermoelec-trical efficiency parameters and figure of merit. The final section of the chapter deals with the role of metallic layers and multilayer systems for X-ray optics. The connection of X-ray optics to microelectronics comes from the progress in optical lithography techniques which aim at feature sizes well below 100 nm. Because of the smaller wavelengths, the novel li-thography approaches can no longer be based on transmission optics, but have to use reflec-tive optics instead. Metal thin film systems are therefore needed to realize the appropriate optical elements (mirrors, gratings, etc.). The section discusses the fundamental aspects of X-ray optics with respect to thin film systems based on reflection and diffraction.

4 1 Introduction

Chapter 3 is devoted to the deposition techniques used to prepare thin film systems and to the main analytical approaches employed to study their behavior. The analysis involves mi-croscopy, spectroscopy, or diffraction techniques and gives access to different properties, such as the film morphology, chemical composition, crystallographic and electronic struc-ture. Deposition techniques for thin metallic films exist in a wide variety and are described in Chapter 3.1. Today vacuum based physical and also chemical deposition techniques play the dominant role in the preparation of thin metallic films, but non-vacuum based deposition methods such as electroplating or the modified CVD technique ALD (atomic layer deposi-tion) are also of growing interest and will therefore be discussed in this book. Both transmis-sion electron microscopy (TEM) and electron diffraction are strong techniques for studying micro- and nanostructures in metal based thin films. Furthermore, with enhancement of an analytical TEM by spectroscopic attachments for such as energy dispersive X-ray spectros-copy (EDXS) and electron energy-loss spectroscopy (EELS) it is also possible to receive chemical information (element distribution and chemical binding) in the nanometer range of thin films. A powerful method for the immediate study of electrical thin film properties is in situ scanning electron microscopy (SEM). In situ SEM methods allow the investigation of potential contrast, ferroelectric domains, electron beam induced current (EBIC) and proc-esses of electro- or acoustomigration respectively. X-ray scattering techniques are discussed as a widely-used tool for structural information on thin films. Both the possibilities and limi-tations of angle diffraction, reflectometry, soft X-rays and magnetic scattering are discussed. Spectroscopic techniques allow the element distribution and depth profile analysis of thin films. They can be carried out by electrons, X-rays or ions and are frequently used in connec-tion with imaging techniques such as scanning or transmission electron microscopy. In con-trast to bulk materials, thin films on substrates are usually under mechanical stress. Thus, stress measurement methods play an important role in the characterization of thin films for electronics. Different techniques such as the substrate curvature and the sin2� method are discussed under application aspects. As one of the core parts of this book Chapter 4 addresses current challenges in the inves-tigation and application of metal-based thin films. These include the aspects of thermal sta-bility, acousto- and electromigration, barrier and nucleation layers, functional electric and magnetic layers and mulilayers for X-ray optical purposes. These topics represent the fore-front of the current research in materials science and solid state physics. Because of the con-tinuing downscaling in the architecture of integrated circuits electromigration is a life- limit-ing process in metallization layers. The damage analysis is discussed both for Al and Cu interconnects. The introduction of copper as the conducting material for interconnects re-quires effective diffusion barriers since copper readily diffuses into silicon oxide and silicon. The optimization of barriers and new barrier/ seed concepts are therefore the focus of atten-tion. Migration effects are also observed in surface acoustic waves (SAW) structures, as a result of diminishing structure dimensions (< 1 μm) and increasing electrical input power values (> 1 W) which cause very high power density levels and therefore high stress loading of metallization. Thus, new metallization concepts have to be discussed in detail. Spintronic applications of functional magnetic layers, such as for sensors and MRAMs, may be realized by thin film systems which may be grouped into multilayers, spin valves and tunnel junc-tions. These systems excel in a precisely defined functionality which is strongly influenced by temperature. Therefore the thermal stability plays a dominant role in both the manufacture and operation of functional magnetic layers, as will be demonstrated for magnetoresistive layer stacks. A further group of thin film based components with growing importance are

Organization, Aim and Content of This Book 5

multilayers for X-ray optical purposes, e.g. as reflectors for X-rays. Finally, the last part of Chapter 4 is focused on functional electric layers with well–defined electronic and electrical transport properties. Such thin film materials are used as resistance layers, thermoelectric sensors and generator devices. The optimization of the electrical and thermoelectric film parameters will be discussed in depth. The application of metal-based thin film systems in electronic and microelectronics-related devices is the focus of Chapter 5. The diversity of the devices treated in this chapter highlights the widespread application areas of metal film systems. The first section deals with interconnect technologies for memory and logic products. Of particular interest are the combination of Cu interconnects and low-k dielectrics. The subsequent section on surface acoustic wave devices gives examples of high frequency filters, resonators and delay lines. The device concepts range from relatively simple transversal bandpass filters to programma-ble phase shift keying filters. The magnetic and magnetoelectronic sensor devices are mainly related to automotive applications and thus emphasize one of the growing future markets for microelectronics products. There, magnetic sensors are employed to measure positions, an-gles, rotational speeds, or torques with the aim of improving fuel economy, vehicle and pas-senger safety, and driving comfort in the present and new generations of automobiles. Re-ducing the energy consumption and improving the energy efficiency is also the driving force in the development of thermoelectric sensors and transducers. The devices discussed range from thermal converters for high precision AC measurements to low power thermoelectric generators and microcoolers for applications in microelectronics. The chapter closes with a section describing several examples of X-ray optical elements based on metal thin film sys-tems. The applications cover not only X-ray telescopes and microscopes, but also recent developments in the area of extreme ultraviolet lithography (EUVL) instrumentation. The latter will be the fundamental tool for a future downscaling in microelectronics. The final Chapter 6 of the book gives an overview of the developments to be expected in the field of metal-based thin films and their implementation into microelectronic circuits and devices. The future will not only see the use of new materials and device concepts, but also the fusion of distinct areas to achieve improved or novel functionalities. This concerns, for example, the possible implementation of optical interconnects which may be seen as a com-bination of standard microelectronics and optoelectronics. Another example is the incorpora-tion of nonvolatile functions on the basis of magnetic components, i.e., the synthesis of con-ventional microelectronics and spinelectronics. The major driving forces behind these activi-ties are not only the expected revenue, but also the opportunity for new discoveries and de-velopments which may completely change our current picture of microelectronics in the future.

Acknowledgement

Particular thanks go to Mrs. B. Prässler-Wüstling, Mrs. V. Haase, Mrs. C. Singer and Mrs. K. Schmiedel for their skillful processing of the various manuscripts during the prepara-tion of the book. We also would like to thank Mrs. V. Palmer and Mrs. C. Wanka from Wiley-VCH for their support and help during this project.

2 Thin Film Systems: Basic Aspects

2.1 Interconnects for Microelectronics

2.1.1 Introduction Interconnects are the means of transportation of information within a microelectronic circuit. When one takes apart an old radio, one finds that all the active components are connected by single wires, each of which has been soldered to transistors, resistances, capacities etc. Nowadays this apparent chaos of wires is replaced by printed circuit boards where a polymeric substrate is covered with copper and channels are etched to create wires. A three-dimensional wire structure has been converted into a planar structure and only now and then has an additional wire to be added to form a bridge. The aspect ratio of the copper wires is small i.e. they are much wider than high. Low cost wet etch techniques can be employed.

Figure 2.1: SEM cross-section of AMD's eighth generation microprocessor with eight levels of copper interconnects [2.1]

When one takes apart a modern microelectronic chip one will find a completely different scenario. Unlike the printed circuit board there are several up to ten different metal layers in an integrated circuit. The active components are all situated in the substrate, which is usually made of silicon. The aspect ratios are higher, in extreme cases even significantly greater than one (i.e. the lines are higher than wide). In addition to the conductor lines made out of copper

8 2 Thin Films System: Basic Aspects

or aluminum, one introduces several other layers, such as dielectrics, etch stops, anti-reflective coatings, diffusion barriers and vertical connections (so-called plugs). The barriers will be discussed at the end of this chapter. All of these layers have special functions and properties. Figure 2.1 shows a cross-section of a state of the art microprocessor revealing the complicated layers of wiring that will be described in detail later in this chapter. In order to create a working circuit the engineer has to overcome two basic challenges: manufacturability and reliability. The first, even if sometimes very complicated, is usually straightforward. It is apparent whether a circuit works or not. However, sometimes the search for the reason for failure can be tedious. In the case of reliability, on the other hand, it is difficult to predict whether a circuit will work ten years from now. This task is usually addressed by a combination of the following concepts. Lifetime tests have to be accelerated by increasing temperature and the current densities that the wires have to carry. Obviously these conditions are not realistic and thus have to be extrapolated to service conditions. Empirical models that are based on variations in temperature and current density are relatively easily to formulate, however, they bear the risk of being too aggressive or too conservative when the extrapolation is made. It is now the task of materials science to promote understanding of the mechanisms responsible for failure, investigate their temperature and current density dependence and formulate mechanistic models that can be employed for lifetime prediction. The next sections will focus on the fabrication of interconnect lines, their dimensionality and function, the materials science applicable to them and finally will elucidate future perspectives. The last section will focus on function and materials choice of diffusion barriers.

2.1.2 Metallization Layers

Function of On-Chip Interconnects and Materials Selection The function of an interconnect system is to distribute clock and other signals and to provide power/ground, by connecting the various circuit/systems functions of a chip. The fundamental development requirement for the on-chip interconnects is to meet the high-speed needs of chips to transmit clocks and signals despite further down-scaling of feature sizes. In particular, the so-called RC (resistance x capacitance) time delay has to be minimized using a smart interconnect design and new technologies and materials. This task includes the development and the implementation of conducting material with low resistivity for interconnects and of dielectric material with low permittivity as the isolating material between them. Additionally, numerous other, mostly ultrathin films of the back-end-of-line layer stack have to be considered since they all contribute to the overall performance and reliability of the interconnect system: barriers, capping layers, etch stop layers, hard masks, etc. The following requirements for the conductor material have been derived from the performance and reliability requirements of the on-chip interconnect system:

� low resistivity (high electrical conductivity) � high thermal conductivity � high melting point (and thus low diffusivities) � materials compatibility to the isolating dielectric material and to barrier and capping layers

2.1 Interconnects for Microelectronics 9

� technology compatibility to the back-end-of-line process.

The first level of metallization is the contacting plug that provides the connection to the metal-oxide-semiconductor field effect transistors (MOSFETs). Until now, tungsten has been widely used for the contacting plug to the devices and for the so-called local interconnects in microprocessors, ASICs and dynamic random access memories (DRAMs). One challenge will be high aspect ratio (A/R) stacked capacitor DRAM contacts with A/R up to 20 and more. For the further interconnect system, metallic films with lower resistivity, e.g. aluminum and copper, are usually used. For more than 30 years, the back-end-of-line manufacturing in the semiconductor industry was dominated by the “metal PVD and metal wet-etch” wiring technology. That means, aluminum and aluminum alloys were deposited using physical vapor deposition (PVD) followed by a wet subtractive etching. Al(Cu) alloys have been used since the late 1960s to alleviate electromigration concerns associated with the Al(Si) metallurgy. Thin layers of refractory metals like Ti above and/or below the Al(Cu) interconnects and the formation of Al3Ti films reduced the contact resistance and improved the electromigration stability. Both performance and reliability of high-performance microprocessors (HP MPU) is increasingly determined by design, technology and materials for interconnects and dielectric interlayers which result in lower RC products. The need for new conductor and dielectric materials that would be necessary to meet the projected overall technology requirements has been described in the Technology Roadmap for Semiconductors since 1994 [2.2,2.3]. As the dimension of the interconnect lines continues to shrink, aluminum-based interconnects and CVD oxide/nitride interlayer dielectrics are being replaced by inlaid copper with reduced electrical resistance and by low-k dielectrics. Besides the higher conductivity, inlaid copper lines also offer the advantages of improved electromigration performance and reduced cost of manufacturing [2.4–2.6].

Table 2.1: Materials properties for aluminum and copper

Physical property Aluminum Copper Specific electrical resistivity (μ cm)

2.72 1.71

Thermal conductivity (W m-1 K-1)

238 327.7

Melting point (K)

933.5 1358

Table 2.1 compares materials properties for aluminum and copper. The resistivity of copper is about 40% lower than that of aluminum, which is generally mentioned as the major advantage in introducing this material, since it improves the product performance of microprocessors and memories due to the direct impact on the RC product. The high melting point of copper is advantageous for the interconnect reliability, since all diffusion-controlled atomic transport processes are slower, and consequently, the current-carrying capacity is higher. The introduction of a planar multilevel metallization architecture with inlaid copper interconnects was first reported by IBM in September 1997 [2.4]. Copper was deposited

10 2 Thin Films System: Basic Aspects

using an electrochemical deposition process (ECD) into trenches and vertical contacts (vias). These inlaid structures had been etched into silicon oxide layers deposited using chemical vapor deposition (CVD) from tetraethylorthosilicate (TEOS). Since that time, copper has mainly been used for microprocessor applications. Although chips with inlaid copper interconnects in silicon dioxide (dielectric constant k = 4.0) were introduced in 1998, we have witnessed the start of the change to new insulator materials with lower dielectric constant only recently. Fluorine-doped silicon dioxide (FSG, k = 3.7) combined with the copper dual inlaid process has been in production since the 180 nm technology node. Next potential materials for the 130 nm technology node and below are lower-k materials (k = 2.6–3.0) like organic spin-on-polymers (SOP) and plasma-enhanced CVD (PECVD) inorganic/organic hybrid materials [2.7, 2.8]. Potential commercial materials for this k range could be Applied Material’s Black Diamond organosilicate material, Coral organosilicate glass (OSG) film from Novellus, Flowfill CVD from Trikon Technologies and SiLK spin-on low-k material from Dow Chemicals. Eventually, the nitride etch-stop layers and even the dielectric antireflection coating (ARC) layers/hard masks (with k ~ 7–9) will probably be replaced by SiC-based films (with k < 5) offered by Novellus and Applied Materials. Ultra-low-k materials (ULK, k < 2.5) are in development. Integration efforts focus on solving the problems of these reduced density materials with their compromised thermal and mechanical properties. The ideal ULK material will have a closed pore structure and uniformly distributed pores with a maximum pore size, tied to, and decreasing with, the technology node. A tight pore size distribution is also desirable. Porous ULK materials need even more planarization development efforts than nonporous materials. The introduction of these new conductor and isolator materials, along with the reduced thickness and higher conformity requirements for barriers and nucleation layers, is a difficult integration challenge. The most challenging integration modules are dielectric etching, integrated cleaning, chemical-mechanical polishing (CMP) and packaging. A primary integration challenge with the low-k materials is the adhesion failure of barrier or capping materials with the dielectric during planarization. Process integration and device related aspects are described in Section 5.1.

Table 2.2: Selected interconnect technology requirements from the 2001 ITRS [2.2]

Technology node 130 nm 65 nm 22 nm

Number of metal levels 8 10 11

Total interconnect length active wiring (m cm-2)

4086 11169 33508

Local wiring pitch (nm) 350 150 50

Local wiring aspect ratio, Cu 1.6 1.7 2.0

Conductor effective resistivity, Cu intermediate wiring (μ cm)

2.2 2.2 2.2

Interlevel insulator effective dielectric constant (k)

3.0-3.6 2.3-2.7

2.1 Interconnects for Microelectronics 11

Table 2.2 shows some 2001 ITRS requirements for on-chip interconnect systems [2.2]. Important parameters are the minimum trench width and the aspect ratio (A/R) for interconnects. According to the roadmap, the minimum trench width for interconnects will decrease from today’s 115 nm to 22 nm in 2016.

Fabrication In principle, there are two routes that are currently applied: (a) the subtractive method (aluminum), and (b) the inlaid method (copper). Up to 1998, all microelectronic devices were fabricated with aluminum metallization. Most of the chips, except for high end applications like microprocessors or fast RAM, are still built that way. Traditionally, the fabrication of interconnects and dielectrics belongs to the so-called back-end-of-line process, because they are physically located at the ‘back-end’ of a fabrication line. All transistor fabrication processes belong to the front end. Aluminum lines are fabricated by depositing a homogenous thin film by magnetron sputtering. Usually the deposition of Al is preceded by a thin layer of titanium or titanium nitride as a diffusion barrier and followed by the same material as an antireflection coating for lithography purposes. Subsequently, a layer of photoresist is deposited and cured. The photoresist is then exposed to UV light and a pattern is transferred from a mask to the photoresist. After dissolution of the exposed areas the photoresist has the same pattern as the aluminum will eventually have. In the next step the photoresist serves as an etch mask to remove Al by a reactive ion etch process (RIE). Usually chlorine is used as an etch gas, which prevents under-etch by forming a passivating layer on the sidewalls. The photoresist is then removed by an oxygen plasma. In the next step a dielectric, usually a glass, is deposited and planarized by a polishing step if several layers of metallization are anticipated to follow. In order to allow for a 3D structure, the dielectric is patterned and filled with so-called tungsten plugs by a CVD process. This process (Figure 2.2) is repeated iteratively in order to generate a multilayer structure.

Figure 2.2: Comparison of Al (conventional) and Cu (inlaid) process flow

As mentioned before, with the demand for higher and higher clock frequencies the time delay associated with the interconnect structure (RC time delay) eventually became time

12 2 Thin Films System: Basic Aspects

limiting. This, among other factors, was the driving force in replacing the combination aluminum-glass by the combination copper-polymer. The change in material, however, proved to be a significant step for the industry as it incorporated significant changes in processing in a previously only marginally researched field. Unlike for aluminum, there is no adequate RIE process for mass-production of copper. Therefore, the entire process had to be inverted (Figure 2.2). After the front end processes a layer of dielectric is first deposited. This layer is then patterned to form trenches in which the copper is to be deposited except for the first layer, which is in direct contact with the silicon substrate. In this case tungsten plugs are deposited by a CVD process. Different deposition techniques are required for several reasons: (a) the sputter process cannot fill high aspect ratio trenches; (b) as copper is a highly undesirable contaminant for silicon, the copper line has to be encapsulated from all sides with diffusion barriers; (c) an additional silicon nitride etch stop is needed for subsequent layers. The solution to these issues is a sputter deposition of a diffusion barrier (Ta, TaN) and a thin copper seed layer. In the next step the wafer is immersed into a copper electroplating bath and the trenches are overfilled so that a relatively homogenous copper surface is established. This process is called electrochemical deposition (ECD). Now, however, there is a short circuit between all interconnects. This dilemma is solved by borrowing an ancient artisan technique from Damascus. The excess copper is removed by a chemical mechanical polishing step (CMP) that confines the metal to the corresponding trenches (“Damascene” technique). The encapsulation is then completed by a thin layer of silicon nitride which serves as an etch stop for the subsequent layers as well as a diffusion barrier. Again the process is repeated iteratively to form a 3D structure. A general trend that should be noted is the increase in the line widths from the layer closest to the silicon to the top (Figure 2.1). The layer thickness generally stays the same. So far the metal in these interconnects has been treated as a homogenous material. However, in reality the continuous line is formed by a polycrystalline copper material. The next section will address the consequences of thin film crystallinity.

2.1.3 Materials Science of Metallic Interconnects

Microstructural Effects When a thin film is deposited onto an amorphous substrate, the microstructure that evolves depends on a variety of deposition parameters. The key thin film parameters that one tries to influence/optimize are grain size, texture, defect density and roughness. Again the cases of aluminum and copper have to be differentiated. The key parameters in aluminum sputter deposition are deposition rate, substrate temperature, argon pressure and residual gas pressure. For high throughput and high purity high deposition rates are desirable. An elevated substrate temperature enhances grain growth but leads to higher roughness. Usually, aluminum films are also thermally annealed after the deposition process to trigger grain growth and heal defects. For aluminum the equilibrium grain size is given by the film thickness according to the Mullins criterion [2.9], where grain boundary grooving limits further grain growth. The preferred crystallographic orientation of grains (texture) that one tries to establish for reliability reasons (see Section 4.1), is the (111) out of plane orientation. The �111� axes of all grains are closely aligned to the substrate normal. Details of measurement and

2.1 Interconnects for Microelectronics 13

quantification of textures can be found in Section 3.3. For aluminum films this texture is easily achieved as the (111) surfaces have the lowest surface energy and thus the energy of the system is minimized. In the case of electroplated copper, on the other hand, several new effects can be observed. Electroplated copper tends to self anneal at room temperature [2.10, 2.11]. This effect is rather surprising as the homologous temperature of copper (temperature normalized by the melting temperature, usually a measure of diffusion) is significantly lower than for aluminum. The grains grow abnormally (Figure 2.3) that means that a minority of grains ‘eats up’ all the grains around them. In normal grain growth all grains would grow at a similar rate. Usually, the self-annealing effect is attributed to the bath chemistry of the electroplating bath that appears as contaminants in the copper film.

Figure 2.3: FIB (focused ion beam) images of electroplated and sputtered 1 �m Cu films at 0° tilt (scale bar: 3 μm) [2.12]

The scenario is further complicated as copper interconnects exist in the form of lines and contacts with geometry- and process-dependent microstructure and properties. The microstructure of copper interconnects is essential for both product performance and reliability. In particular, degradation mechanisms in copper interconnects can be influenced by their microstructure parameters such as grain size, texture and stress. From the materials point of view, alternative barrier and capping layer materials pose additional challenges (see Section 4.2).

Test structures with arrays of parallel single inlaid copper lines with varied line width allow for the quantification of the geometry dependence of the copper microstructure. In [2.13, 2.14], trenches with a height of 0.45 μm and a width between 0.35 and 1.0 μm were etched into silicon oxide. Their sidewalls were not fully vertical, i.e., the sidewall angle was about 85o, with the smaller width at the trench bottom. The trenches were filled using ECD after deposition of Ta barrier and Cu seed layers. After CMP, a thin silicon nitride film was deposited onto the samples (see Figure 2.4).

14 2 Thin Films System: Basic Aspects

Figure 2. 4: Copper line cross section (schematically); w, h = width and height of the copper line; = sidewall angle [2.13]

Figure 2.5: Schematic illustration of the preferred crystallographic orientation of bottom oriented and sidewall oriented grains in copper lines [2.13]

Due to the geometry of the trenches additional texture components can be observed (Section 3.3). One can find �111� texture components that are perpendicular to the sidewalls of the trenches. With decreasing line width, the relative contribution of the texture component from sidewall oriented copper grains to the total texture increases. The preferred crystallographic orientation of both bottom oriented and sidewall oriented grains in narrow copper lines is shown schematically in Figure 2.5 [2.13]. Again surface energy minimization is the driving force. As copper has a relatively low stacking fault energy compared to aluminum (especially when not very pure), plastic deformation is accommodated by mechanical twinning. This is a process in which all atoms in a crystal region are moved in unison to form a twin boundary that corresponds to a stacking fault. By this process the macroscopic shape of the crystal is changed and plastic strain is accommodated. One can envision this process by taking a single crystal, cutting it in half along a (111) plane, rotating it by 180° and gluing it together again. In terms of texture a (115) component is added to the already existing �111� component [2.12-2.14]. Another attribute of copper is its high elastic anisotropy. This also has consequences [2.15] regarding the evolution of texture in copper metallization. We have explained that �111� texture in aluminum is driven by surface energy minimization. If a thin copper film, however, is under mechanical stress an additional term comes into play. Thus we have a competition between surface energy minimization and strain energy minimization, an energy term that scales with the volume. Thus it is apparent

2.1 Interconnects for Microelectronics 15

that for thicker films the strain energy term starts to dominate and we observe a texture change from �111� to �110� out of plane. In the last paragraph we have explained a texture component by the existence of mechanical stresses in thin films. But what is the origin of these stresses? One can imagine that in a sputter process when energetic argon ions are impinging on the film in formation compressive deposition stresses arise. However, as usually the metallization is annealed after deposition, deposition stresses are of secondary importance. The most important stresses are the so-called thermal stresses induced by the mismatch in the thermal expansion coefficients (CTE) of the film and substrate, usually of the order of tens of ppm K-1. When a thin film is now annealed at high temperatures, where diffusive processes are active and stresses can be relaxed, and subsequently cooled, tensile thermal stresses are observed as the metal has a much higher CTE than the semiconducting substrate. As these stresses are very important for interconnect reliability great care is taken in their measurement (also see Section 3.5). At room temperature these films are usually at their tensile yield stress [2.16]. As the yield stress of thin films scales inversely with their thickness and grain size [2.17-2.19], thinner films or narrower lines experience higher and higher stresses. These stresses can be responsible for failure by stress voiding due to thin film creep processes and institute a reliability issue. Recently, a fairly broad distribution of local stresses has been found by X-ray microdiffraction techniques [2.20] (see Section 3.3). Another case where local stresses are important is electromigration which will be briefly introduced later. There, stresses may even have a beneficial effect as their gradients counteract the electromigration driving force (for details see Section 4.1). The detailed mechanical stresses in copper lines, however, are affected by the inlaid process and arise from the differences in the linear thermal expansion coefficients, not only between the metallic interconnect and the substrate, but also the dielectric that rigidly confines it, as well as the line aspect ratio. But both grain size and texture interact with stress in inlaid copper lines too, and the stress level can be changed by the same process parameters which influence other microstructure features [2.13, 2.14]. The stress level in inlaid copper lines was measured by Besser et al. [2.14, 2.21, 2.22] and Ho et al. [2.23, 2.24]. They found that the stress in copper lines increases with increasing post-plating anneal temperature. Vinciet al. and others [2.25-2.27] observed stress-induced voiding in passivated copper lines, which institutes an additional failure mode. Since the atomic transport processes which can cause degradation of copper interconnects depend on interconnect geometry and copper microstructure, the measurement of microstructure parameters like grain size, texture and stress on a routine basis is a reasonable monitor of the process stability. This approach of copper microstructure monitoring was reported by Zschech et al. [2.28]. Statistically relevant data for texture and stress of copper lines were obtained with a micro X-ray diffractometer (micro-XRD) in reasonable periods of time for process control. The specific test structures consist of arrays of parallel single inlaid copper lines with an array size of 120 � 120 μm2. According to [2.28] stress and texture in copper lines are the most sensible microstructure parameters to control deposition and anneal processes in the interconnect technology. For instance, stress changes in the capping layer are reflected also in stress changes in the copper lines. The stress was determined for several directions from lattice parameter shifts based on the Cu (311) Debye ring intensity analysis. The texture was monitored quantitatively along and across the copper lines, based on Cu �111�, �110� and �110� pole figures.

16 2 Thin Films System: Basic Aspects

Figure 2.6 shows the grain size, texture and stress data for a production period of 8 weeks [2.28]. In this particular case, the microstructure of single inlaid copper lines with a line width of 0.18 μm was monitored. The inlaid copper lines were fabricated in SiO2 using an oxide patterning and etch technique. PVD-Ta and PE-CVD Si3N4 were used as barrier and capping layer, respectively. Overall, the data demonstrate a high stability of interconnect manufacturing.

Figure 2.6: Copper line microstructure monitoring: grain size (upper left), texture (upper right), and stress (lower left). The data show high process stability [2.28]

In terms of the characterization of the microstructure of thin metallic films several, sometimes complementary, techniques are employed. Chapter 3 describes these techniques and their applications in detail. So far we have addressed pure metallic systems as in the case of aluminum or a contaminated system as in the case of electroplated copper. In the latter system contamination even had a beneficial effect (self-anneal). In the next section we will talk about the intentional addition of other elements: alloying.

Purpose of Alloying About twenty years ago aluminum interconnects started to show a failure mode known as electromigration (see Section 4.1). Further miniaturization seemed to be a risk as smaller interconnect cross-sections increased the current densities and thus accelerated the electromigration phenomenon. By chance, minute quantities of Cu were added to a batch of chips and an increase in lifetime of two orders of magnitude was observed in 1970 [2.29].

2.1 Interconnects for Microelectronics 17

Since then Al(Cu) alloys (~ 0.5 wt% Cu) are commonly used for interconnects. Details of why Cu has such a beneficial effect will be given at a later point (see Section 4.1). The addition of Cu is just an example; in general trace elements can have the following effects:

�� increase yield stress �� prevent interdiffusion �� reduce self diffusivities �� create self passivating layer �� reduce fatigue effects �� promote adhesion �� provide shunt layers �� improve electromigration.

Usually, however, beneficial effects come at a cost. As the main task of interconnects is the conduction of electrical current, their resistivity has to be minimized. Any addition of alloying elements will, in general, increase the resistivity. The degree of resistivity increase, however, depends on the kind of alloying element used. The electromigration resistance of aluminum can be improved by various dopants. Cu in Al(Cu) alloys for instance forms intermetallic Al2Cu precipitates which eventually appear at grain boundaries and interfaces. There, they serve as reservoirs to block fast diffusion paths and reduce the rate of material transport without significantly increasing the resistivity (see Chapter 4). In solid solutions, such as Al(Mg), which also improves the electromigration resistance, the dopant atoms also act as additional scattering centers, and the resistivity is increased significantly. Let us address some of the effects mentioned above in a little more detail. The yield stress of a thin film is determined by its thickness, the grain size and its texture [2.17-2.19, 2.30]. If the yield stress has to be increased even more, one has to introduce obstacles for dislocations that have a spacing that is significantly smaller than the grain size or thickness. This can be achieved by particles such as Al-Cu precipitates or ceramic yttria, or by single atoms that have a significant size difference to the matrix and pin dislocations caused by their stress field (e.g. Mg). One of the common alloying elements for Al in addition to Cu is Si. In some circuits the interconnect material is in direct contact with the semiconductor. The resulting undesirable phenomenon is the so-called spiking where Al and Si interdiffuse locally. If the aluminum alloy is already saturated with Si there is no driving force for interdiffusion and the phenomenon is suppressed. One of the common barrier layers for Al is Ti. On the one hand, this improves the Al texture, on the other hand Ti diffuses into Al and creates an intermetallic phase at the bottom of the interconnect. This usually forms a high resistance conducting path. So if a void is formed by thermal stresses or electromigration, the current path changes from the line down to the intermetallic layer. This causes local heating and in many cases leads to a self-healing of the void. The relevant issues for inlaid Cu metallization are self-passivation and electromigration. The resistivity of copper alloys increases with the dopant concentration and with the charge difference between copper and the dopant. Mg and Al have been studied as dopant elements in copper since these elements diffuse to the interfaces and form stable oxides. In this way the lines would be self-passivating [2.31, 2.32]. Hu et al. [2.33] have shown that the addition of Sn to Cu metallization significantly reduces the electromigration drift velocity. However,

18 2 Thin Films System: Basic Aspects

the addition of a small percentage of Sn (0.5–2.0 wt%) decreases the average grain size of copper and hence increases the number of fast diffusion paths for material transport. Additionally, the electron scattering rate at grain boundaries increases.

Interconnect Degradation and Reliability Advanced process technologies and new combinations of materials bring about new reliability challenges: different microstructure of the metallic interconnects, other types of interfaces and new degradation phenomena. Electromigration, stress-induced degradation and mechanical weakness in the case of low-k materials are reliability concerns for inlaid copper interconnects. The current generation of highly integrated microprocessors, requiring dense interconnects and increased current densities, has highlighted the electromigration issue. Formation of voids in copper lines induced by electromigration during normal microprocessor operation will cause an interconnect opening or a high resistance, resulting in malfunction or speed degradation, respectively. Stress-induced degradation phenomena and later catastrophic failures are not yet well understood, but they are probably exacerbated by normal stresses at the copper/barrier and copper/nitride interfaces as well as hydrostatic stress components. In particular, fast diffusion paths have to be identified and failure mechanisms based on directed transport of atoms have to be understood. This knowledge is the basis for process and materials changes which improve interconnect reliability. Considering a high-quality processing technology, degradation of inlaid copper lines is connected with directed material transport. Such a directed transport of copper atoms can be caused by a gradient of the chemical potential, e.g. caused by a concentration gradient (interdiffusion), a gradient of the electrical potential, e.g. caused by a directed current (electromigration), temperature gradients (thermomigration) or stress gradients (stress-induced migration). The atomic transport processes and the resulting degradation mechanisms are discussed in detail in Chapter 4 (see also [2.13, 2.28]).

Figure 2.7: Degradation mechanisms in copper via/line structures: a) Cu/cap layer interface diffusion, b) Cu/barrier interface diffusion and diffusion along the surface of the void, c) Grain boundary

e-

Metal 2

Metal 1

Ta-based barrier

Vi SiOx

PEN a)

c) d)

b)