LAB REPORT: BASICS OF VLSI

Experiment 1: SIMULATION OF NMOS AND PMOS date:26-08-2015

Submitted by: RINOOP R. M150205EC JUSTIN K. THOMAS M150190EC SINO V. ANTONY M150411EC

OBJECTIVE: Simulating the input and output characteristics of nMOSFET and pMOSFET and

parameter extraction.

THEORY:

MOSFET is the fundamental building block of digital integrated circuits. It is a four terminal device which operates in three regions, viz, cut-off, linear and saturation.Drain current equation for n-channel MOSFET is,

ID=0 ; (VGS<VTH) for cut-off

ID= μnCoxWL

[(VGS-VTH) VDS - 12

VDS2] ; (VDS<VGS-VTH) for linear region

ID= 12

μnCox WL

(VGS-VTH)2 ; (VDS>VGS-VTH) for saturation region

SOFTWARE TOOL: Cadence Virtuoso

DESIGN CONSIDERATIONS:

nMOS pMOS W=1 µm ; L=1µm W=1 µm ; L=1µm

WL

=1 WL

=1

VDD=1.8 V VDD=1.8 V

SCHEMATICS AND PLOTS:

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Figure 2 schematic - pmosFigure 1 schematic - nmos

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Figure 3 input characteristics - nmos(ID Vs VGS) Figure 4 input characteristics - pmos(ID Vs VGS)

Figure 9 sub-threshold characteristics nmos(log10ID Vs VGS)

Figure 5 output characteristics - nmos(ID Vs VDS) Figure 6 output characteristics - pmos(ID Vs VDS)

Figure 7 Effect of body bias on nmos(ID Vs VGS) Figure 8 Effect of body bias on pmos(ID Vs VGS)

Figure 10 sub-threshold characteristics pmos(log10ID Vs VGS)

OBSERVATIONS AND CALCULATIONS:

Sl.no. Parameter Formula ValuenMOS pMOS

1Threshold Voltage

From the plot graphically

VTH=0.479mV VTH=0.502mV

2Sub-threshold current Ioff

From the plot Ioff=3.427pA Ioff=4.347pA

3Sub-thresholdSlope

𝑠s¿∂V GS

∂ log (I ¿¿DS);¿VDS constant

SS=89.8mV/decade SS=93.12mV/decade

4Transconductance gm(Linear)

gm=∂ ID∂V GS

;

VDS constant

gm= 79.42uVDS=0.5 V

gm= 320.3uVDS= -0.5 V

5Transconductance gm(Saturation)

gm=∂ ID∂V GS

;

VDS constant

gm=310.964uVDS=1.8 V

gm= 473.9uVDS= -1.8 V

6 DIBLDIBL=

V TH 1∨V DS1−V TH 2∨V DS2

V DS1−V DS2

VDS1= 0.09 V

VTH1= 0.434 V

VDS2= 1.8 vVTH2= 0.509 v

DIBL= 44.444 mVV

VDS1= -0.09 V

VTH1= -0.449 V

VDS2= -1.8 vVTH2= -0.552 V

DIBL= 60.23mVV

7Drain conductance gd(Linear)

gd=∂ ID∂V DS

; VGS constant gd =95.97µ ;VGS=.09 V

gd =67.29µVGS=.09 V

8Drain conductance gd(Saturation)

gd=∂ ID∂V DS

; VGS constant gd =3.123µ gd =9.452 µ9

Output resistance r0

rd =1/ gD (Saturation)320.178KΩat VDS=1.8 V

105.8 KΩat VDS=1.8 V

10On resistance ron

rd =1/ gD (Linear)10.419KΩ

at VDS=0.1 V14.86KΩ

at VDS=-0.1 V

INFERENCE:

i. As source to body voltage (VSB) increases, threshold voltage increases.ii. The OFF current of pMOS is greater than that of nMOS.

iii. The output resistance of nMOS is higher than pMOSiv. The On resistance of pMOS is more compared to nMOS.v. As VDS increases leakage current increases.

RESULT:

The input and output characteristics of nMOS and pMOS were simulated using cadence virtuoso tool and plotted. Their typical parameter values have been calculated from the plots.

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