Lab 6: Traffic Light Controller

鄭宇順, chengys@csie.nctu.edu.tw EC616

巫仁傑, jenchieh@csie.nctu.edu.tw EC616

1. Open a new project by issuing “File -> New Project”.

i. Click 下一步

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ii. Click 下一步iii. Click 下一步iv. Click 下一步v. Click 完成

2. Create a new module by issuing “Project > New Source”

Create a verilog file “traffic_light.v” .

(You can copy it from the class handout)

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3. Save the file and issue “Synthesis-> Check syntax” by doubling click.

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4. Create the schematic symbol of the module “traffic_light.v” by doubling click.

5. If no syntax error, create a new verilog module by issuing “Project > New

Source”. Create a verilog file “bc_4b_ce_aclr.v”

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6. Start HDL Editor and create macro for a 4-bit binary counter with a clock enable

and an asynchronous reset inputs.

7. Save the file and issue “Synthesis-> Check syntax” by double click.

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8. Create the schemaric symbol of the module “bc_4b_ce_aclr.v” by doubling click.

9. Create another module named “clk12Hz“ to generate 11.9 Hz clock, check

syntax and then create the symbol of the module “clk12Hz“.

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10. In Project Manager window, issue “Project -> New Source”.

Create a schematic file named “trf_ltc”.

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11. In Schematic Editor window ”Xilinx ESC”, create your design at here.

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12. In addition, assign input and output pads to appropriate pins of the FPGA.

Double click “trf_ltc_pin.ucf”.

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13. Simulate, implement and download your design.

Requirements:A. Design a two-way traffic light controller.

H

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Ggg?HG

F

B. Refer to the FSM as shown in class-handout.

C. Design clock, counter and controller modules using verilog code.

D. The top module must implemented in schematic design, cannot use verilog code.

(Pin connection:)

CAR -> P62

HG -> p5

HY -> p4

HR -> p3

FG- > p9

FY -> p8

FR -> p6

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