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November 2011Revision: EB67_01.0
LatticeXP2 Brevia 2 Development Kit
User’s Guide
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LatticeXP2 Brevia 2 Development KitLattice Semiconductor User’s Guide
IntroductionThank you for choosing the Lattice Semiconductor LatticeXP2™ Brevia 2 Development Kit!
This user’s guide describes how to start using the LatticeXP2 Brevia 2 Development Kit, an easy-to-use platform for evaluating and designing with LatticeXP2 FPGAs. Along with the evaluation board and accessories, this kit includes a pre-loaded Brevia System-on-Chip (SoC) demonstration design based on the LatticeMico8™ microcon-troller.
Note: Static electricity can severely shorten the life span of electronic components.
FeaturesThe LatticeXP2 Brevia 2 Development Kit includes:
• LatticeXP2 Brevia 2 Evaluation Board with the following on-board components and circuits:– LatticeXP2-5E 6TN144C– 2-Mbit SPI Flash memory– 128K by 8-bit SRAM– On-board USB controller for JTAG programming (FTDI - FT2232H)– 2x20 expansion header for general I/O– 1x8 JTAG programming header (unpopulated)– 2x5 expansion header for general I/O– Four debounced general purpose pushbuttons– One debounced reset pushbutton– 4-bit DIP switch (with 3 of 4 switches debounced)– Eight status LEDs
• Pre-loaded Demo – The kit includes a pre-loaded demo design that integrates several Lattice reference designs including the LatticeMico8 microcontroller, SRAM controller, SPI Flash memory controller, and a UART periph-eral.
• USB Mini Cable – For power and JTAG programming.
• LatticeXP2 Brevia 2 Development Kit Web Page — The LatticeXP2 Brevia 2 Development Kit web page on the Lattice web site provides access to the latest documentation, demo designs and drivers for the kit.
The contents of this user’s guide include demo operation, top-level functional descriptions of the various portions of the evaluation board, descriptions of the on-board connectors, switches and a complete set of schematics of the LatticeXP2 Brevia 2 Evaluation Board.
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LatticeXP2 Brevia 2 Development KitLattice Semiconductor User’s Guide
Figure 1. LatticeXP2 Brevia 2 Evaluation Board, Top Side
20x20 Expansion Header LatticeXP2 FPGA
SRAM Memory(128K x 8)
JTAG Interface(Not Populated)
USB MiniInterface
Status LEDs
Push-buttons
2x5Expansion
Header
DIP Switches
Reset Button
LatticeXP2 DeviceThis board features a LatticeXP2 FPGA with a 1.2V core supply. It can accommodate all pin-compatible LatticeXP2 devices in the 144-pin TQFP (20x20 mm) package. A complete description of this device can be found in the LatticeXP2 Family Data Sheet.
Demonstration DesignLattice provides a demo that illustrates key applications of the LatticeXP2 device.
Demo_LatticeXP2_Brevia_SoCThe Demo_LatticeXP2_Brevia_SoC is pre-programmed into the non-volatile Flash memory of the LatticeXP2 FPGA and is operational upon power-up. The design provides the following features:
• Prints the ASCII representation of any characters received by the UART on the eight LEDS (D0-D7).
• Prints the SPI memory ID code on demand.
• Displays the current DIP switch setting on demand.
• Logs Read ID and Read Switch commands, along with their results, into the asynchronous SRAM.
• Stores the contents of the SRAM into the SPI ROM on demand.
• Restores the SRAM contents from the SPI ROM on demand.
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LatticeXP2 Brevia 2 Development KitLattice Semiconductor User’s Guide
The demo design integrates the following Lattice reference designs:
• LatticeMico8 Microcontroller (RD1026)
• WISHBONE UART (RD1042)
• SPI WISHBONE Controller (RD1044)
• LatticeMico8 to WISHBONE Interface Adapter (RD1043)
Firmware running on the LatticeMico8 demonstrates control logic for the peripherals connected to a shared on-chip WISHBONE bus and communication between the LatticeXP2 Brevia 2 Evaluation Board and a host PC connected to the USB cable.
Figure 2. Demo_LatticeXP2_Brevia_SoC Block Diagram
LatticeXP2 Brevia Evaluation Board
LED Bank
UART
SPI SRAM
RS-232, JTAGPC Host
SPI MemoryController
SRAM MemoryController
SPI 2-MbitFlash Memory
SRAM 1-MbitMemory
LatticeMico8
WISHBONE Bus
Switch Bank
LatticeXP2 FPGA
FTDIController
USB
Set Up a VT100/ANSI Terminal EmulatorThe Demo_LatticeXP2_Brevia_SoC preloaded in the LatticeXP2 Brevia 2 Evaluation Board is operated by interact-ing with a monitor program. The monitor program sends and receives data across the RS232 communications port on the LatticeXP2 Brevia 2 Evaluation Board. It is necessary to start and configure a VT100 or ANSI style terminal emulator program like PuTTY, PuTTY Portable, Tera Term Pro (Windows) or Minicom (Linux).
Follow these steps to interact with the monitor program:
1. Connect the Brevia 2 Evaluation Board to your computer using the supplied USB cable.
2. Install the required device drivers
a. Install the FTDI USB driver during the installation of Lattice Diamond or standalone ispVM programming software. If you have already installed Diamond or ispVM without the driver, you can run the Diamond or ispVM installation again and install only the driver.
b. Configure a Virtual COM port driver as described in the FTDI installation guide available on the FTDI web-site.
3. Start a terminal emulation program. The RS232 UART on the LatticeXP2 Brevia Evaluation Board is configured to operate at 115.2bps, 8 data bits, 1 stop bit, no parity, and no flow control.
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LatticeXP2 Brevia 2 Development KitLattice Semiconductor User’s Guide
4. Press the RESET button on the evaluation board.
When configured correctly you will see a banner displayed, like the one shown below.
=========================================================================
Welcome to the LatticeXP2 Brevia Development KitSoC Demonstration Rev 1.0, April 2010
Main Menu------------------------------------------------------------ 0: Re-display Main Menu 1: Read SPI Flash Memory IDCode 2: Read DIP Switch Bank 3: Read Data History from SRAM 4: Copy Data History from SRAM to SPI Flash Memory 5: Read Data History from SPI Flash Memory 6: Write Data to SRAM (Specified Address and Data) 7: Read Data from SRAM (Specified Address) 8: Write Data to SPI (Specified Address and Data) 9: Read Data from SPI (Specified Address) a: SRAM Auto-Test b: SPI Auto-Test
Press 0-b to select an option.=========================================================================
SoC Command Monitor FeaturesThe LatticeXP2 Brevia 2 Evaluation Board, after it powers up or is reset, begins running a command interpreter monitor under the control of the LatticeMico8 microcontroller. The monitor code waits for a keypress and immedi-ately performs the requested function.
When the Read ID and Read Switch Bank commands are executed the ASCII output from the command is stored into the SRAM. The LatticeMico8 stores the next address to write in three of its general purpose registers. After power up the registers are cleared to 0x000000. Commands that have their results logged to the SRAM print out the address of the next available SRAM location.
Read SPI Flash Memory IDCode CommandThe SPI ROM device on the LatticeXP2 Brevia 2 Evaluation Board can be queried and will return the ID code implemented by the ROM manufacturer. The LatticeMico8 initiates memory transactions using the SPI Memory controller to acquire the data.
To scan the SPI Flash Memory IDCode:
1. From the terminal Main Menu, press 1.
The LatticeMico8 performs the manufacturer specific SPI memory transactions to acquire the ID code. The ID number is returned as a hex value. This command logs the result to the SRAM.
Example:
ID:0x44 (SRAM ADDR:0x00006)
Note: The ID for your board may differ.
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LatticeXP2 Brevia 2 Development KitLattice Semiconductor User’s Guide
Read DIP Switch BankThe LatticeMico8 has the ability to read the state of switches 1-4 on the DIP switch bank. The pushbutton switches are can also be read. Each pushbutton press toggles the internal state of a register in the FPGA. The current state of the register is displayed on the high nibble of the output. The hexadecimal representation of the switches is printed and logged to the SRAM. A DIP switch that is set ON has a '0' value, and one that is OFF has a value of '1'.
To read the DIP switch:
1. From the terminal window press 2.
Example:
SW:0x00 (SRAM ADDR:0x0000C)
Read Data History from SRAMUse the Read Data History from SRAM command to see the results from each command that is logged to the SRAM memory. The output from this command does not get written into the SRAM.
To read data history from SRAM:
1. From the terminal window press 3. The transaction log is listed.
Example:
SRAM: 0x44 0x00
Copy Data History from SRAM to SPI Flash MemoryThis command erases a portion of the SPI ROM, and stores the command results logged in the SRAM. The LatticeMico8 starts writing from SRAM address 0x000000 and continues writing values into the SPI ROM until it reaches the last valid entry in the SRAM.
To copy data history from SRAM to SPI Flash memory:
1. From the terminal window press 4. The data log is transferred and the terminal indicates “Done”.
Example:
SRAM => SPI: 0x44 0x00Done.
Read Data History From SPI Flash MemoryThis command copies the Data History from the SPI ROM into the SRAM. After power is supplied, or RESET asserted the SRAM Data History log information is no longer available. Running this command permits the history to be restored from the non-volatile SPI ROM.
To read data history from the SPI ROM into SRAM:
1. From the terminal window press 5. The transaction log is listed.
Example:
SPI Flash: 0x44 0x00
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LatticeXP2 Brevia 2 Development KitLattice Semiconductor User’s Guide
Write Data to SRAM (Specified Address and Data)This command allows you to write a single data value to any location in the SRAM memory space.
1. From the terminal window press 6.Example:Please Enter the Address(17 bits,Hex), eg: 1f26a, no Spaces, then Press ENTER:10000Please Enter the Data(8 bits,Hex), eg: b7, no Spaces, then Press ENTER:93SRAM Write Done.
Read Data from SRAM (Specified Address)This command allows you to read the data value from any address in the SRAM.
1. From the terminal window press 7.Example:Please Enter the Address(17 bits,Hex), eg: 1f26a, no Spaces, then Press ENTER:10000Read Data: 93SRAM Read Done.
Write Data to SPI (Specified Address and Data)This command allows you to write a single data value to any location in the SPI memory space.
1. From the terminal window press 8.Example:Please Enter the Address(18 bits,Hex), eg: 1f26a, no Spaces, then Press ENTER:10000Please Enter the Data(8 bits,Hex), eg: b7, no Spaces, then Press ENTER:93SPI Write Done.
Read Data from SPI (Specified Address)This command allows you to read the data value from any address in the SPI.
1. From the terminal window press 9.Example:Please Enter the Address(18 bits,Hex), eg: 1f26a, no Spaces, then Press ENTER:10000Read Data: 93SPI Read Done.
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LatticeXP2 Brevia 2 Development KitLattice Semiconductor User’s Guide
Perform SRAM Auto-testThis command automatically tests SRAM.
1. From the terminal window press a.Example:> aStarting SRAM Auto-Test................................................................................................................................SRAM Test Done: Successful.
Perform SPI Auto-testThis command automatically tests SPI.
1. From the terminal window press b.Example:>bStarting SPI Auto-Test................................................................................................................................SPI Test Done: Successful.
Download Demo DesignsLattice distributes source and programming files for a variety of demonstration designs compatible with the LatticeXP2 Brevia 2 Evaluation Board.
To download demo designs:
1. Browse to the LatticeXP2 Brevia 2 Development Kit web page of the Lattice web site. Select the Demo Applica-tions download and save the file.
2. Extract the contents of Demo_LatticeXP2_Brevia_Soc_vhdl.zip or Demo_LatticeXP2_Brevia_Soc_verilog.zip to an accessible location on your hard drive. One or more designs will be extracted and each will follow the following basic form.
Demo Directories
Demo1 Demo1 .\project .\source .\LatticeMico8_Vx_y_Verilog .\RD1042 .\project .\source .\RD1043 .\project .\source .\RD1044 .\project .\source .\RD1046 .\project .\source
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LatticeXP2 Brevia 2 Development KitLattice Semiconductor User’s Guide
Where:
• \project – Lattice Diamond® project (.ldf), preferences (.lpf), and programming file (.jed). This directory may con-tain intermediate results of the Diamond build process.
• \source – HDL source for the Diamond project.
• .\LatticeMico8_Vx_y_Verilog – LatticeMico8 Microcontroller Reference Design (RD1026).
• .\RDxxxx – Reference designs integrated by the demo.
Programming a Demo Design with the Lattice Diamond ProgrammerDemo_LatticeXP2_Brevia_SoC is pre-programmed into the LatticeXP2 Brevia Evaluation Board by Lattice. To restore a LatticeXP2 Brevia 2 Evaluation Board to factory settings, use the procedure described below.
To program the LatticeXP2 FPGA:
1. Connect the USB cable to the host PC and the LatticeXP2 Brevia Evaluation Board.
2. From Diamond, click on the Programmer icon. Select Create a new Project from a Scan and browse for the .XCF file to import.
3. Click on Detect Cable. The Programmer will detect the cable (Cable: USB2, Port: FTUSB-0).
4. Click on the Program icon. When complete, PASS is displayed in the Status column.
Recompile a Demonstration Project with Lattice Diamond® Design SoftwareUse the procedure described below to recompile a demo project for the LatticeXP2 Brevia 2 Evaluation Board.
1. Install and license Lattice Diamond software.See www.latticesemi.com/latticediamond for download and licensing information.
2. Download the demo source files from the LatticeXP2 Brevia 2 Development Kit web page.
3. Run Lattice Diamond.
4. Use File > Open Project and open the Diamond <demo>.ldf.
5. From the Process view, select JEDEC File from the Export Files process.
6. Choose Export Files, right-click and choose Run.
After a few moments the JEDEC programming file is output.
7. See the Programming a Demo Design with the Lattice Diamond Programmer section for details on how to download the demo design to the board.
Reassembling the Demo LatticeMico8 FirmwareUse this procedure to reassemble and download changes to the LatticeMico8 microcontroller firmware.
1. Install the LatticeMico8 Tool Code.
Note: The LatticeMico8 tool executables are also provided in the . \Demo_LatticeXP2_Brevia_SoC\LatticeMico8_Vx_y_Verilog\utils directory and. \Demo_LatticeXP2_Brevia_SoC\LatticeMico8_Vx_y_VHDL\utils directory
2. The C source code for the LatticeMico8 Assembler and Simulator is included in the tools package. An optional step you can perform is to compile this source instead of using the pre-compiled versions supplied by Lattice.
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LatticeXP2 Brevia 2 Development KitLattice Semiconductor User’s Guide
3. Modify the Assembly source (.s) file, if desired, and recompile to a memory image (.hex). Source for Demo_LatticeXP2_Brevia_SoC is provided as Demo_LatticeXP2_Brevia_SoC.s. The assembler and simulator are command line applications. The tools display their invocation syntax if they are started without command line parameters.
4. Once the assembly code has been recompiled it is necessary to update the LatticeMico8 PROM contents. The fastest way to update the PROM contents is to use the Diamond Memory Initialization tool. The tool updates the PROM contents without modifying the connectivity of the design.
Launch the Memory Initialization tool, and select the isp8_prom component, choose the new memory initializa-tion file, click on the Apply Changes button, and save the new NCD file.
5. Run the Generate Data File (JEDEC) process.
6. Download the new JED file to the FPGA. You will see the effects of your assembly code changes.
LatticeXP2 Brevia 2 Evaluation BoardThis section describes the features of the LatticeXP2 Brevia 2 Evaluation Board in detail.
OverviewThe LatticeXP2 Brevia 2 Evaluation Board is a complete development platform for the LatticeXP2 FPGA. The board includes on-board SRAM and SPI Flash memory, and SPI microcontroller communication interfaces, a USB port, and an expansion header to support test connections.
Figure 3. LatticeXP2 Brevia 2 Evaluation Board Block Diagram
LatticeXP2LFXP2-5E-6TN144C
2x20Header
2x5Header
USB to JTAG or1x8 JTAG Header
SPI FlashSPI
1 MbitSRAM
DebouncedPushbutton (x4)
DebouncedPushbutton
4-Bit DIP Switch(Debounced except 4-to-5)
8 LEDs
50 MHz Crystal
JTAGProgramming
28
4
8
31
USB to RS232Serial
SerialCommunication
8
4
GPIO
GSRN/IO
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LatticeXP2 Brevia 2 Development KitLattice Semiconductor User’s Guide
I/O Mapping DetailsExpansion Header 1 InterfaceAccess to 40 I/Os are available to the user via the expansion header J3. The connector type is a 2x20 0.100" cen-ter-to-center Berg stick, male. The interface details are included in Table 1.
Table 1. Expansion Header 1 Interface
Expansion ConnectorPin Number
Expansion Connector/FPGAPin Name
FPGAPin Number Pin Functionality
Expansion Connector J3
1 3.3V Power
2 3.3V Power
3 EXP_IO15 103 I/O
4 EXP_IO31 69 I/O
5 EXP_IO14 102 I/O
6 EXP_IO30 66 I/O
7 EXP_IO13 101 I/O
8 EXP_IO29 65 I/O
9 EXP_IO12 100 I/O
10 EXP_IO28 62 I/O
11 EXP_IO11 99 I/O
12 EXP_IO27 61 I/O
13 GND Ground
14 GND Ground
15 EXP_IO10 98 I/O
16 EXP_IO26 116 I/O
17 EXP_IO9 96 I/O
18 EXP_IO25 115 I/O
19 EXP_IO8 94 I/O
20 EXP_IO24 114 I/O
21 EXP_IO7 93 I/O
22 EXP_IO23 113 I/O
23 EXP_IO6 92 I/O
24 EXP_IO22 78 I/O
25 GND Ground
26 GND Ground
27 EXP_IO5 91 I/O
28 EXP_IO21 77 I/O
29 EXP_IO4 90 I/O
30 EXP_IO20 74 I/O
31 EXP_IO3 89 I/O
32 EXP_IO19 73 I/O
33 EXP_IO2 88 I/O
34 EXP_IO18 108 I/O
35 EXP_IO1 87 I/O
36 EXP_IO17 107 I/O
37 GND Ground
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LatticeXP2 Brevia 2 Development KitLattice Semiconductor User’s Guide
Expansion Header 2 InterfaceThe connector is a 10-pin dual-row Berg stick, male. The interface details are included in Table .
Table 2.
Expansion ConnectorPin Number
Expansion Connector Pin Name
FPGA Pin Number Pin Functionality
Expansion Connector J2
1 EXP_IO36 31 I/O
2 3.3V Power
3 EXP_IO37 32 I/O
4 EXP_IO32 27 I/O
5 EXP_IO38 35 I/O
6 EXP_IO33 28 I/O
7 EXP_IO39 36 I/O
8 EXP_IO34 29 I/O
9 GND Ground
10 EXP_IO35 30 I/O
Expansion Header 2 Interface
LEDs and SwitchesEight LEDs, four debounced pushbutton switches and one DIP (4) switch are provided. All DIP switches are debounced except the SW1D connection (4-to-5, #55 on the silkscreen).
Table 3.
LED FPGA Pin Number
D1 46
D2 45
D3 44
D4 43
D5 40
D6 39
D7 38
D8 37
LED Interface
38 GND Ground
39 XP2_RESET 19 Reset
40 EXP_IO16 104 I/O
Table 1. Expansion Header 1 Interface (Continued)
Expansion ConnectorPin Number
Expansion Connector/FPGAPin Name
FPGAPin Number Pin Functionality
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LatticeXP2 Brevia 2 Development KitLattice Semiconductor User’s Guide
Table 4.
Switch FPGA Pin Number
SW1A 58
SW1B 57
SW1C 56
SW1D1 55
SW3 54
SW4 53
SW5 52
SW6 50
1. SW1D is not debounced.
Switch Interface
Flash InterfaceThe LatticeXP2 Brevia 2 Evaluation Board provides 2 Mbits of non-volatile Flash memory. The Flash uses the four-wire SPI communication interface.
Table 5.
Flash Signal Name FPGA Pin Number
FPGA Flash 2 Mbit (U1)
XP2_SPI_CS0 11
XP2_SPI_CLK 13
XP2_SPI_IN 15
XP2_SPI_OUT 16
FLASH_RSTn 17
FLASH_Wn 18
Flash Interface
SRAM InterfaceThe LatticeXP2 Brevia 2 Evaluation Board provides 1Mbit of asynchronous SRAM memory in a 128K x 8-bit config-uration.
Table 6. SRAM Interface
SRAM Signal NameFPGA Pin Number
FPGA SRAM 1 Mbit (U2)
Data_0 1
Data_1 2
Data_2 5
Data_3 6
Data_4 7
Data_5 8
Data_6 9
Data_7 10
Addr_0 119
Addr_1 120
Addr_2 121
Addr_3 122
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LatticeXP2 Brevia 2 Development KitLattice Semiconductor User’s Guide
Please note the JTAG header is not populated by default. It is recommended to use the USB mini cable and on-board USB configuration circuit as described elsewhere in this document.
Table 7. JTAG Programming Interface
JTAG ConnectorPin Number
JTAG ConnectorPin Name
FPGAPin Number
FPGAPin Name Pin Functionality
JTAG Connector J1
1 3.3V — — VCC
2 TDO 82 TDO TDO
3 TDI 80 TDI TDI
4 — — — None
5 — — — None
6 TMS 79 TMS TMS
7 GND — — GND
8 TCK 81 TCK TCK
FPGAThe Lattice XP2 Brevia 2 Evaluation Board is based on the LatticeXP2 non-volatile FPGA. The board is populated with a 5K LUT device in a 144 TQFP package. A complete description of the device can be found in the LatticeXP2 Family Data Sheet and on the LatticeXP2 web page.
Software RequirementsInstall the Lattice Diamond software before you begin developing designs for the evaluation board.
Mechanical SpecificationsDimensions: 3 in (L) x 3 in (W) x 1/2 in (H)
Environmental RequirementsThe evaluation board must be stored between -40° C and 100° C. The recommended operating temperature is between 0° C and 55° C. The evaluation board can be damaged without proper anti-static handling.
Addr_4 123
Addr_5 124
Addr_6 125
Addr_7 127
Addr_8 129
Addr_9 130
Addr_10 131
Addr_11 132
Addr_12 133
Addr_13 134
Addr_14 137
Addr_15 138
Addr_16 141
SRAM_CSb 142
SRAM_OEb 143
SRAM_WEb 144
SRAM Signal NameFPGA Pin Number
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LatticeXP2 Brevia 2 Development KitLattice Semiconductor User’s Guide
GlossaryDIP: Dual In-line Package
FPGA: Field-Programmable Gate Array
LED: Light Emitting Diode
LUT: Look-Up Table
PCB: Printed Circuit Board
RoHS: Restriction of Hazardous Substances Directive
PLL: Phase Locked Loop
SPI: Serial Peripheral Interface
SRAM: Static Random Access Memory
UART: Universal Asynchronous Receiver/Transmitter
WDT: Watchdog Timer
TroubleshootingThe LatticeXP2 Brevia 2 Evaluation Board is not responsive.
• Verify the LatticeXP2 device is programmed.
The functionality displayed by the board does not match the demo features described.It is possible the LatticeXP2 Brevia 2 Evaluation Board has been reprogrammed. You can either reprogram the FPGA with the demonstration bitstream, or read the checksum of the bitstream loaded in the FPGA. To restore the LatticeXP2 Brevia 2 Evaluation Board to the factory default, see the Download Demo Designs section of this docu-ment for details on downloading and reprogramming the device.
You can use Diamond Programmer to read the checksum of the bitstream programmed into the FPGA. This value can be compared against the checksum stored in the JEDEC file. The JEDEC file checksum value is the last line in the file. This may allow you to determine the contents of the FPGA.
A final option is to use Diamond Programmer to read the current bitstream in the FPGA, and then to reprogram the FPGA with your desired bitstream.
Ordering Information
Description Ordering Part NumberChina RoHS Environment-Friendly
Use Period (EFUP)
LatticeXP2 Brevia 2 Development Kit LFXP2-5E-B2-EVN
Technical Support AssistanceHotline: 1-800-LATTICE (North America)
+1-503-268-8001 (Outside North America)e-mail: [email protected]: www.latticesemi.com
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LatticeXP2 Brevia 2 Development KitLattice Semiconductor User’s Guide
Revision HistoryDate Version Change Summary
November 2011 01.0 Initial release.
(c) 2011 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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LatticeXP2 Brevia 2 Development KitLattice Semiconductor User’s Guide
Appendix A. SchematicsFigure 4. LatticeXP2 Brevia 2 Evaluation Board Block Diagram
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
USB CON
USB to JTAG / RS232
LEDs and Switches
OSC 50MHz
FPGA
SRAM
FLASH
Exp Header Exp Header
JTAG
Battery and
Power from USB 5V
BANK 7 BANK 6
BANK 3BANK 2
BANK 0
BANK 1
BANK 4
BANK 5
LFXP2-5E-TN144RS232
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LatticeXP2 Brevia 2 Development KitLattice Semiconductor User’s Guide
Figure 5. USB to JTAG/RS232
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3 3
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ent N
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rR
ev
Dat
e:S
heet
of
AX
EL
SY
S
LF
XP
2-5E
-B2-
EV
NA
Latti
ce X
P2
Bre
via
2 E
valu
atio
n B
oard
-US
B to
JT
AG
/RS
232
B
25
Thu
rsda
y, D
ecem
ber
09, 2
010
R1
5k1
DN
I
R1
5k1
DN
I
L1
600o
hm 5
00m
A
L1
600o
hm 5
00m
A12
R13
10k
R13
10k
C14
18pF
C14
18pF
R9
5k1
R9
5k1
C9
0.1u
F
C9
0.1u
F
C10
10uF
C10
10uF
R7
0R
70
R2
5k1
DN
I
R2
5k1
DN
I
R14
2k2
R14
2k2
FTD
I Hig
h-S
peed
US
B
F
T223
2H
FT22
32H
L
U1
FTD
I Hig
h-S
peed
US
B
F
T223
2H
FT22
32H
L
U1
VR
EG
IN50
VR
EG
OU
T49
DM
7
DP
8
RE
F6
RE
SE
T#
14
EE
CS
63
EE
CLK
62
EE
DA
TA
61
OS
CI
2
OS
CO
3
TE
ST
13
AD
BU
S0
16
AD
BU
S1
17
AD
BU
S2
18
AD
BU
S3
19
VPHY4
VPLL9
VCORE12
VCORE37
VCORE64
VCCIO20
VCCIO31
VCCIO42
VCCIO56
AGND10
GND1
GND5
GND11
GND15
GND25
GND35
GND47
GND51P
WR
EN
#60
SU
SP
EN
D#
36
AD
BU
S4
21
AD
BU
S5
22
AD
BU
S6
23
AD
BU
S7
24
AC
BU
S0
26
AC
BU
S1
27
AC
BU
S2
28
AC
BU
S3
29
AC
BU
S4
30
AC
BU
S5
32
AC
BU
S6
33
AC
BU
S7
34
BD
BU
S0
38
BD
BU
S1
39
BD
BU
S2
40
BD
BU
S3
41
BD
BU
S4
43
BD
BU
S5
44
BD
BU
S6
45
BD
BU
S7
46
BC
BU
S0
48
BC
BU
S1
52
BC
BU
S2
53
BC
BU
S3
54
BC
BU
S4
55
BC
BU
S5
57
BC
BU
S6
58
BC
BU
S7
59
X1
12M
HZ
X1
12M
HZ
11
33
G1
2G
24
C6
0.1u
F
C6
0.1u
F
R10
12k
1%R
1012
k1%
C13
18pF
C13
18pF
93LC
56-S
O8
U2
93LC
56-S
O8
U2
CS
1
CLK
2
DI
3
DO
4V
SS
5O
RG
6N
U7
VC
C8
C11
0.1u
F
C11
0.1u
F
R3
5k1
DN
I
R3
5k1
DN
I
C1
4u7
C1
4u7
1 2
C3
4u7
C3
4u7
1 2
R6
0R
60
C4
0.1u
F
C4
0.1u
F
C7
0.1u
F
C7
0.1u
F
L2
600o
hm 5
00m
A
L2
600o
hm 5
00m
A12
R11
10k
R11
10k
R5
0R
50
C2
0.1u
F
C2
0.1u
F
R8
0R
80
R4
5k1
R4
5k1
C5
0.1u
F
C5
0.1u
F
R12
10k
R12
10k
C12
0.1u
F
C12
0.1u
F
J1
head
er_1
x8D
NI
J1
head
er_1
x8D
NI
11
22
33
44
55
66
77
88
C8
0.1u
F
C8
0.1u
F
19
LatticeXP2 Brevia 2 Development KitLattice Semiconductor User’s Guide
Figure 6. Memory, LEDs, Switching
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
SPI Flash
����
�
SRAM
Switches
LEDs
GLOBAL RESET
Add
r_0
Add
r_1
Add
r_2
Add
r_3
Add
r_4
Add
r_5
Add
r_6
Add
r_7
Add
r_8
Add
r_9
Add
r_10
Add
r_11
Add
r_12
Add
r_13
Add
r_14
Add
r_15
Add
r_16
Dat
a_0
Dat
a_1
Dat
a_3
Dat
a_4
Dat
a_5
Dat
a_6
Dat
a_7
Dat
a_2
STATUS_LED6
STATUS_LED7
STATUS_LED5
STATUS_LED4
STATUS_LED3
STATUS_LED2
STATUS_LED0
STATUS_LED1S
W0
SW
1
SW
2
SW
3
SW
4
SW
5
SW
6
SW
7
SW
_RE
SE
TS
W_R
ES
ET
+3.
3V
+3.
3V+
3.3V
+3.
3V
+3.
3V
+3.
3V
FLA
SH
_RS
Tn
4F
LAS
H_W
n4
XP
2_S
PI_
CS
04
XP
2_S
PI_
CLK
4
XP
2_S
PI_
OU
T4
XP
2_S
PI_
IN4
Add
r_[0
:16]
4D
ata_
[0:7
]4
ST
AT
US
_LE
D[0
:7]
4
SR
AM
_WE
b4
SR
AM
_CS
b4
SR
AM
_OE
b4
XP
2_R
ES
ET
4
XP
2_S
W0
4X
P2_
SW
14
XP
2_S
W2
4X
P2_
SW
44
XP
2_S
W5
4X
P2_
SW
64
XP
2_S
W7
4R
ES
ET
4
XP
2_S
W3
4
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
AX
EL
SY
S
LF
XP
2-5E
-B2-
EV
NA
Latti
ce X
P2
Bre
via
2 E
valu
atio
n B
oard
- M
em, L
ED
s, S
w
B
35
Thu
rsda
y, D
ecem
ber
09, 2
010
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
AX
EL
SY
S
LF
XP
2-5E
-B2-
EV
NA
Latti
ce X
P2
Bre
via
2 E
valu
atio
n B
oard
- M
em, L
ED
s, S
w
B
35
Thu
rsda
y, D
ecem
ber
09, 2
010
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
AX
EL
SY
S
LF
XP
2-5E
-B2-
EV
NA
Latti
ce X
P2
Bre
via
2 E
valu
atio
n B
oard
- M
em, L
ED
s, S
w
B
35
Thu
rsda
y, D
ecem
ber
09, 2
010
R18
470
R18
470
21
C16
0.1u
F
C16
0.1u
F
R30
2k2
R30
2k2
R19
470
R19
470
21
SW
1A
SW
_SP
ST
_4D
IP_L
P
SW
1A
SW
_SP
ST
_4D
IP_L
P1
8
D1
Red
D1
Red
1 2
SW
1B
SW
_SP
ST
_4D
IP_L
P
SW
1B
SW
_SP
ST
_4D
IP_L
P2
7
D7
Red
D7
Red
1 2
U5
MA
X68
18
U5
MA
X68
18OU
T1
19IN
12
GN
D10
Vcc
20E
N1
IN2
3
IN3
4
IN4
5
IN8
9IN
78
IN6
7IN
56
OU
T2
18
OU
T3
17
OU
T4
16
OU
T5
15
OU
T6
14
OU
T7
13
OU
T8
12
CH
11
SW
1C
SW
_SP
ST
_4D
IP_L
P
SW
1C
SW
_SP
ST
_4D
IP_L
P3
6
C15
0.1u
F
C15
0.1u
F
SW
1D
SW
_SP
ST
_4D
IP_L
P
SW
1D
SW
_SP
ST
_4D
IP_L
P4
5 SW
3
SP
ST
-NO
SW
3
SP
ST
-NO
14
2 3
R26
2k2
R26
2k2
C18
0.1u
F
C18
0.1u
F
U3
SS
T25
VF
020-
20-4
C-S
AE
U3
SS
T25
VF
020-
20-4
C-S
AE
S1
Q2
W3
Vss
4
Vcc
8
D5
C6
Res
et7
D2
Red
D2
Red
1 2
D8
Red
D8
Red
1 2
R27
2k2
R27
2k2
SW
2
SP
ST
-NO
SW
2
SP
ST
-NO
14
2 3
R15
470
R15
470
21
SW
6
SP
ST
-NO
SW
6
SP
ST
-NO
14
2 3
D3
Red
D3
Red
1 2
R20
470
R20
470
21
R17
470
R17
470
21
R21
470
R21
470
21
R16
470
R16
470
21
R28
2k2
R28
2k2
U4
IDT
71V
124S
A15
TY
G8
U4
IDT
71V
124S
A15
TY
G8
A0
1
A1
2
A2
3
A3
4
IO2
10
WE
12
A7
16
A16
32A
1531
A14
30
CS
15
IO7
27IO
626
IO5
23IO
422
A12
21A
1120
A10
19
A8
17
A5
14A
413
IO0
6
IO1
7
A9
18
IO3
11
A13
29
GN
D25
VC
C24
A6
15
OE
28
GN
D9
VC
C8
D4
Red
D4
Red
1 2
R31
10k
R31
10k
C19
0.01
uF
C19
0.01
uF
SW
5
SP
ST
-NO
SW
5
SP
ST
-NO
14
2 3
R24
2k2
R24
2k2
R29
2k2
R29
2k2
D5
Red
D5
Red
1 2
R32
0R32
0
R23
2k2
R23
2k2
C17
0.1u
F
C17
0.1u
F
SW
4
SP
ST
-NO
SW
4
SP
ST
-NO
14
2 3
R25
2k2
R25
2k2
D6
Red
D6
Red
1 2
R22
470
R22
470
21
20
LatticeXP2 Brevia 2 Development KitLattice Semiconductor User’s Guide
Figure 7. FPGA Banks
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
ST
AT
US
_LE
D7
ST
AT
US
_LE
D0
ST
AT
US
_LE
D1
ST
AT
US
_LE
D2
ST
AT
US
_LE
D3
ST
AT
US
_LE
D4
ST
AT
US
_LE
D5
ST
AT
US
_LE
D6
EX
P_I
O[1
:31]
Add
r_0
Add
r_1
Add
r_2
Add
r_3
Add
r_4
Add
r_5
Add
r_6
Add
r_7
Add
r_9
Add
r_10
Add
r_11
Add
r_12
Add
r_13
Add
r_14
Add
r_15
Add
r_16
EX
P_I
O27
EX
P_I
O28
EX
P_I
O29
EX
P_I
O30
EX
P_I
O31
EX
P_I
O1
EX
P_I
O19
EX
P_I
O20
EX
P_I
O21
EX
P_I
O2
EX
P_I
O22
EX
P_I
O3
EX
P_I
O4
Add
r_8
EX
P_I
O5
EX
P_I
O6
EX
P_I
O7
EX
P_I
O8
EX
P_I
O9
EX
P_I
O10
EX
P_I
O11
EX
P_I
O12
EX
P_I
O13
EX
P_I
O14
EX
P_I
O15
EX
P_I
O16
EX
P_I
O17
EX
P_I
O18
EX
P_I
O23
EX
P_I
O24
EX
P_I
O25
EX
P_I
O26
EX
P_I
O16
EX
P_I
O17
EX
P_I
O6
EX
P_I
O18
EX
P_I
O7
EX
P_I
O19
EX
P_I
O20
EX
P_I
O21
EX
P_I
O8
XP
2_R
ES
ET
EX
P_I
O22
EX
P_I
O23
EX
P_I
O9
EX
P_I
O10
EX
P_I
O24
EX
P_I
O25
EX
P_I
O11
EX
P_I
O12
EX
P_I
O13
EX
P_I
O14
EX
P_I
O15
EX
P_I
O27
EX
P_I
O28
EX
P_I
O29
EX
P_I
O30
EX
P_I
O31
EX
P_I
O26
EX
P_I
O1
EX
P_I
O5
EX
P_I
O2
EX
P_I
O3
EX
P_I
O4
Dat
a_0
Dat
a_6
Dat
a_5
Dat
a_4
Dat
a_3
Dat
a_1
Dat
a_7
Dat
a_2
EX
P_I
O33
EX
P_I
O34
EX
P_I
O35
EX
P_I
O36
EX
P_I
O37
EX
P_I
O38
EX
P_I
O39
EX
P_I
O32
EX
P_I
O33
EX
P_I
O34
EX
P_I
O35
EX
P_I
O[3
2:39
]
EX
P_I
O36
EX
P_I
O37
EX
P_I
O38
EX
P_I
O39
EX
P_I
O32
+3.
3V
+3.
3V+
3.3V
+3.
3V+
3.3V
+3.
3V
+3.
3V+
3.3V
+3.
3V
+3.
3V+
3.3V
ST
AT
US
_LE
D[0
:7]
3
XP
2_S
W7
3
RS
232_
Rx_
TT
L2
RS
232_
Tx_
TT
L2
Add
r_[0
:16]
3
SR
AM
_CS
b3
SR
AM
_OE
b3
SR
AM
_WE
b3
XP
2_R
ES
ET
3
XP
2_S
W6
3X
P2_
SW
53
XP
2_S
W4
3X
P2_
SW
33
XP
2_S
W2
3X
P2_
SW
13
XP
2_S
W0
3
Dat
a_[0
:7]
3
FLA
SH
_RS
Tn
3F
LAS
H_W
n3XP
2_S
PI_
CS
03
XP
2_S
PI_
CLK
3X
P2_
SP
I_IN
3X
P2_
SP
I_O
UT
3
RE
SE
T3
DT
Rn
2
CT
Sn
2R
TS
n2
DS
Rn
2D
CD
n2
XO
UT
5X
IN5
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
AX
EL
SY
S
LF
XP
2-5E
-B2-
EV
NA
Latti
ce X
P2
Bre
via
2 E
valu
atio
n B
oard
- F
PG
A B
anks
B
45
Thu
rsda
y, D
ecem
ber
09, 2
010
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
AX
EL
SY
S
LF
XP
2-5E
-B2-
EV
NA
Latti
ce X
P2
Bre
via
2 E
valu
atio
n B
oard
- F
PG
A B
anks
B
45
Thu
rsda
y, D
ecem
ber
09, 2
010
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
AX
EL
SY
S
LF
XP
2-5E
-B2-
EV
NA
Latti
ce X
P2
Bre
via
2 E
valu
atio
n B
oard
- F
PG
A B
anks
B
45
Thu
rsda
y, D
ecem
ber
09, 2
010
C21
0.1u
F
C21
0.1u
F
C25
0.01
uF
C25
0.01
uF
C24
0.1u
F
C24
0.1u
F
C29
0.01
uFC29
0.01
uF
C27
0.1u
F
C27
0.1u
F
BANK 3
BANK 2
LFXP
2-5E
-6TN
144C
U6-
3
BANK 3
BANK 2
LFXP
2-5E
-6TN
144C
U6-
3
PR
24A
73
PR
24B
74
VC
CIO
376
PR
14B
77
PR
14A
78
PR
12B
87
PR
12A
88
PR
11B
89
PR
11A
90
PR
10B
91
PR
9B92
PR
10A
93
PR
9A94
VC
CIO
495
PR
8B96
PR
8A98
PR
7B99
PR
6B10
0
PR
7A10
1
PR
6A10
2
PR
5B10
3
PR
5A10
4
VC
CIO
510
5
PR
2B10
7
PR
2A10
8
GN
DIO
375
GN
DIO
497
GN
DIO
510
6
BANK 5
BANK 4
LFXP
2-5E
-6TN
144C
U6-
4
BANK 5
BANK 4
LFXP
2-5E
-6TN
144C
U6-
4
PB
8A37
PB
7A38
PB
8B39
PB
7B40
VC
CIO
642
PB
13B
43
PB
13A
44
PB
15A
45
PB
14A
46
PB
15B
47
PB
14B
48
VC
CIO
749
PB
16A
50
PB
16B
52
PB
17A
53
PB
17B
54
PB
18A
55
PB
19A
56
PB
18B
57
PB
19B
58
PB
20A
61
PB
20B
62
VC
CIO
863
PB
26A
65
PB
26B
66
PB
27A
69
PB
28A
70
PB
27B
71
PB
28B
72
GN
DIO
641
GN
DIO
751
GN
DIO
864
J3 Hea
der2
x20
J3 Hea
der2
x20
2 4 6 8 10 12 14 16 18 20 2422 26 28 30 32 34 36 38 4039373533312927252321191715131197531
BANK 1
BANK 0
LFXP
2-5E
-6TN
144C
U6-
2
BANK 1
BANK 0
LFXP
2-5E
-6TN
144C
U6-
2
PT
28B
109
PT
28A
110
VC
CIO
011
2
PT
21B
113
PT
20B
114
PT
21A
115
PT
20A
116
PT
19B
119
PT
19A
120
PT
18B
121
PT
17B
122
PT
18A
123
PT
17A
124
PT
16B
125
PT
16A
127
VC
CIO
112
8
PT
15B
129
PT
14B
130
PT
15A
131
PT
14A
132
PT
13B
133
PT
13A
134
VC
CIO
213
6
PT
9B13
7
PT
9A13
8
PT
7B14
1
PT
8B14
2
PT
7A14
3
PT
8A14
4
GN
DIO
011
1G
ND
IO1
126
GN
DIO
213
5
J2 head
er 2
x5
J2 head
er 2
x5
1 3 5 7 9
2 4 6 8 10
C28
0.01
uF
C28
0.01
uF
C26
0.1u
F
C26
0.1u
F
C22
0.01
uF
C22
0.01
uF
C30
0.1u
F
C30
0.1u
F
C31
0.1u
F
C31
0.1u
F
C20
0.1u
F
C20
0.1u
F
C23
0.1u
F
C23
0.1u
F
BANK 7
BANK 6
LFXP
2-5E
-6TN
144C
U6-
5
BANK 7
BANK 6
LFXP
2-5E
-6TN
144C
U6-
5
PL2
A1
PL2
B2
VC
CIO
104
PL5
A5
PL5
B6
PL6
A7
PL6
B8
PL7
A9
PL7
B10
PL8
A11
PL8
B13
VC
CIO
914
PL9
A15
PL1
0A16
PL9
B17
PL1
0B18
PL1
1A19
PL1
1B20
PL1
2A21
PL1
2B22
PL1
5A27
PL1
4A28
PL1
5B29
PL1
4B30
PL1
6B31
PL1
6A32
VC
CIO
1133
PL2
5A35
PL2
5B36
GN
DIO
103
GN
DIO
912
GN
DIO
1134
21
LatticeXP2 Brevia 2 Development KitLattice Semiconductor User’s Guide
Figure 8. Power/JTAG
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
JTAG
50MHz OSC
This is optional
to enable or
disable the
crystal.
+3.
3V
+3.
3V
+3.
3V
VB
US
_5V
VB
US
_5V
VB
US
_5V
+1.
2V
+1.
2V
+1.
2V
+3.
3V
+3.
3V+
3.3V
DM
2D
P2
TD
O2
TD
I2
TM
S2
TC
K2
XO
UT
4
XIN
4
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
AX
EL
SY
S
LF
XP
2-5E
-B2-
EV
NA
Latti
ce X
P2
Bre
via
2 E
valu
atio
n B
oard
- P
ower
/ JT
AG
B
55
Thu
rsda
y, D
ecem
ber
09, 2
010
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
AX
EL
SY
S
LF
XP
2-5E
-B2-
EV
NA
Latti
ce X
P2
Bre
via
2 E
valu
atio
n B
oard
- P
ower
/ JT
AG
B
55
Thu
rsda
y, D
ecem
ber
09, 2
010
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
AX
EL
SY
S
LF
XP
2-5E
-B2-
EV
NA
Latti
ce X
P2
Bre
via
2 E
valu
atio
n B
oard
- P
ower
/ JT
AG
B
55
Thu
rsda
y, D
ecem
ber
09, 2
010
C46
0.01
uF
C46
0.01
uF
C56
0.1u
FC
560.
1uF
R35
1KR35
1K
C41
0.1u
F
C41
0.1u
F
C40
1uF
C40
1uF
L4
600o
hm 5
00m
A
L4
600o
hm 5
00m
A12
C37
0.1u
F
C37
0.1u
F
C42
0.1u
F
C42
0.1u
F
C43
0.1u
F
C43
0.1u
FC
48
10uF
C48
10uF
C33
1uF
C33
1uF
C44
0.1u
F
C44
0.1u
F
C47
0.01
uF
C47
0.01
uF
R34
10k
DN
I
R34
10k
DN
I
C36
0.1u
F
C36
0.1u
F
C35
0.1u
F
C35
0.1u
F
U8
NC
P11
17
U8
NC
P11
17
GN
D
1
IN3
OU
T2
TA
B4
X2
CB
3LV
-3C
-50M
0000
X2
CB
3LV
-3C
-50M
0000
EN
1
GN
D2
Out
put
3
Vcc
4
C52
0.1u
F
C52
0.1u
F
R33
10k
R33
10k
C34
0.1u
F
C34
0.1u
F
C39
10uF
C39
10uF
D9
Gre
enD
9G
reen
1 2
LFXP
2-5E
-6TN
144C
U6-
1
LFXP
2-5E
-6TN
144C
U6-
1
VC
CA
UX
123
VC
C1
24
VC
C2
59
VC
CA
UX
260
VC
C3
84
VC
CA
UX
385
VC
CA
UX
411
7
VC
C4
118
TO
E25
CF
G0
26
LRC
_VC
CP
LL1
67
ULC
_VC
CP
LL3
140
GN
D86
LRC
_GN
DP
LL2
68
ULC
_GN
DP
LL4
139
C51
22uF
C51
22uF
L5 600o
hm 5
00m
A
L5 600o
hm 5
00m
A
1 2
R36
0R36
0
C49
22uF
C49
22uF
C45
0.01
uF
C45
0.01
uF
C50
10uF
C50
10uF
C32
10uF
C32
10uF
R37
0R
370
C38
0.01
uF
C38
0.01
uF
JTAG
LFXP
2-5E
-6TN
144C
U6-
6
JTAG
LFXP
2-5E
-6TN
144C
U6-
6
TM
S79
TD
I80
TC
K81
TD
O82
VC
CJ
83
U7
FA
N11
12U
7F
AN
1112
GND1
Out
put
2In
put
3
Tab
4
J4
SK
T_M
INIU
SB
_B_R
A
J4
SK
T_M
INIU
SB
_B_R
A
VC
C1
D-
2
D+
3
ID4
GN
D5
C55
0.1u
F
C55
0.1u
F
L3
600o
hm 5
00m
A
L3
600o
hm 5
00m
A12
C54
0.01
uF
C54
0.01
uF
C53
0.1u
F
C53
0.1u
F
22
LatticeXP2 Brevia 2 Development KitLattice Semiconductor User’s Guide
Appendix B. Bill of MaterialsTable 8. Bill of Materials
Item Quantity Reference Description ManufacturerManufacturer Part Number
1 2 C1,C3 Cap Cer 4.7uF 6.3V 10% X5R 0603 Panasonic ECJ-1VB0J475K
2 33
C2, C4, C5, C6, C7, C8, C9, C11, C12, C15, C16, C17, C18, C20, C21, C23, C24, C26, C27, C30, C31, C34, C35, C36, C37, C41, C42, C43, C44, C52, C53, C55, C56
CAP CERAMIC 0.1UF 16V X7R 0402 Kemet C0402C104K4RACTU
3 5 C10, C32, C39, C48, C50 CAP CECAP CER 10UF 10V X5R 20% 0603 Taiyo Yuden LMK107BJ106MALTD
4 2 C13, C14 CAP CER 18PF 25V C0G 0402 Kemet C0402C180K3GACTU
5 10 C19, C22, C25, C28, C29, C38, C45, C46, C47, C54
CAP CERAMIC 10nF 16V 5% X7R 0402 Kemet C0402C103J4RACTU
6 2 C33, C40 CAP CERAMIC 1uF 6.3V X5R 0402 Kemet C0402C105K9PACTU
7 2 C49, C51 CAP CERAMIC 22uF 10V X5R 0805 Taiyo Yuden LMK212BJ226MG-T
8 8 D1, D2, D3, D4, D5, D6, D7, D8
LED SUPER RED CLEAR 0603 SMD LITE-On INC LTST-C190KRKT
9 1 D9 LED SUPER GREEN CLEAR 0603 SMD LITE-On INC LTST-C190KGKT
11 1 J2 CONN HEADER 10POS .100" SMT Align TIN Samtec TSM-105-01-T-DV-A
12 1 J3 Header 2x10 .100 20POS Align VER Samtec TSM-120-01-T-DV-A-P
13 1 J4 CONN MINI USB RCPT RA TYPE B SMD Neltron 5075BMR-05-SM-CR
14 5 L1, L2, L3, L4, L5 Ferrite Bead 600ohm@100MHz 500mA 0603 Murata BLM18AG601SN1D
16 2 R4, R9 Res 1/16W 5.1K 1% 0402 Yageo RC0402FR-075K1L
17 7 R5, R6, R7, R8, R32, R36, R37 Res 1/10W 0.0 Ohm 5% 0603 Yageo RC0603JR-070RL
18 1 R10 Res 1/16W 12.0K 1% 0402 Yageo RC0402FR-0712KL
19 5 R11, R12, R13, R31, R33 Res 1/16W 10.0K 1% 0402 Yageo RC0402FR-0710KL
20 9 R14, R23, R24, R25, R26, R27, R28, R29, R30 Res 1/16W 2.2K 1% 0402 Yageo RC0402FR-072K2L
21 8 R15, R16, R17, R18, R19, R20, R21, R22 Res 1/16W 470R 1% 0402 Yageo RC0402FR-07470RL
23 1 R35 Res 1/16W 1.0K 1% 0402 Yageo RC0402FR-071KL
24 1 SW1 SWITCH DIP SPST SEALED 4POS SMD C&K Components SD04H1SB
25 5 SW2, SW3, SW4, SW5, SW6
SWITCH TACT 6MM MOM SMD H=5.0MM C&K Components PTS645SH50SMTRLFS
26 1 U1 USB to UART / FIFO FTDI FT2232HL
27 1 U2 IC 93LC56 EEPROM Microchip 93LC56C-I/SN
28 1 U3 SPI Flash 256Kx8 20Mhz SST / Microchip SST25VF020-20-4C-SAE
29 1 U4 SRAM 128Kx8, 15ns IDT IDT71V124SA15TYG8
30 1 U5 CMOS Switch Debouncer Octal Maxim MAX6818EAP+
23
LatticeXP2 Brevia 2 Development KitLattice Semiconductor User’s Guide
31 1 U6 FPGA XP2 Lattice LFXP2-5E-6TN144C
32 1 U7 IC REG LDO 1A 1.2V SOT-223 Fairchild Semi FAN1112SX
33 1 U8 IC Reg LDO 3.3V SOT-223 On Semi NCP1117ST33T3G
34 1 X1 12Mhz Crystal TXC 7M-12.000MAAJ-T
35 1 X2 OSC 50MHz 3.3V 50ppm CTS CB3LV-3C-50M0000
Table 8. Bill of Materials (Continued)
Item Quantity Reference Description ManufacturerManufacturer Part Number
