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Freescale Semiconductor Confidential and Proprietary Information. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2005.
TM
LeAF: A Leakage- Aware Floorplanner
Aseem GuptaProf. Nikil Dutt
Prof. Fadi KurdahiKamal Khouri, Ph.D.Magdy Abadir, Ph.D.
Slide 1
As VT is decreased to maintain noise margins and to meet frequency demands, the leakage current will increase leading to excessive battery draining.
0%
10%
20%
30%
40%
50%
2000 2002 2004 2006 2008
Leak
age
Pow
er (%
of T
otal
)
Source: Borkar, De Intel®
Year 2002 2005 2008 2011 2014
Power supply Vdd (V) 1.5 1.2 0.9 0.7 0.6Threshold VT (V) 0.4 0.4 0.35 0.3 0.25
…and phones leaky!
Why worry about power? – Leakage Power
Slide 2
Leakage Power
• Leakage power is more than 50% of the total power in many chips.
• Major component of leakage power is sub-threshold current. • Sub-threshold leakage current is sensitive to temperature.• Leakage power of an industrial core at 65nm:
• Leakage power more than doubles with a 20ºC increase in the temperature of the die.
Leakage Power (% of Total Power)Core
85 ºC
Worst (0.9V) 20% 46%
Typical (1.0V) 17% 40%400 MHz
Best (1.1V) 25% 53%
105 ºCCase (Voltage)
Source: Freescale Semiconductor®
Slide 3
• Power densities are increasing with smaller geometries leading to increased chip temperatures.
• Temperature difference across a SoC can be as high as 50ºC.
• The heat of a IP-block is not confined to itself and effects other blocks also:
Thermal DiffusionHeat flows from high temperature block to low temperature blocks.
• Floorplan of SoC affects temperatures of the IP-blocks.
Thermal Characteristics of a Chip
Slide 4
Thermal Diffusion
Power Densities
• Alpha 21364 Core with gcc benchmark
0.623
0.137
[Moritz, Koren]
Temperatures
85.3
73.5
Power densities don’t necessarily map to temperatures
Slide 5
Temperature & Floorplans
• Thermograms for 2 floorplans of the same SoC look different.• Significant temperature gradients across the SoC (45ºC in right floorplan).• Leakage power (Temperature dependent) for the two floorplans is different
by about 10%.
Slide 6
Problem Definition
• Given:Leakage power is highly dependent on temperature.
Different blocks in a SoC are at different temperatures. The effect of thermal diffusion is very significant.
There is an interdependency between SoC floorplan, temperature, and leakage power
• How much is the impact of SoC floorplans on the leakage power?
• Can we optimize SoC floorplans for thermal-aware leakage power ?
Slide 7
Traditional Floorplanning
Candidate Floorplan
Estimate Area and Wire Delay
Simulated Annealing done? Generate moreCandidateFloorplans
Y
N
Output Floorplan with lowestvalue of cost function
Evaluate Cost Function
Slide 8
Leakage Aware Floorplanning
Candidate Floorplan
Estimate Area and Wire Delay
Estimate Floorplan- &Temperature- Aware
Leakage Power[using STEFAL]
Simulated Annealing done? Generate moreCandidateFloorplans
Y
N
+
Output Floorplan with lowestvalue of cost function
Evaluate Cost Function
Minimum changes in any existing floorplanner’s optimization algorithm
Slide 9
LeAF
Leakage Aware Floorplanner (LeAF)
Output Temperature- Dependent Leakage Aware Floorplan
ThermalProperties of Chip’s Package
Temperature vs. Leakage Power
Tables for Different Types of Transistors
Dynamic Power For Each
Block in SoC
Netlist of the SoC with Areas of Blocks,
Aspect Ratio Range, Connectivity List of Blocks
Input SoC Design
TransistorComposition
of each Blockin the SoC
A design has many different types of transistors (n,p /h,l,svt).
Thermal resistivity, thermal capacitance etc. Leakage of each type of transistor has
different sensitivity to temperature.
Slide 10
Cost Function
• All floorplanners’ output is optimized for a Cost Function.
• Traditional floorplanner’s Cost Function = ƒ(Area, Wire Length)
• Cost Function of Leakage Aware Floorplanner = ƒ(Area, Wire Length, Leakage Power)
• Leakage Aware Floorplanner additionally optimizes floorplans for temperature dependent leakage power which is estimated using STEFAL.
• Each parameter in the Cost Function has respective weights. Sum of all weights = 1.
Slide 11
Thermal- vs. Leakage- Aware Floorplanning
• Related work focused on thermal-aware floorplanning:Optimizes floorplans for peak temperature> objective is to reduce the peak temperature of a SoC
Peak temperatures affect package design, reliability etc. Reduction of peak temperatures ‘may or may not’ reduce the leakage power It is different from leakage aware floorplanning.
• Leakage-aware floorplanning:Optimizes floorplans for leakage power> objective is to reduce the leakage power of a SoC
Slide 12
Thermal- vs. Leakage- Aware Floorplanning• Peak temperature and leakage of different floorplans • No definite correlation between peak temperature and
leakage power
Slide 13
Positive feedback between Leakage & Temperature
Power Dissipated by
Package
Leakage Power Stable Operating Point: Stable
Temperature and Leakage Power
Temperature
Pow
erD
ynam
ic BD
AC
Temperature
Point of Thermal Runaway
Room
Dynamic Power +
Pow
er
During temperature dependent leakage estimation, this positive feedbackcannot be ignored.
Slide 14
STEFAL
• System Level Temperature- and Floorplan- Aware Leakage Power Estimator
• Estimates the leakage power of a SoC:Considers the candidate floorplan of the SoCConsiders the actual temperature profile of the SoCConsiders positive feedback between leakage and temperature
15
Blocks’Transistor
Composition
Temperature vs. Leakage
PowerTables
Calculate Temperature -Aware Leakage Power
Blocks’ Dynamic Power Profile
ComputeTotal Power
Estimate Floorplan-Aware
Blocks’Temperature
Profile
Floorplan Steady Temperatures
Reached?
Output Floorplan-& Temperature-
Aware Leakage Power
Y
N
Initial Leakage Power @ 27˚C
Leakage PowerBlocks’
Floorplan-AwareTemperature Profile
Properties of Chip’s Thermal
Package
Blocks’Temp. less than
Thermal run-away Temp.?
N
Y
EXIT
Leakage Estimation
with STEFAL
16
Blocks’Transistor
Composition
Temperature vs. Leakage
PowerTables
Calculate Temperature -Aware Leakage Power
Blocks’ Dynamic Power Profile
ComputeTotal Power
Estimate Floorplan-Aware
Blocks’Temperature
Profile
Floorplan Steady Temperatures
Reached?
Output Floorplan-& Temperature-
Aware Leakage Power
Y
N
Initial Leakage Power @ 27˚C
Leakage PowerBlocks’
Floorplan-AwareTemperature Profile
Properties of Chip’s Thermal
Package
Blocks’Temp. less than
Thermal run-away Temp.?
N
Y
EXIT
Inputs
Output
Leakage Estimation
with STEFAL
17
Blocks’Transistor
Composition
Temperature vs. Leakage
PowerTables
Calculate Temperature -Aware Leakage Power
Blocks’ Dynamic Power Profile
ComputeTotal Power
Estimate Floorplan-Aware
Blocks’Temperature
Profile
Floorplan Steady Temperatures
Reached?
Output Floorplan-& Temperature-
Aware Leakage Power
Y
N
Initial Leakage Power @ 27˚C
Leakage PowerBlocks’
Floorplan-AwareTemperature Profile
Properties of Chip’s Thermal
Package
Blocks’Temp. less than
Thermal run-away Temp.?
N
Y
EXIT
Leakage Estimation
with STEFAL
Slide 18
Leakage Aware Floorplanning
Candidate Floorplan
Estimate Area and Wire Delay
Estimate Floorplan- &Temperature- Aware
Leakage Power[using STEFAL]
Simulated Annealing done? Generate moreCandidateFloorplans
Y
N
+
Output Floorplan with lowestvalue of cost function
Evaluate Cost Function
Slide 19
Results: Design - I
0
10
20
30
40
50
60
70
1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0
Weight of Leakage Power in Cost Function
Inac
tive
Are
a (%
of A
ctiv
e A
rea)
oO
utpu
t Flo
orpl
an
0
0.5
1
1.5
2
2.5
3
3.5
Nor
mal
ized
Lea
kage
Pow
er o
f O
utpu
t Flo
orpl
an
Inactive Area (%) Leakage Power
Inactive Area of the floorplan (as a % of Active Area)
Normalized Leakage Power of the floorplans
•Leakage power variation: 190%!•Even floorplans with 20% Inactive Area show a variation of 84% !•All the floorplans shown in the results meet wire length constraints.
Slide 20
Effect of the Positive Feedback Loop
• Run STEFAL on a floorplan and report leakage power numbers for each iteration.
Iteration Number of STEFAL Output Leakage Power1 X2 X + 19.8%3 X + 24.9%4 X + 26.3%5 X + 26.7%6 X + 26.9%7 X + 26.9%
• Emphasizes the importance of considering the positive feedback loop to reach steady state temperatures.
Slide 21
Conclusion
• Temperature sensitivity of leakage power cannot be ignored.
• Thermal diffusion has very significant impact on the block temperatures.
• Different floorplans have different temperature profiles different floorplans have different leakage power
• SoC floorplans need to be optimized for leakage power.
• Design cost of leakage aware floorplanning is minimal.
• Leakage aware floorplanning has only 4% runtime overhead compared to traditional floorplanning.