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2. Types

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Some Typ

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8086

80286

80386EX

80486D

Pentium

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t the 808

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note that 8atible wit 80386, 8tructions

neral‐purppose microd micropare some e

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addresses

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Example

Solution:

10

Example2

Solution:

In

8 /2=

4 /2=

2 /2=

1 /2=

0 /2=

0 /2=

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Table 1:

1: Evaluat

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1.012

2: Evaluat

:

nteger

0 (LS

0

0

1 (M

0

0

1000

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= 5.25

te the bina

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0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

cimal equi

0(21) + 1(2

0(2) + 1(1)

1 + 0 + 0.2

ary repres

0.87

0.75

0.5

0

0

0

1000.111

decimal reBinary

0

1

10

11

100

101

110

111

1000

1001

1010

1011

1100

1101

1110

1111

ivalent of

20) + 0(2‐1

+ 0(0.5) +

25

sentation o

Fr

75 x2=

5 x2=

x2=

x2=

x2=

x2=

1

epresentatHexadecim

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

binary nu

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+ 1(0.25)

of decima

raction

= 1

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.11

tion of somal

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al number

(MSB)

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11

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Generally

8‐bit

16‐bit

32‐bit

Example3evaluate

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called

called

called

3: Evaluaits hexade

:

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numbers a

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are expres

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10710

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ed length

sentation

0112 = 6BH

either:

of decim

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1. Interna

The inter(BIU) andthe sameindepend

The BIU fetching, inputtingplace ovaddress b

The BIU prefetch

The EU isunit (ALUregisters.

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al Archite

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g or outpuer the sybus, and th

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cture 2

ecture of t

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2- Softw

the 8086

the 8086 t (EU). Eacel processe Fig. 1

performing of datta for inps. This bus needed t

g 1: Execut

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ware Ar

contains tch unit hasing make

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tion and b

s instructicode.

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bus interfa

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ting instrupurpose r

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s operatiomemory, aerals. Thebidirectioover the b

ace units

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Software A

LectureBy

f 8086

ts: the busons and bxecution o

ons, such ddress ge

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eue permi

contains aand temp

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2. Memo

8086 canstored ataccess ansignifican

Example storage value 0000001016 16‐bit woto 0000D

The wordaddress. its least sFig 3. To storesignificanFig 4.

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ory addres

n supportst consecutiny two connt byte of

1: For thelocation 0001112=7contains ord 225A1

D16 .

d of data It’s also csignificant

double nt byte sto

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ss space a

s 1Mbyte otive addrensecutive the word,

e 1Mbyteof addres716 , whilethe value

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word fouore at an a

3 Aligned aaligned wo

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of externaesses over bytes as a, and the h

e memory ss 00009e the locae 011111d in the lo

even‐addrned wordn odd ad

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and ord

organizatio

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ocations 0

ress bound. The wordress. It’s

ons are nhat is a mu

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n Fig 2, ns the ddress . The 000C16

dary if itsrd of datas also calle

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Fig 4misalign

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s least sig is at an oed misalig

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00

000

000

000

000

00

00

00

Fig2:P

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Software A

LectureBy

individuato FFFFF16dressed bmost sign

gnificant bodd‐addregned word

le word , 416, 816,..

009 0

00A

00B

00C 5

00D 2

00E

000F

010 7

Part of 1M

and e word

Architecture o


al bytes of. The 8086byte is the ificant byt

byte is in ess boundd, as show

that it’s ...) as show

07

5A

22

7D

Mbyte mem

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even ary if wn in

least wn in

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3. Segme

Even thotime. ActEach seglowest ad

Only fourdata segmsegment ES(extra addresse

Note thatchange th

There is

reside on

while the

segment

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ent registe

ugh the 8tually, thegment is address byt

r of these ment, andregisterssegment)d byte of

t the segmheir conte

one restr

n a 16‐by

e segmen

register c

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8086 has ae 1Mbytesassigned ate‐storage

64Kbyte sd extra segs: CS (cod. These rethe segme

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riction on

te addres

nt register

content to

Fig 5: S

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segments gment. Thde segmeegisters coent (see F

sters are ugh softwa

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evaluate

Software

egmentati

address sory are paddress tha).

are activehe addresent), SS (sontain a 16Fig 5).

user accesare.

e assigne

ary. This i

s 16 bits.

the segm

model of

on

space, notartitioned at identifi

e a time: tses of thestack seg6‐bit base

sible. This

ed to a se

s because

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ent startin

8086 micr

t all this minto 64Kbies its sta

the code sese four segment), Daddress t

s means th

egment as

e the mem

ts (0000)

ng addres

roprocess

Software A

LectureBy

memory isbyte (65,5arting poin

segment, segments aDS (data sthat points

hat the pr

s base ad

mory add

must be

ss.

or

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ogramme

ddress: it

ress is 20

added to

of 8086

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ment, n four and owest

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must

0 bits

o the

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Example

CS = 0009

data segm

4. Instruc

Instructioof instructhe offset

The offseinstructio

5. Data R

The 8086

destinatio

Notice thcount regeither asbyte‐wid

CS

DS

SS

ES

0

0

1

3

Segme

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2:Let the

9H, DS = 0

ment are o

ction Poin

on pointerction codet of the ne

et in IP is con code (C

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6 has fou

on of an o

hat they agister(C), as a wholee data ope

0009H

0FFFH

10E0H

3281H

ent register

d Systems Enors

segment

0FFFH, SS =

overlappe

Fig 6

nter

r (IP): is a e to be fetext word o

combined CS:IP).

r general‐

operand d

re referreand the de (16 bitserations.

rs

gineering

registers

= 10E0, an

ed while ot

6: Overlap

16 bits in tched fromof instruct

with the c

‐purpose

uring arith

ed to as thdata regists) for wo

00090

0FFF0

20E00

32810

FFFFF

00000

be assigne

nd ES = 32

ther segm

ped and d

length anm the currtion code

current va

data regi

hmetic an

he accumuter (D). Eaord data

ed as follo

281H. We

ments are d

disjointed

d identifieent code sinstead of

alue in CS

ister, whic

d logic op

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ow:

note here

disjointed

segments

es the locasegment of its actua

to genera

ch can be

perations (

ster (A), thf these rens or as

Code segm(64kbyte)

Data segm(64kbyte)

Stack segm(64kbyte)

Extra segm(64kbyte)

Software A

LectureBy

e that code

d (see Fig 6

s

ation of thof memorl address.

ate the ad

e used as

(see Fig 5)

he base reegisters catwo 8‐bit

ment

ment

ment

ment

1Mbyte m

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6).

he next wory, it conta.

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the sourc

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egister (B)an be accet register

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memory un

of 8086

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F

6. Pointe

The 8086two index

An offsesegment

Unlike thaccessed

Threg

Thadd

7. Status

The statuimpleme

1. Thesigres

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Fig 7: (a) G

er and Inde

6 has fourx registers

t address base addr

he genera as words

e stack pgister (SS)

e source idresses fo

Register

us registernted (see

e carry flagnificant bset.

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ex Registe

other gesDI and SI

represenress in a s

al‐purpose(16 bits).

pointer (SP to access

ndex (SI) or instruct

r also callFig 8). Six

ag (CF): Cbit of the r

gineering

urpose dat

ers

neral‐purp. These ar

ts the dispegment re

e data re

P) and bas memory

and destitions that

ed flag rex of theses

CF is set iresult dur

ta Registe

pose regisre used to

placemenegister.

egisters, t

ase pointelocations

nation indaccess da

egister: iss are statu

if there isring the ex

ers, (b) ded

sters, twoo store wh

t of a stor

the pointe

er (BP) awithin th

dex (DI) arta stored

16‐bit regusflags:

s a carry‐oxecution o

dicated re

pointer rat are call

rage locat

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re used we stack se

re used win the dat

gister with

out or a of an inst

Software A

LectureBy

egister fun

registers Sled offset

ion in me

ndex regis

with the segment.

ith DS or ta segmen

h only nin

borrow‐inruction. O

Architecture o


nctions

SP and BPaddresses

mory from

sters are

stack seg

ES to genent of mem

e bits tha

n for the Otherwise

of 8086

f 10 . Fawwaz

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only

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erate ory.

at are

most FF is

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2. Thepaod

3. Thehigbyt

4. TheOt

5. Theres

6. Theran

The othe

1. TheWhspeTh

2. Theintign

3. Thestrdeadd

The 8086to alter tsaving, lo 8. Genera

In

off

Seg

ES)

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e parity frity‐ that d, PF is ree auxiliarygh nibble te in a 16‐e zero flaherwise, Ze sign flasult is a nee overflownge. If the

r three im

e trap flaghen in thecial serviis type of e interruperrupt (INnored and e directioring operacrement dress to lo

15 1

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ating a me

8086, log

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gment ad

).

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flag(PF): Pis, if it coeset. y flag (AFor a borro‐bit word. ag (ZF): ZZF is resetg (SF): Thegative nuw flag (OF result is n

mplemente

g(TF): if TFe single‐sice routineoperationpt flag (IF)NT) input, the mask

on flag (Dations withe addreow addres

14 13 12

s instructince in whmanipula

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ddress is 1

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PF is set intains an

): AF is seow‐in froOtherwisZF is set . he MSB oumber of rF): When Onot out of

ed flag bit

F is set, thstep modee that man is very us): For the the IF fla

kable interF): The loill occur. ess; theress.

2 11 10

OF DF

Fi

ons withinhich the ption flags

dress

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16‐bit data

if the reseven num

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f the resureset if it iOF is set, f range, OF

s are calle

he 8086 goe, it execay determseful for d8086 to rg must berrupt interogic level When s

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0 9 8

F IF TF

ig 8: Flag r

n its instrrogram is.

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ult produmber of b

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ult is copis positiveit indicateF remains

ed control

oes into thcutes an iine the efdebuggingrecognize e set. Wherface is disof DF deet, the sstring da

7 6

SF ZF

register

uction set executed

ombining

ne of the s

uced by thits at the

‐out frominto the

duced by

ied into S. es that th reset.

flags:

he single‐sinstructionffect of exg programmaskableen IF is resabled. etermines string insata transf

5 4 3

AF

t that are d. Also it c

two parts

segment r

Software A

LectureBy

he instruc1 logic le

the low nlow nibbl

an instru

SF. Thus, S

e signed r

step moden and thexecuting ts. e interrupteset, reque

the directructions fers proce

2 1 0

PF C

able to ucontains in

s: Segmen

registers (

Architecture o


ction has evel. If par

nibble intoe of the l

uction is

SF is set i

result is o

e of operaen jumps he instruc

t requestsests at INT

ction in wautomat

eed from

0

CF

use status nstruction

nt address

CS, SS, DS

of 8086

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zero.

f the

out of

ation. to a

ction.

sat its T are

which tically high

flags ns for

s and

S and

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Off

and

To

Example then map

Solution:

Log Ph

Example then map

Solution:

Log Ph

Actually, memory.

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fset addre

d BP). Also

express t

1 Multi

2 Add it

3: if CS =p it to Phy

gical addr

ysical add

4: if CS =p it to Phy

gical addr

ysical add

many dif

Offset IP BP DI SI orBX

SegmeCS SS DS orES

d Systems Enors

ess is 16‐b

o it could

he 20‐bit

iply Segme

t to the of

F

= 002AH, aysical addr

ess = 00

dress = ( CS

= 002BH, aysical addr

ess = 00

dress = ( CS

fferent log

value:

nt Register:

gineering

bit data fr

be base re

PhysicalA

ent registe

fset(see F

ig 9: Gene

and IP = 0ress.

CS:IP2A : 0023 S X 10H )

and IP = 0ress.

CS:IP2B : 0013 S X 10H )

gical addre

om one o

egister BX

Address of

er by 10H

Fig 9)

erating a M

0023H, wr

+ IP = 00

0013H, wri

+ IP = 00

esses map

of the inde

X.

f memory

( or shift

Memory A

rite the lo

02A0 +002

ite the log

02B0 +001

p to the s

ex and poi

it to left b

Address

gical addr

23 = 002C3

gical addr

13 = 002C3

same phys

Software A

LectureBy

inter regis

by four bit

ressthat t

3

ess that t

3

sical addr

Architecture o


sters (DI, S

)

hey repre

hey repre

ess locati

Physical

addresses a

identical he

of 8086

f 10 . Fawwaz

SI, SP

esent,

esent,

on in

re

ere !

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9. The sta

The stac

informati

a softwar

SS

SP

Da

Th

Th

Th

PO

PU

Wh

Wh

Example and after

PUPOPO

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ack

k is impl

ion such a

re point of

register p

and BP po

ta transfe

e first add

e last add

e address

OP instruct

USH instruc

hen a woro the vao and thhen a woro the coo then t

5: let AX=r the execuUSH AX OP BX OP AX

d Systems Enors

emented

as data an

f view as 3

points to t

oints to th

erred to an

dress in th

ress in the

(SS:SP) is

tion is use

ction is us

rd is to be alue of SPhen the co

rd is to be ontents arthe value o

=1234H ,Sution of n

gineering

in the m

d address

32Kwords

he lowest

he address

nd from th

e Stack se

e Stack se

called Top

ed to read

sed to writ

pushed oP is first auontents of

popped fre first moof SP is fir

Fig 10: St

S=0105H ext progra

memory a

ses. The st

s (see Fig 1

t address w

s within st

he stack a

egment (S

gment (SS

p of Stack

wordfrom

te word to

onto the toutomaticaf the regist

rom the tooved out thrst automa

ack segme

and SP=00am instruc

and it is

tack is 64K

10).

word in th

tack

re word‐w

S : 0000) i

S : FFFE) is

k.

m the stac

o the stac

op of the slly decremter writte

op of the he stack toatically inc

ent of me

006H. Fig ctions:

used for

Kbytes lon

he stack

wide, not

is called E

s called Bo

ck.

k.

stack: mented byn into the

stack the o the speccremented

mory

11 shows

Software A

LectureBy

r tempora

ng and is o

byte‐wide

End of Stac

ottom of S

y two e stack.

cific registd by two.

s the state

Architecture o


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Stack.

ter

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University of


10. InputThe 8086space is impleme64Kbyte a

SS

SP

BX

SS

SP

BX

AX

AX

f Technology


t and Outp6 has sepathe pla

nted. Notiaddresses

0105

0006

5D00

0105

0006

1234

(a) Initial s

(c) After ex

1234

1234

d Systems Enors

put addrearate memce wheretice that ths; therefor

01054

01055

01056

01057

01050

01051

01052

01053

01058

01059

0105A

0105B

01054

01055

01056

01057

01050

01051

01052

01053

01058

01059

0105A

0105B

tate

xecution of

gineering

Fig 11PU

ess spacemory and e I/Ointehis addresre only 16

4

5

6

7

0

1

2

3

8

9

A

B

55

1F

DF

DD

02

00

C0

52

90

68

A2

55

4

5

6

7

0

1

2

3

8

9

A

B

34

12

DF

DD

02

00

C0

52

90

68

A2

55

POP BX

USH and PO

input/outrfaces, suss range is6 bits of ad

SS

SP

BX

SS

SP

BX

AX

AX

OP instruc

tput (I/O) uch as ps form 000ddress are

0105

0004

5D00

0105

0008

1234

(b) After

(d) Afte

1234

DDDF

ction

address sprinter an00H to FFFe needed t

0105

0105

0105

0105

0105

0105

0105

0105

0105

0105

0105

0105

0105

0105

0105

0105

0105

0105

0105

0105

0105

0105

0105

0105

r execution

er execution

Software A

LectureBy

spaces. Thnd monitFFH. This rto address

54

55

56

57

50

51

52

53

58

59

5A

5B

34

12

DF

DD

02

00

C0

52

90

68

A2

55

54

55

56

57

50

51

52

53

58

59

5A

5B

34

12

DF

DD

02

00

C0

52

90

68

A2

55

of PUSH AX

n of POP AX

Architecture o


he I/O adtor ports,represents I/Ospace

X

X

of 8086

f 10 . Fawwaz

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University of


Problems1. Wh2. Ho3. List4. Wh

8085. Wh

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s hat are thow large ist the elemhat is the 86? hich part struction ome two dlculate thmbers area) A000 b) ? : 14Dc) D765 d) ? : CDthe curren0016 ANDstruction fthe curren0016 , resp

d Systems Enors

e length os the instruments of thmaximum

of the 8of a progradedicated he value oe hexadec: ? =A012DA =235D: ? =DABC21 =32D2nt values D 01AC16 fetch?. nt values ipectively, w

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Software A

Lecture By

s?

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be used

r. hat follow

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k pointer aof the sta

Architecture o

2 – Page 10oy Mr.WaleedF

ven time i

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are C0001ack?

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1. Introd

Pro

Eac

Proby

A p

Ma

A s

In ins

Ins

Op

Eac

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Ins

As

2. The MO Th

808

Exelocins

Fig

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uction to

ogram is a

ch comma

ograms mthe micro

program w

achine cod

single mac

assemblystead of w

struction c

pcodeiden

ch opcode

perands det the oper

struction s1. Data t2. Arithm3. Logici4. String5. contro6. Procesan examp

OV instru

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ecution ocation to struction a

g 1The MO

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Lec

assembly

a sequence

and in a pr

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can be div

tify the op

e is assign

escribe thration spe

set includetransferinmetic instrinstructiong manipulaol transferssor contr

ple for inst

uction

nstructionction set.

of this insa destin

and the va

OV instruc

destina

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cture 3-

y language

e of comm

rogram is

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machine l

ded using

guage instr

e, each ind 1s

ided into

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ed a uniqu

e data thaecified by t

es structionsructions ns ation instrr instructiorol instruc

tructions,

n is one o

truction tnation localid source

ction and

ation varia

- Addre

e program

mands use

s an instru

ed in mach

language i

g 0s and 1s

ruction ca

nstruction

two parts

that is to b

ue letter c

at are to bthe opcod

s

ructions ons tions.

next sect

f the inst

transfers cation. Fige and dest

the valid s

ations

essing M

mming

ed to tell a

uction

hine langu

is often re

s

an take up

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s : its opco

be perform

combinati

be processde.

ion discus

ructions i

a byte org 1 showtination va

source an

MODES

a microcom

uage befor

eferred to

one or m

ibed with

odeand op

med.

on called

sed as the

sses the M

n the dat

r a word ws the geariations.

d

LectuBy

S

mputer wh

re they ca

as machin

more bytes

alphanum

erands

a mnemo

e micropro

MOV instru

ta transfe

of data feneral fo

Addressing

ure 3 – Page 1y Mr.WaleedF

hat to do.

an be exec

ne code.

s of code

meric sym

nic.

ocessor ca

ction.

r group o

from a sormat of

Modes

of 8 . Fawwaz

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ource MOV

University

DepartmenThird Year

3.AddreA3W2

of Technology

nt of Control and Sy‐ Microprocessors

essing modesAn addressing 3.1 Register opWith register 2belowshows t

ystems Engineering

mode is a meperand addresoperand addthe memory a

g

ethod of specifssing mode dressing modand registers b

Fig 2

fying an opera

de, the operabefore and aft

M

(a) before fet

and. The 8086

and to be acter the executMOV AX, BX

ching and exe

6 addressing m

ccessed is sption of instructX

ecution (b) afte

modes categor

pecified as retion:

er execution

A

L B

rized into thre

esiding in an

Addressing Modes

Lecture 3 – Page 2oBy Mr.WaleedFaww

ee types:

internal reg

of 8 waz

gister.Fig

University

DepartmenThird Year

3Wm

of Technology


3.2 ImmediateWith Immediamemory locati

ystems Engineering

e operand addte operand aon. Fig 3below

g

dressing modeaddressing mowshows the m

Fig 3(

e ode, the opermemory and re

M

(a) before fetc

rand is part oegisters beforeMOV AL, 15

ching and exe

of the instruce and after th5H

cution (b) afte

ction instead e execution o

er execution

A

L B

of the contenf instruction:

Addressing Modes


nts of a regis

of 8 waz

ster or a

University

DepartmenThird Year

3thth

of Technology


3.3 Memory Ohe physical adhe operand is

3.3.1 Dimemory

ystems Engineering

Operand addrddress of the calculated frorect addressiy and registers

g

essing modesoperand and om a segmentng: the values before and a

Fig 4 (a

s: the 8086 usthen initiate t base addresse of the effecafter the execu

a) before fetch

se this modeta read of wris (SBA) and anctive address ution of instruMOV CX,

hing and execu

to reference ate operation n effective addis encoded duction: [1234H]

ution (b) after

an operand inof this storagdress (EA). Thiirectly in the

r execution

A

L B

n memory.Thee location. Ths mode includ instruction.

Addressing Modes


e 8086 must che physical addes five types:Fig 4belowsh

of 8 waz

calculate dress of : ows the

University

DepartmenThird Year

of Technology


3.3.2 Re(BX), basand afte

ystems Engineering

egister indirecse pointer (BPer the executio

g

ct addressing: P) or an indexon of instructi

Fig 5(a)

this mode is x register (SI oon:

before fetchin

similar to the or DI) within t

MOV AX

ng and execut

direct addresthe 8086. Fig

, [SI]

ion (b) after e

ssing but the o5belowshows

execution

A

L B

offset is specifs the memory

Addressing Modes


fied in a base y and register

of 8 waz

register s before

University

DepartmenThird Year

Note thinstead

Note th

of Technology


3.3.3 Bacontentsafter the

hatif BP is usedof DS.

hatThe displace

ystems Engineering

ased addressis of either bae execution of

d instead of BX

ement could be

g

ng: this modease register BXf instruction:

Fig 6(a) X, the calculati

e 8 bits or 16 bi

e, the effectivX of Base poi

before fetchinon of the phys

its

ve address is inter register

MOV [BX]+

ng and executsical address is

obtained by BP. Fig 6belo

1234H, AL

ion (b) after es performed us

adding a direowshows the

execution sing the conten

A

L B

ect or indirectmemory and

nts of the stack

Addressing Modes


t displacemenregisters bef

k segment (SS)

of 8 waz

nt to the fore and

) register

University

DepartmenThird Year

Note th

of Technology


3.3.4 Indaddress and regi

hatThe displace

ystems Engineering

dexed addresis obtained bsters before a

ement could be

g

ssing: this moby adding the and after the e

Fig 7(a) e 8 bits or 16 bi

ode, work in displacementexecution of in

before fetchinits

similar mannt to the value nstruction:

MOV AL, [

ng and execut

ner to that ofin an index r

SI]+1234H

ion (b) after e

f the based aegister (SI or

execution

A

L B

addressing moDI). Fig 7belo

Addressing Modes


ode but the eowshows the

of 8 waz

effective memory

University

DepartmenThird Year

Note thinstead

Note th

of Technology


3.3.5 Ba8belows

hatif BP is usedof DS.

hatThe displace

ystems Engineering

ased‐Indexed shows the mem

d instead of BX

ement could be

g

addressing: mory and regi

Fig 8 (a) X, the calculati

e 8 bits or 16 bi

this mode coisters before a

MO

before fetchinon of the phys

its

ombines the and after the eV AH, [BX

ng and executsical address is

based addresexecution of i][SI]+1234

tion (b) after es performed us

ssing mode anstruction: 4H

execution sing the conten

A

L B

nd indexed a

nts of the stack

Addressing Modes


addressing m

k segment (SS)

of 8 waz

ode. Fig

) register

University of


Lec

Objective

1. Da

Example

Solution:

DS

AX

f Technology


cture 4

e: 1. 2.

3. 4. S5. ‐‐‐‐

ata transfe(a) MOV i

(b) XCHG

Fig 1

1:For the

:

0100

3000

d Systems Enors

4- 8086

Data tranArithmetiLogic instrShift instrRotate ins‐‐‐‐‐‐‐‐‐‐‐‐‐er instructnstruction

Instruct

(a) XCHG

figure be

01007

01006

01005

01004

01003

01002

01001

01000

B

gineering

6 progra

cosfer instruc instructiructions ructions structions‐‐‐‐‐‐‐‐‐‐‐‐‐tions n

G data tran

low. Wha

XCH

7

6

5

4

3

2

1

0

34

12

DF

DD

90

68

A2

55

Before

808

ammin

omputauctions tions

‐‐‐‐‐‐‐‐‐‐‐‐‐

nsfer instr

t is the re

HG AX ,

86 programmi

g-Integ

ations

‐‐‐‐‐‐‐‐‐‐‐‐‐

ruction (b

sult of exe

[0002]

DS 010

AX 906

ng ‐ Integer in

ger inst

‐‐‐‐‐‐‐‐‐‐‐‐‐‐

) Allowed

ecuting th

0

8

Afte

nstructions an

LecBy

truction

‐‐

d operand

he followin

01007

01006

01005

01004

01003

01002

01001

01000

er

nd computatio

cture 4 – Pagey Mr.WaleedF

ns and

s

ng instruct

34

12

DF

DD

30

00

A2

55

ons e 1of 4 Fawwaz

tion?

University of


Mnem

XLAT

Example

Solution:

Example

Solution:

DS

AX

BX

f Technology


(c) XLAT

monic M

T

2: For the

:

(d) LEA, LD

3: For the

:

SI= (DI) +

DS

SI

DI

AX

BX

0100

xx03

0040

d Systems Enors

Meaning

ranslate

Fig

e figure be

DS, and LE

Fig 3 (a)

e figure be

( BX) + 2H

0100

F002

Before

0020

0003

0040

01047

01046

01045

01044

01043

01042

01041

01040

Before

gineering

Format

XLAT

g 2 (a) XLA

elow, wha

ES instruc

LEA, LDS a

elow, wha

LEA SI

H = 0062H

7

6

5

4

3

2

1

0

34

12

DF

DD

90

68

A2

55

808

((AL) +

AT data tra

t is the re

XLAT

ctions

and LES d

t is the re

, [ DI

H

86 programmi

Opera

(BX) + (DS

ansfer ins

sult of exe

T

ata transf

esult of exe

I + BX +

DS 010

AX xx90

BX 004

ng ‐ Integer in

ation

S) *10) A

truction

ecuting th

fer instruc

ecuting th

+2H]

A

DS

SI

DI

AX

BX

0

0

Afte

0

nstructions an

LecBy

Fl

AL no

he followin

ction

he followin

After

0100

0062

0020

0003

0040

01047

01046

01045

01044

01043

01042

01041

01040

er

nd computatio


ags affect

one

ng instruct

ng instruct

34

12

DF

DD

90

68

A2

55

ons e 2of 4 Fawwaz

ted

tion?

tion?

University of


For these

all or any

Example

Solution:

Example

Instru

LEA SI , [

LEA SI , [

LEA BP , [

LEA AX , [

LEA DI , [

LEA DI , [

LEA CS , [

LEA IP , [

LEA AX , [

LEA AL , [

Example LEA BP,MOV BP,MOV BP,

DS 0

SI

B

DI 0

AX 0

BX 0

f Technology


e threeins

y various c

Fig 4T

4: For the

: SI= (DI) +

5 :

ction Sam

BX + SI +

BX + SI ]

[ 890C ]

[ BX + SI +

BP + DI +

DI + DI +

[ BP + DI +

BP +550C

[ CX + DI +

[ DI + 103

6:What is, [F004, F004 , [F004

0100

F002

Before

0020

0003

0040

d Systems Enors

structions

combinatio

The three

e figure be

(BX) +2H

mple

55 ] V

V

v

+ 20 ] V

+ 55 ] V

55 ] N

+ 55 ] N

C ] N

+ 1D ] N

D ] N

s the resul4]

4]

01047

01046

01045

01044

01043

01042

01041

01040

gineering

(LEA, LDS

ons of the

e element

elow, whaLEASI

= 0062H

Valid

Valid

valid

Valid

Valid

Not valid b

Not valid b

Not valid b

Not valid b

Not valid b

lt after exe

34

12

DF

DD

90

68

A2

55

808

S and LES)

e three ele

816

used to c

t is the re, [ DI

SI= BX

SI= BX

BP= 8

AX = B

DI = B

because EA

because d

because d

because EA

because d

ecuting ea

86 programmi

) the effec

ements in

compute a

esult of exe+ BX +

X + SI + 55

X + SI

890C

BX + SI + 2

BP + DI + 5

A doesn’t

estination

estination

A doesn’t

estination

ach one of

DS 010

SI 006

DI 002

AX 000

BX 004

ng ‐ Integer in

ctive addr

Fig 4

an effectiv

ecuting th+2H]

Res

5

20

55

involve D

n cant be s

n cant be i

involve C

n must be

f the next

After

00

62

20

03

40

nstructions an

LecBy

ress could

ve addres

he followin

ult

DI twice

segment r

instruction

CX

16 bit

instructio

01047

01046

01045

01044

01043

01042

01041

01040

nd computatio


d be forme

s

ng instruct

register

n pointer

ons?

34

12

DF

DD

90

68

A2

55

ons e 3of 4 Fawwaz

ed of

tion?

University of


Solution:

InsLEA BP,MOV BP,MOV BP,

The instrRegister

2. AriThe 808except s

Addition

ADD AL

ADD BX

ADD BX

AdditionExample Wh Wh Wh

Solution:

Th

If B

DS

SS

DI

AX

BX

BP

f Technology


:

truction , [F004, F004 , [F004

uction LESinstead of

ithmetic i

86 microprsegment r

n must oc

,BL

, SI

, CL

n can occu7: For thehat is the hat is the hat is the

:

EA= [ DIPA = (DS ×Memory wAX=AX+90

e address

BPused in

0100

0200

0020

0003

0040

Be

0040

d Systems Enors

4] The

The4] The

Dat

S is similarf Data Seg

nstruction

rocessor cregister ( C

cur betwe

ur betweee figure beresult of eaddressinPA if BP re

I+ BX +× 10H) + word stor067

ing mode

the EA, th

0106

0106

0106

0106

0106

0106

0106

0106

efore

gineering

e value F0

e value F0

e wordatta Segme

r to the ingment Reg

n

can perforCS, DS, ES,

een simila

en registerelow, executing g mode foegister useADDAX

+2H] =[00EA = 1000ed at loca

for this in

hen PA = (

67

66

65

64

63

62

61

60

34

12

DF

DD

90

67

A2

55

808

004 will be

004 will be

memory nt) will be

struction gister

rm additio, and SS) a

r sizes

V

V

N

r and mem

the followor this insted instead, [ DI

020 + 00400H +0062Hation 1062

nstruction

SS × 10H)

86 programmi

Re

e assigned

e assigned

locationse assigned

LDS excep

on operatiand instru

Valid

Valid

Not Valid

mory

wing instrutruction?d of BX reg+ BX +

0 + 02H ]=H= 1062H2H is 9067

is Based

+ 0062 =

DS 0

SS 0

DI 0

AX 9

BX 0

BP 0

ng ‐ Integer in

esult

to the Ba

to the Ba

s F004 an to Base P

pt that it lo

on betweuction poin

(different

uction?

gister? +2H]

0062H

Indexed m

= 2000H +

Aft

0100

0200

0020

906A

0040

0040

nstructions an

LecBy

ase Pointe

ase Pointe

d F005 ( Pointer

oad the Ex

en any twnter (IP).

t sizes)

mode.

+0062H= 2

01067

01066

01065

01064

01063

01062

01061

01060

ter

nd computatio


er

er

in the cu

xtra Segm

wo register

2062H

7

6

5

4

3

2

1

0

34

12

DF

DD

90

67

A2

55

ons e 4of 4 Fawwaz

urrent

ment

rs

University ofDepartment Third Year ‐ M

Thcon

(S)

AD

Example

locations

store the

Solution:

f Technology of Control anMicroprocesso

8086 p

(a) Ad

e instructntent of th

+ (D) + (C

DC is prima

8: let

200 and 3

e result at

: MOV MOV ADD ADC MOV MOV

d Systems Enors

programmi

ddition ins

(c)

ion add whe carry fl

CF) (D)

arily used

num1=11

300 respe

memory l

AX, [02BX , [0AX , [0BX , [0[0400] [0402]

gineering

ng - Intege

tructions

Allowed o

with carry(Alag is also

for multiw

223344H

ctively in

location 4

200] 0202] 0300] 0302] ,AX , BX

808

Lecturer instructio

(b) Allowe

operands f

ADC) woradded, th

word add

and nu

the curre

00.

86 programmi

re 5 ons and co

ed operan

for INC ins

k similarlyhat is

operation

m2=5566

nt data se

ng ‐ Integer in

omputation

nds for AD

struction

y to ADD,

n.

7788H a

egment. A

nstructions anLectBy

ns (continu

D and AD

but in this

re stored

ADD num1

nd computatioture 5 – Page y Mr.WaleedF

ue)

C.

s case the

d at me

and num2

ons 1 of 6 Fawwaz

mory

2 and


INC

No Example instructio

Solution:

AAtw

AAadd

Sinins

Example

Assume tcode for

Solution

DS 0

B

CF X


C instructi

ote that th

9:For thons?

: SI= (DI) +

AAinstructo binary n

AA instrucds ASCII d

nce AAA cstructions

10: what

that AL conumber 4

:

0100

Before

d Systems Enors

tion add 1

he INC inst

he figure

(BX) + 2H

tion specifnumbers w

ction shoudata.

can adjustthat proc

is the resuADAA

ontains 324) , and AH

01047

01046

01045

01044

01043

01042

01041

01040

gineering

to the spe

truction d

e below,

INC WINC B

H = 0062H

fically usewhich repr

uld be exe

t only datess ASCII

ult of execDD AL , AA 2H (the AH has been

34

12

DF

DD

03

FF

03

FF

808

ecified ope

on’t affec

what is

WORD PTBYTE PT

d to adjusresented i

ecuted im

ta that arnumbers

cuting theBL

SCII code n cleared.

D

86 programmi

erand

t the carry

the res

TR [004TR [004

st the resuin ASCII.

mmediatel

re in AL, should be

e following

for numb

DS 010

CF X

Doesn’t chan

ng ‐ Integer in

y flag

ult of ex

40] 42]

ult after th

y after th

the destine AL.

g instructi

ber 2), BL

After

00

nged


xecuting

he operat

he ADD in

nation reg

on sequen

L contain 3

01047

01046

01045

01044

01043

01042

01041

01040


the follo

ion of add

nstruction

gister for

nce?

34H (the

34

12

DF

DD

03

00

04

00

ons 2 of 6 Fawwaz

owing

dition

that

ADD

ASCII


DA

AA

Sinins

DA

Example

Assume tBCD code

Solution

Su

Fo

If b

If N

Su

AL

CF X

BL

AL

CF X

BL


AA instruc

AA but for

nce DAA cstructions

AA must be

11: what

that AL coe for decim

:

btraction

r subtract

borrow oc

NO borrow

btraction

29

Before

13

32

Before

34

d Systems Enors

tion used

the addit

can adjustthat proc

e invoked

is the resuADDA

ontains 29mal numb

subgroup

ion the ca

ccur after s

w occur af

subgroup

Af

Af

gineering

to perfor

ion of pac

t only datess BCD n

after the

ult of execDD AL , AA H (the BCer 13) , an

of instruc

arry flag C

subtractio

fter subtra

content i

AL

fter ADD

CF 0

BL

AL

fter ADD

CF 0

BL

808

rm an adju

cked BCD

ta that arnumbers s

addition o

cuting theBL

D code fond AH has

ction set is

CF acts as

on then CF

action the

nstruction

3C

instructio

13

66

instructio

34

86 programmi

ust opera

numbers

re in AL, hould be A

of two pa

e following

or decimalbeen clea

s similar t

borrow fla

F = 1.

n CF = 0.

n shown in

on Af

on Af

ng ‐ Integer in

tion simila

instead of

the destinAL.

cked BCD

g instructi

number 2ared.

o the add

ag

n table be

AL

CF

BL

fter DAA

AL

CF

BL

fter AAA


ar to that

f ASCII num

nation reg

numbers.

on sequen

29), BL co

ition subg

elow

42

0

13

instructio

06

0

34

instructio


performe

mbers.

gister for

nce?

ontain 13H

group.

on

on

ons 3 of 6 Fawwaz

ed by

ADD

H (the


(c) Al

SB

An

Th

Example

Solution


(a) Sub

lowed op

B is prima

other inst

e NEG ins

12: what

:

B

CF

BX

d Systems Enors

btraction in

erands fo

arily used f

truction ca

truction e

is the resuNE

Before

0

0013

gineering

nstruction

r INC instr

for multiw

alled NEG

evaluate th

ult of execEG BX

808

ns (b) Allow

ruction (d

word subt

is availabl

he 2’comp

cuting the

86 programmi

wed opera

) Allowed

ract opera

le in the s

plement o

e following

CF 1

BX FFE

After

ng ‐ Integer in

ands for S

operands

ations.

ubtraction

of an opera

g instructi

ED


SUB and SB

s for NEG

n subgrou

and

on sequen

nd computatioture 5 – Page 4y Mr.WaleedF

BB.

instructio

p

nce?

ons 4 of 6 Fawwaz

n

Mu


ltiplicatio

(


n and Div

(a)Multipl

d Systems Enors

ision instr

ication an

gineering

ructions:

nd division

808

n arithmet

86 programmi

tic instruct

ng ‐ Integer in

tions (b) A


Allowed o


perands.

ons 5 of 6 Fawwaz


MUL in

registe

MUL in

registe

Note t

Note t

IMULi

Note t

DX and

Example

Assume t2’comple

Solution


nstruction

er or mem

nstruction

er or mem

hat the m

hat the m

s similar t

hat the de

d AX

13: what

What

that AL coement of t

:

d Systems Enors

n used to

mory) and s

n used to

mory) and s

multiplicati

multiplicati

to MULbut

estination

is the resu

MU

is the res

IM

ontains FFthe numbe

A

C

A

C

gineering

multiply

store the

multiply u

store the

on of two

on of two

t is used fo

operand

ult of exec

UL CL

ult of exec

MUL CL

FH (the 2’er 2).

AL FF

Be

CL FE

AL FF

Bef

CL FE

808

unsigned

result in A

unsigned

result in D

o 8‐bit num

o 16‐bit nu

or signed

for instru

cuting the

cuting the

compleme

fore

fore

86 programmi

number

AX

number i

DX and AX

mber is 16

umber is 3

numbers

ctionsMUL

e following

e following

ent of the

A

A

C

A

A

C

ng ‐ Integer in

in AL wit

n AX with

X

6‐bit numb

32‐bit num

L and IM

g instructi

g instructi

e number

AX FD02

After MU

CL FE

AX 0002

After IMU

CL FE


h an 8 bi

h an 16 bi

ber

mber

MUL iseit

on?

on?

1), CL co

2

UL

2

UL


t operand

it operand

therAX or

ntain FEH

ons 6 of 6 Fawwaz

d ( in

d ( in

both

H (the


Ex1:Assu

1. MUL

2. IMU

3. DIV

4. IDIV

Example

1.

2.

3.

4.


8086 pume that e

L BL =

UL BL =

=

BL

V BL

:Assume t

MUL BL

IMUL BL

IDIV BL

DIV BL

d Systems Enors

programmieach instru

=AL . BL =

=AL . BL=

=7BH * 35

= AX

BL =

= AX

BL =

that each i

=AL *

L =AL *=0DH

= BL

AH (rema

15

A(rema

1

L AX

BL =

gineering

ng - Integeuction star

AL = 85

= 85H * 3

= 2’SAL *

5H = 1977

H

H =

H

H =

instructionAL = F3H

* BL = F3

* BL =2’SH * 6FH =

= F H

ainder)AL(qu

02

AH ainder) (15 2’

F H

H = 0

808

Lecturer instructiorts from thH, BL = 3

35H = 1B8

* BL= 2’S

7H→2’s co

AH (1B

AH (1B

n starts froH, BL = 9

3H * 91H

SAL *2’SB05A3H →

= F H

L uotient)

2

AL (quotient) comp(02)

01

86 programmi

re 6 ons and co

hese values35H, AH =

89H →AX

(85H) * 3

omp→E6

(remainder)

(remainder)

om these v1H, AH =

= 89A3H

BL= 2’S(F→AX.

= 2 quotie

, but P

(r

(re

ng ‐ Integer in

omputations: = 0H

X = 1B89H

5H

89H →AX

) AL (qu02

) AL (qu

02

values: = 00H

→AX = 8

F3H) *2’S

ent and 15

n

AH emainder)

15

AH emainder)

62


ns (continu

H

X.

uotient)

uotient)

89A3H

S(91H)

5H remain

egative ,

AL (quotien

FE

AL (quotient

01


ue)

nder:

so

nt)

t)

ons 1 of 8 Fawwaz


Example

1. MUL

2. IMU

3. DIV

4. IDIV

Example

1. IDIV

2. DIV

To dividebits of AH In a simisign bit operation Note thaequivalen(DX,AX)


: Assume

L BX =

UL BX =

BL AX

B

V BL AX

B

:Assume

V BL AX

B

B

V AX

B

e an 8-bit H. This ca

ilar way 1in AX is

n automati

at CBW ent to the ) without c

d Systems Enors

that each AX

F000H *

2’S(F000H

X

L =

F H

HX

L =

F

H

that each

X

L =

H

H

= 29

But 29H(po

X

L =

H

H

dividend an be done

16-bit divis extendedically.

extend 8-bvalue in

changing t

gineering

instructioX= F000H

9015H =

H) *2’S(9

H = 0B6DH

H

H =

H

instructioAX=

H =

H quotien

ositive) 2

H =20H

by and 8e automati

idend in Ad to fill

bit in ALAL. Sim

the origin

808

n starts froH, BX= 90

DX

8713

9015H) =

H more

H

H =C3H

n starts fro= 1250H,

=

nt and 60H

2’S(29H)=

8-bit divisoically by e

AX can beall bits o

L to 16-bmilarly, CW

al value.

86 programmi

om these v15H, DX=

A3 B

1000 * 6F

e than FFH

more t

om these vBL= 90H

=

H remainde

D7H

or by exteexecuting

e divided of DX. Th

bit in AXWD conv

ng ‐ Integer in

values: = 0000H

AX 000

FEB =

H Divi

than 7FH

values: H

H =

H

er

AH(Rema

60

AH(Rema

50

ending thetheInstruc

by 16-bithe instruc

X while thvert the va


DX 06FE B

de Error

Divide

H

H

H ainder) (H

H ainder) (H

e sign bitoction (CBW

t divisor.IctionCWD

he value alue in A


AX B000

e Error

AL (quotient)

D7H

AL (quotient)

20H

of Al to fiW).

n this casD perform

in AX wAX to 32-

ons 2 of 8 Fawwaz

fill all

se the m this

willBe -bitIn


3. Logica

Loope

Us

AND

use

Example

Example

OR

Us

Example

Example


al & Shift

ogical instreration on

ses any add

ed to clear

Clear the AND BLClear bit AND DH

sed to set c

Set the loOR BL, 0Set bit 7 oORAH, 8

d Systems Enors

t Instructi

ructions: Tn the speci

dressing m

r certain b

high nibbL, 0FH

5 of DH rH, DFH

certain bit

ower three07H of AX reg80H

gineering

ions

The 8086 pified sourc

mode exce

bits in the o

ble of BL r

register (xxxx

s

bits of BL

gister

808

processor ce and des

ept memor

operand(m

register (xxxxxxx

xxxxxAND

L register(xxxxxxx

(xxxxxxx

86 programmi

has instrustination o

ry-to-mem

masking)

xxAND 00

D1101 111

xxOR 000

xxOR1000

ng ‐ Integer in

uctions to operands.

mory and

000 1111

11 = xx0x

00 0111 =

0 0000 =


perform b

segment

= 0000 xx

xxxx)

xxxx x11

1xxxxxxx


bit by bit l

registers

xxx)

1)

x)

ons 3 of 8 Fawwaz

ogic


XOR

Us

Us

Example

ExampleC

Example XOR AOR AXNOT CAND AND W

4. Shift in

Thope

Sh

Th

Note thatis one bit


sed to inve

sed to clea

Invert bitXOR BL

ClearDX rXORDX,

AX , DL X,DX CX , DX WORD PWORD PT

nstructionhe four shierations: tift instruco Aligno Isolateo Perfor

he source cValueValue

t the amout or should

d Systems Enors

ert certain

ar a registe

t 2 of DL rL, 04H

register , DX

TR [BX +TR [BX +

n ft instructthe logicaltions are u

n data e bit of a brm simplecan specifie of 1 e of CL regunt of shiftd be stored

gineering

bits (togg

er by XOR

register

(

+ DI + 5HDI] , DS

tions of thel shift, theused to

byte of woe multiply fied in two

gister ft specifiedd in CL if

808

gling bits)

Red it with

(xxxxxxx

(DX will b

not vavalidnot va

], BX not va

e 8086 cane arithmeti

ord so thatand divid

o ways : Shif: Shif

d in the sof more tha

86 programmi

h itself

xxOR 000

be 0000H

alid size

alid Not valid

alid sour

n performic shift

t it can be e computa

ft by One ft by the vurce opera

an 1.

ng ‐ Integer in

00 0100 =

H)

don’t mat

instruction

ce must no

m two basic

tested ations

bit value of CLand can be


= xxxx x x

tch

n has one

ot be segm

c types of

L register e defined

nd computatioture 6 – Page 4y Mr.WaleedF

xx)

operand

ment regis

shift

explicitly

ons 4 of 8 Fawwaz

ter

if it


Thto t

Thwit

Thwit

Example

Solution:LSB is fi


he SHL anthe right w

he SHR inth zeros.

he SAR inth the valu

let AX=1

causes thelled with z

d Systems Enors

d SAL arewith zeros

nstruction

nstruction ue of MSB

234H wha

e 16-bit rezero and t

gineering

A

e identicals.

shifts the

shifts the B (this ope

at is the v

egister to bthe bit shif

808

llowed op

l:they shif

operand

operand eration use

alue of AX

SHL AX

be shiftedfted out of

86 programmi

perarnds

ft the oper

to right an

to right aned to shift

X after ex

X,1

d 1-bit posf the MSB

ng ‐ Integer in

and to left

nd fill the

nd fill thet the signe

ecution of

sition to thBis saved i


ft and fill t

e vacated

e vacated ed number

f next inst

he left whein CF

AX

AX


he vacated

bits to th

bits to thrs)

truction

ere the va

X Before

X After

ons 5 of 8 Fawwaz

d bits

e left

e left

cated


Example

The two saved in C

Exampleafter the i

Thof

ExampleSolution:

ExampleSolution:

ExampleSolution: ExampleSolution:


:

MSBsare CF.

: Assume instruction

his operatiothe LSB a

: Multiply SHL A

MOVMOVSHL AADD

: What is t

: What is t

: Assume

d Systems Enors

MOV CLSHR DX filled wit

CL= 2 annSAR AX

on is equivare zeros.

y AX by 1AX, 1 BX, AX CL,2 AX,CL AX, BX

the result DBH

the result A8H

DL contaMOV CLSAR DL

gineering

L, 2H X, CL

th zeros an

nd AX= 0X, CL is ex

valent to d

0 using sh

of SAR C

of SHL A

ins signedL , 2 L , CL

808

nd the LS

091AH. Dxecuted.

division by

hift instruc

CL, 1 ,if C

AL, CL ,if

d number;

86 programmi

B is throw

Determine

y powers

ctions

CL initially

f AL conta

divide it b

ng ‐ Integer in

wn away w

the new

of 2 as lon

y contains

ains 75H a

by 4 using


while the

contents

ng as the b

B6H?

and CL co

g shift inst

D

D

A

A


second LS

of AXAn

bitsshifted

ontains 3?

truction?

DX Before

DX After

AX Before

AX After

ons 6 of 8 Fawwaz

SB is

nd CF

d out

e

e


Rotate In


nstructions

d Systems Enors

s

gineering

808

86 programming ‐ Integer innstructions anLectBy


ons 7 of 8 Fawwaz


Example

Solution

The origihave beenRotate rigthe right In rotate the carry ExampleSolution:


: Assume

:

inal valuen rotated 1ght ROR instead of

through cflag.

: Find the

d Systems Enors

e AX = 12

e of bit 151 bit positinstructio

f left.

carry left R

addition r

MOV CLMOV BLROR DLAND BLAND DLADD DL

gineering

34H , wha

5 which istion to the on operate

RCL and r

result of th

L , 04H L , DL L , CL L , 0FH L , 0FH L , BL

808

at is the reROL AX

s 0 is rotaleft. s the sam

rotate thro

he two hex

86 programmi

esult of exX, 1

ated into C

e way as R

ough carry

xadecimal

ng ‐ Integer in

xecuting th

CF and bit

ROL exc

y right RC

l digitspac

A


he instruct

t 0 of AX

eptthat da

CR the bits

cked in DL

AX Befor

AX After


tion

X.All other

ata is rotat

srotate thr

L.

re

r

ons 8 of 8 Fawwaz

r bits

ted to

rough

University of


1. Fla

A group o

LAHF

SAHF

CLC

STC

CLI

STI

CMC

Examplethe memomemory l

Solution:

The instrflag.

Example Solution:

f Technology


8086 p

ag Contro

of instruct

Load AH

Store AH

Clear Ca

Set Carr

Clear Int

Set inter

: Write anory locatiolocation p

ructions C

: Clear the

SF

Form

d Systems Enors

programmi

ol

tions that

H from fla

H into flag

arry Flag (

ry Flag (CF

terrupt Fla

rrupts flag

n instructioon pointedpointed tob

LAHF

MOV [SI

MOV AH

SAHF

----

CLC, STC

e carry fla

ST

ZF

mat of the A

gineering

ing –Contro

directly af

ags (AH)

gs (Flags)

(CF) 0

F) 1

ag (IF)

g (IF) 1

on sequencd to by SI by DI

I], AH

H, [DI]

-------------

C, and CM

ag without

TC

AH registe

8086 progra

Lecturol Flow Ins

ffect the s

(Flags)

(AH)

0

ce to saveand then r

------------

MC are us

using CL

AF

er for the

mming ‐Contr

re 7 structions a

tate of the

Flags aff

e the currenreload the

-------------

sed to clea

LC instruct

LAHF and

rol Flow Inst

and Progra

e flags:

fected: SF

nt contentflags with

-----------

ar, set, an

tion.

PF

d SAHF in

tructions and Lectu

By

am Structur

, ZF, AF,

ts of the 8h the cont

nd comple

nstruction

Program Struure 7 – Page 1y Mr.WaleedF

res

PF, CF

086’s flagents of

ementthe

CF

ns

uctures of 10 Fawwaz

gs in

carry

University of


2. Co

MnemonCMP

Exampleexecuted

Solution

The First

The comp

(AX) - (B

The resulOF=0, Cahas odd p

3. Ju

There are

In unconchange th

f Technology


ompare inic Mean

Com

: Describe

MOVMOVCMP

:

t two instru

pare instru

BX)= 000

lts of the sarry and aparity (PF=

mp Instru

e two type

nditionaljhe executi

d Systems Enors

CM

nstructionning Fo

mpare CM

Allo

e what ha

AX, 1234 BX, 0ABAX, BX

uctions m

(A

(BX

uction per

010010001

subtractionauxiliary c=0).

uctions

es of jump

ump, as on sequen

gineering

MC

n ormat MP D,S

Co

owed oper

appens to

4H BCDH

makes

AX) = 000

X) = 1010

rforms

110100B -

n is nonzearry occur

, uncondi

the instrunce.

8086 progra

Operatio(D) – (Sresetting

ompare in

rands for c

o the statu

010010001

010111100

-10101011

ero (ZF=0)rred theref

itional and

uction is

mming ‐Contr

on ) is used i

g the flagsnstruction

compare in

us flags a

110100B

01101B

11100110

), positivefore,(CF=

d conditio

executed,

rol Flow Inst

n setting o

nstruction

as the seq

1B = 0110

e (SF=0),o=1, and AF

onal

the jump

tructions and Lectu

By

Flag aor CF, A

SF ,ZF

n

quence of

00110011

overflow dF =1). Fina

p always


affected AF , OF, PFF

finstructio

00111B

did not occally, the re

takes pla


F,

ons is

cur esult

ce to

University of


(a)Un

f Technology


ncondition

d Systems Enors

nal jump p

gineering

program se

8086 progra

equence (b

mming ‐Contr

b) Conditi

rol Flow Inst

ional jump

tructions and Lectu

By

p program


m sequence


e.

University of


1.1. Un

Mnemon

JMP

Examples

JM

JM

JM

JM

Uncondit

a) Int

i)

ii)

f Technology


ncondition

nic Me

Uncoju

s:

MP 1234H;

MP BX; IP w

MP [BX]; IP

MP DWORD

tional Jum

trasegmen

Short Jum

Near Jum

Example

It means the instruvalue in label)or a

d Systems Enors

nal Jump

eaning

onditional ump

IP will tak

will take th

P will take

D PTR [DI]

mp types:

nt: this is a

mp: Fo

mp: Fo

: Consider

jump to auction is nIP and 12

a 16-bit co

gineering

Form

JMP Op

ke the valu

he value in

the value

] ; DS:D

identi

CS.

a jump wit

rmat

rmat

r the follow

address 12ot 1234H.

234H. Thionstant (ne

8086 progra

mat

perand

(a)

(b)

ue 1234H

n BX

in memo

DI points to

fies the n

thin the cu

JMP shor

JMP near

wingexam

JMP 12

234H. How. Instead, is offset isear label),

mming ‐Contr

O

Jump is address s

o

ry locatio

o two wor

ew IP and

urrent seg

rt Label (8

r Label (16

mple of an

234H

wever, theit is the dis encoded dependin

rol Flow Inst

peration

initiated tspecified boperand

n pointed

rds in mem

d the next

gment

8 bit)

6 bit)

uncondit

e value ofifference b

d as either ng on the s

tructions and Lectu

By

to the by the

to by BX

mory, the

word iden

ional jump

f the addrbetween th

an 8-bit csize of the


Flag affec

none

first word

ntifies the

p instructi

ess encodhe incremeconstant (differenc


cted

d

e new

ion:

ded in ented (short e.

University of


iii)

iv)

Example

JMP [SI]

JMP [BP

b) Int

i)

ii)

inters

memo

new c

Example:

f Technology


Memptr1

Regptr16

Examplea memoryand Regppermit a j

uses the is, the val

To specif8086 can

uses the contains t

will re

+ SI + 100

tersegmen

Far Jump

The first ExampleJMP 200Memptr3

An indire

egment ju

ory bytes

code segm

:

d Systems Enors

16: Fo

6:: For

e: the jumpy location

ptr16 operjump to an

contents olue in BX

fy an opern be used, F

contents the value

eplace the

DS:S

00] like

nt :this is a

p: Format 16 bit are

e: 00h:40032: Forma

ect way

ump is by

starting a

ment addre

J

gineering

rmat

mat

p-to addren or the corand, respeny address

of registerX is copied

rand as a For instan

of BX asof IP (Me

e IP with

SI and DS:S

previous

‐‐‐‐‐‐‐‐‐‐‐

a jump ou

JMP fa

loaded in

0h (if this

t JMP M

to specif

using the

at the spe

ess respec

JMP DWOR

8086 progra

JMP Mem

JMP Regp

ess can alsontents of ectively. Js in the cu

JM

r BX for td into IP.

pointer tonce:

JMP

s the offsemptr16 op

the cont

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Department of Control and Systems Engineering Lecture 8 – Page 1 of 10 Third Year – Medical system - Microprocessors By Dr. Waleed Fawwaz

Lecture 8 8086 Microprocessor and its Memory and Input / Output Interface

In this lecture, we cover the 8086 microcomputer from the hardware point of view. The

8086, announced in 1978, was the first 16-bit microprocessor introduced by Intel

Corporation. The 8086 is manufactured using high-performance metal-oxide

semiconductor (HMOS) technology, and the circuitry on its chips is equivalent to

approximately 29000 transistors. It is housed in a 40-pin dual in-line package.

As seen from Pin diagram of the 8086 (Figure 1) that many of its pins have multiple

function.

Figure 1: Pin layout of the 8086



For example, we see that address bus lines A0 through A15 and data bus lines D0 through

D15 are multiplexed. For this reason, these leads are labeled AD0 through AD15. By

multiplexed we mean that the same physical pin carries an address bit at one time and

the data bit at another time.

The 8086 can be configuring to work in either of two modes:

• The minimum mode is selected by applying logic 1 to the MN/MX�� input lead.

Minimum mode 8086 systems are typically smaller and contain a single

microprocessor.

• The maximum mode is selected by applying logic 0 to the MN/MX�� input lead.

Maximum mode configures 8086 systems for use in larger systems and with

multiple processors.

Depending on the mode of operation selected, the assignments for a number of pins on

the microprocessor package are changed. As Figure 1 shows, the pin function of the

8086 specified in parentheses relate to a maximum-mode system. Figure 2 below list

the names, types and functions of the 8086 signals

Common signals

Name Function Type

AD15-AD0 Address /data bus Bidirectional , 3-state

A19/S6-A16/S3 Address / status Output/ , 3-state

MN/MX�� Minimum/Maximum mode control Input

RD�� Read control Output, 3-state

TEST�� Wait on test control Input

READY Wait state control Input

RESET System reset Input

NMI Non-maskable interrupt request Input

INTR Interrupt request Input

CLK System clock Input

VCC +5 volt Input

GND Ground Input

(a)

Minimum mode signals (MN/MX��=VCC)

Name Function Type

HOLD Hold request Input

HLDA Hold acknowledgment Output

WR�� Write control Output, 3-state

M\IO�� IO/memory control Output, 3-state

DT\R� Data transmit /receive Output, 3-state

DEN�� Data enable Output, 3-state

BHE�� \ S7 Bank high enable/Status line 7 Output, 3-state

ALE Address latch enable Output

INTA�� Interrupt acknowledgment Output

(b)



Maximum mode signals (MN/MX��=Ground)

Name Function Type

RQ/GT1,0�� Request/grant bus

access control

Bidirectional

LOCK�� Bus priority lock

control

Output, 3-state

S2�� − S0�� Bus cycle status Output, 3-state

QS1, QS0 Instruction queue

status

Output

(c)

Figure 2 (a) signals common to both minimum and maximum mode. (b) Unique

minimum-mode signals. (c) Unique maximum-mode signals.

Minimum mode interface signals The minimum-mode signals can be divided into the following basic groups:

1. Address/Data Bus

The address bus is 20 bits long and consists of signal lines A0 (the LSB) to A19 (the

MSB).

The data bus is 16 bits long and consists of signals lines D0 (the LSB) to D15 (the

MSB). When acting as a data bus, they carry read/write data for memory,

input/output data for I/O devices, and interrupt-type codes from an interrupt

controller.

2. Status signals

The four most significant address lines, A19 through A16 are also multiplexed,

but with status signals S6 through S3. These status bits are output on the bus at

the same time that data are transferred over the other bus lines. Bits S4 and S3

together form a 2-bit binary code that identifies which of the internal segment

registers was used to generate the physical address that was output on the address

bus during the current bus cycle (See Figure 3)

S4 S3 Address Status

0 0 alternate(relative to the ES segment)

0 1 Stack (relative to the SS segment)

1 0 Code/None (relative to the CS segment or a default of zero)

1 1 Data (relative to the DS segment)

Figure 3 address bus status codes

Status line S5 reflects the status of logic level of the internal interrupt enable flag.

3. The control signals

These are provided to support the memory and I/O interfaces of the 8086.

• ALE signal: is a pulse to logic 1 that signals external circuitry when a

valid address is on the bus. This address can be latched in external

circuitry on the 1-to-0 edge pulse at ALE.



• M/�� signal: tells external circuitry whether a memory or I/O transfer is

taking place over the bus. (Logic 1 for memory operation, logic 0 for I/O

operation).

• DT/�� signal: when this line is logic 1 the bus is in Transmit Mode (data

are either written into memory or output to an I/O device). When this line

is logic 0 the bus is in Receive Mode (data are either read from memory

or input to an I/O device).

• !"�� signal: logic 0 on this line is used as a memory enable signal for the

most significant byte half of the data bus, D8 through D15.

• �#�� signal: indicate that a read bus cycle is in progress.

• $�� signal: indicate that a write bus cycle is in progress.

• #"%�� signal: during read operations, this signal is also supplied to enables

external devices to supply data to the microprocessor.

• READY signal: used to insert wait states into the bus cycle so that it is

extended by a number of clock periods.

4. Interrupt signals: (INTR, INTA��, TEST��, RESET, NMI)

5. Direct memory access (DMA) interface signals: (HOLD, HLDA�� )

Maximum mode interface signals

When the 8086 microprocessor is set for the maximum-mode configuration, it produces

signals for implementing a multiprocessor/coprocessor system environment. By

multiprocessor system environment we mean that multiple microprocessors exist in the

system and that each processor executes its own program.

8288 bus controller: Bus Commands and Control Signals

During the maximum mode (as shown in figure 6) operation, the WR��, M/IO��,

DT/R�, DEN��, ALE, and INTA�� signals are no longer produced by the 8086. Instead, it

outputs a status code on three signals lines, S�0,S�1,and S�2 , prior to the initiation of each

bus cycle.

• &'��, &(��, &)��: These three bit are input to the external bus controller device,

the 8288, which decodes them to identify the type of next bus cycle, as

shown in figure 5. In addition to the signal produced (figure 5) the 8288

bus controller produce DEN, DT/R�, and ALE

• *�+,�� signal: this signal is meant to be output (logic 0) whenever the

processor wants to lock out the other processors from using the bus.

• Queue Status Signals (QS1, QS0): these two bits tell the external

circuitry what type of information was removed from the queue.

• �-/./(�� , �-/./)�� : these two signals provide a prioritized bus access

mechanism for accessing the local bus.



Figure 4 Minimum-Mode block diagrams

Status inputs CPU Cycle 8288 Command Meaning

&'�� &(�� &)��

0 0 0 Interrupt

Acknowledge INTA�� Interrupt acknowledge

0 0 1 Read I/O port IORC�� I/O read control

0 1 0 Write I/O port IOWC��, AIOWC�� I/O write control,

Advanced I/O write control

0 1 1 Halt None ---

1 0 0 Instruction Fetch MRDC�� Memory read control

1 0 1 Read Memory MRDC�� Memory read control

1 1 0 Write Memory MWTC��, AMWC�� Memory write control, advanced

memory write control

1 1 1 Passive None ---

Figure 5 Bus Status Codes



Figure 6 Maximum-Mode block diagram with the 8288 Bus Controller

System Clock

The time base for synchronization of the internal and external operations of the

microprocessor in a microcomputer system is provided by the clock (CLK) input

signal. The 8086 microprocessor is manufactured in three speeds: the 5-MHz 8086, the

8-MHz 8086-2 and the 10-MHz 8086-1. The 8284 clock generator and driver IC

generates CLK (Figure 7)



Figure 7 Connecting the 8284 to the 8086.

Bus cycle and time state

A bus cycle defines the basic operation that a microprocessor performs to communicate

with external devices. Example of bus cycles are

• Memory read

• Memory write

• IO read

• IO write

The bus cycle of 8086 microprocessors consists of at least four clock periods (T1, T2,

T3, and T4):

• During T1 the 8086 puts an address on the bus.

• During T2 the 8086 puts the data on the bus (for write memory cycle) and

maintained through T3 and T4.

• During T2 the 8086 puts the bus in high-Z state (for read cycle) and then the

data to read must be available on the bus during T3 and T4.

These four clock states give a bus cycle duration of 125 ns × 4= 500 ns in an 8-MHz

system.

Idle States

If no bus cycles are required, the microprocessor performs what are known as idle state.

During these states, no bus activity takes place. Each idle state is one clock period long,

and any number of them can be inserted between bus cycles. Idle states are performed

if the instruction queue inside the microprocessor is full and it does not need to read or

write operands form memory.

8284 8086

8 19 X1

X2

F/ C 13

17

18

XTAL



Wait States

Wait states can be inserted into a bus cycle. This is done in response to request by an

event in external hardware instead of an internal event such as a full queue. The

READY input of the 8086 is provided specifically for this purpose. As long as READY

is held at the 0 level, wait states are inserted between states T3 and T4 of the current

bus cycle, and the data that were on the bus during T3 are maintained. The bus cycle is

not completed until the external hardware returns READY back to the 1 logic level.

Read Cycle

The read bus cycle begins with state T1. During this period, the 8086 output the 20-bit

address of the memory location to be accessed on its multiplexed address/data bus AD0

through AD15 and multiplexed lines A16/S3 through A19/S6.note that at the same time a

pulse is also produced at ALE. The signal BHE�� is also supplied with the address lines.

(Figure 8)

Figure 8 Minimum-mode memory read bus cycle of the 8086.



Write Cycle

The write bus cycle is similar to the read bus cycle except that signal WR�� is set 0 instead

of the signal RD�� and signal DT/R� is set to 1.

Hardware organization of the 8086 memory address space

The 8086’s 1Mbyte memory address space I s implemented as two independent

512Kbyte banks: the low (even) bank and the high (odd) bank. Figure 9 shows four

different cases that happen during accessing data:

1. When a byte of data at an even address (such as X) is to be accessed:

• A0 is set to logic 0 to enable the low bank of memory.

• BHE�� is set to logic 1 to disable the high bank. (Figure 9-a).

2. When a byte of data at an odd address (such as X+1) is to be accessed:

• A0 is set to logic 1 to disable the low bank of memory.

• BHE�� is set to logic 0 to enable the high bank. (Figure 9-b).

3. When a word of data at an even address ( aligned word ) is to be accessed:


• BHE�� is set to logic 0 to enable the high bank. (Figure 9-c).

4. When a word of data at an odd address ( misaligned word ) is to be accessed

the 8086 need two bus cycles to access it (Figure 9-d):

a. During the first bus cycle, the odd byte of the word (in the high bank) is

addressed

• A0 is set to logic 1 to disable the low bank of memory.

• BHE�� is set to logic 0 to enable the high bank.

b. During the second bus cycle, the odd byte of the word (in the low bank)

is addressed


• BHE�� is set to logic 1 to disable the high bank.



Figure 9 (a) Even-address byte transfer by the 8086. (b) Odd-address byte transfer by the

8086. (c) Even-address word transfer by the 8086. (d) Odd-word transfer by the 8086

University of Technology Memory types and memory expansion Department of Control and Systems Engineering Lecture 9 – Page 1 of 6 Third Year –Medical System Eng. Microprocessors By Dr. Waleed Fawwaz

Lecture 9 - Memory types and memory expansion

Memory provides the ability to store and retrieve digital information and it is one of

the key elements of a microcomputer system. Previously; we indicated that the memory

unit of the microcomputer is partitioned into a primary storage section and secondary

storage section. The main differences between them are summarized in the table below:

Primary storage memory Secondary storage memory

Used for working information, such

as the instruction of the program

currently being run and data that it

is processing .

Used for storage of data,

information, and programs that are

not in use.

This part normally requires high

speed operation but does not

normally require very large storage

capacity.

This part of the memory unit can be

slow speed, but it requires very

large storage capacity.

It is implemented with

semiconductor memory devices,

such as ROM , RAM and FLASH.

It is normally implemented with

magnetic storage device, such as

the floppy disk and hard disk drive.

Read Only Memory is one type of semiconductor memory device. It is most widely

used in microcomputer systems for storage of the program that determines overall

system operation. The information stored within a ROM integrated circuit is

permanent (nonvolatile). Three types of ROM devices are in wide use today:

1. The mask programmable read only memory (ROM).

2. The one time programmable read only memory (PROM).

3. The erasable programmable read only memory (EPROM).

A large number of standard EPROM ICs are available today. The Table below lists the

part number, bit densities, and byte capacities of nine popular devises.

EPROM Density (bits) Capacity (bytes)

2716 16K 2K× 8

2732 32K 4 K×8

27C64 64K 8 K×8

27C128 128K 16 K×8

27C256 256K 32 K×8

27C512 512K 64 K×8

27C010 1M 128 K×8

27C020 2M 256 K×8

27C040 4M 512 K×8

الجدول

لالطالع فقط


Random Access Memory

RAM is similar to ROM in that its storage location can be accessed in a random order,

but it is different from ROM in two important ways:

1. Data stored in RAM is not permanent.

2. RAM is volatile

Two types of RAMs are in wide use today:

Static RAM (SRAM): data remain valid as long as the power supply is not turned

off.

Dynamic RAM (DRAM): to retain data in a DRAM, it is not sufficient just to

maintain the power supply; we must periodically restore the data in each storage

location (Refreshing the DRAM).

Table below list a number of standard static RAM ICs.

SRAM Density (bits) Organization

4361 64K 64K× 1

4363 64K 16 K×4

4364 64K 8 K×8

43254 256K 64 K×4

43256A 256K 32 K×8

431000A 1M 128 K×8

Memory expansion

In many applications, the microcomputer system requirement for memory is greater

than what is available in a single device. There are two basic reasons for expanding

memory capacity:

1. The byte-wide length is not large enough

2. The total storage capacity is not enough bytes.

Both of these expansion needs can be satisfied by interconnecting a number of ICs.

الجدول

لالطالع فقط


Example 1: show how to implement 32K× 16 EPROM using two 32K×8 EPROM?

Solution:


Example 2: show how to implement 64K× 8 EPROM using two 32K×8 EPROM?

Solution:

The CS̅̅ ̅1 and CS̅̅ ̅0 signals could be implemented as follow:

Notes:

CS̅̅ ̅ means Chip Select , and it is active low signal (active when it is 0 logic) ,

and is generated from the address bus as above (sometimes through decoder).

OE̅̅ ̅̅ means Output Enable and it should be connected to RD̅̅ ̅̅ signal from the

Microprocessor.

WE̅̅̅̅̅ means Write Enable and it should be connected to WR̅̅ ̅̅ ̅ signal from the

Microprocessor.

A15 CS̅̅ ̅0

CS̅̅ ̅1


Example 3: Design a 8086 memory system consisting of 1Mbytes, Using 64K× 8

memory

A0

A17 A18

A19

M/𝑰𝑶̅̅̅̅ 𝑩𝑯𝑬̅̅ ̅̅ ̅̅ ̅

D8-D15 D0-D7

A1-A16

High bank

Low bank

64K X 8

64K X 8

Decoder 3to8

74LS138

D0-D7

A0-A15

A0-A15

D0-D7

Decoder 3to8

74LS138


Figure below shows layout of widely used 3 to 8 active low decoder (74LS 138):

The inputs are A, B , C (A is the LSB and C is the MSB).

e.g. when C B A = 110 , then Y0 to Y7 generate logic 1, except Y6=0.

To work properly, the G1 input must be tied to +5V permanently, while G2A

and G2B inputs must be tied to ground.

3 to 8 decoder 74LS138

Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7

A B C 𝐺1 𝐺2𝐴̅̅ ̅̅ ̅̅ 𝐺2𝐵̅̅ ̅̅ ̅̅

+5V

Questions for lectures 1 to 7 Microprocessor

هندسة سيطرة ونظم 2017- 2016ثالث طبية د. وليد فواز

1 of 6

(Note:Question marked with ⋆ relates to lectures 8 to 10)

Q1) Which of the next instructions is valid? If not, State why? 1. MOV [0330] , AX

2. ADD CL, SI

3. XOR DH , [SP]

4. MUL AX , BX

5. MUL AX , DS

6. SBB CL , CH

7. INC IP

8. MOV [BL] , AX

9. ROR AL , 03 h

10. ADD CL , CL 11. SUB [AX] , [2000 h] 12. MUL BX 13. MOV [DH] , AX 14. ROR BX , 06 h 15. SUB CL , CL 16. ADD [AX] , [2000 h] 17. MUL BX 18. SAHF

Q2) What is the value of CX after the execution of the next program?

MOV CX , 0A03H

MOV BX , 020EH

SUB BX , CX

ROL CX , CL

NEG CL (solution: CL=E8 H)

Q3) What is the value of AX after the execution of the next program? MOV CX , 0401H

MOV AX , 8A01H

MUL CH

ADD AX , CX

SHR AL , CL (solution AX=0402 H)

Q4) Write program to implement the following operation: DL = BH * 4.5 assume (0 < BH < 10H)



2 of 6

Q5) Write program to implement the following operation: DL = BH * 0.75

assume (0 < BH < 10H) .

Q6) Draw the software model of the 8086.

Q7) Draw the Execution and bus interface units of the 8086.

Q8) Draw the 8086 software model (showing the internal register, memory

address space with its segments, and IO address space with its direct and

indirect pages).

Q9) Write program to generate an array of 100 byte as

shown in Figure (1).

Q10) Given array A(I) in Figure (1), write program to

generate array B(I) of 100 byte stored at 5000:0050h,

so that B(I) = 2* A(I).

Q11) Draw the lower byte of the 8086 status register and

define names and functions of three flags only.

Q12) Write a program that scans the 5010 bytes start at

location D016 in the current data segment for the value

45H , if this value is found then store FFH in the

memory location 5000H in the same segment else store

00H in the same location.

Q13) Write a program segment for each of the next

statements: 1. Clear the least significant bit of DS register.

2. Multiply unsigned number in BL by the unsigned number in AX. (result is less than 16

bits)

3. Rotate the content of BX register 5010 times to the right.

Q14) List names and sizes of all registers in 8086 microprocessor.

Q15) Explain briefly the difference between the following 1. SAHF and LAHF instructions.

2. INC AX and ADD AX,01 instructions.

Q16) Complete the following:

1. Each 8086 microprocessor instruction can be divided into two parts: ________

and operand.

2. The internal architecture of the 8086 contains two processing units: _________

and the execution unit.

3. _________ storage memory used for storage of data, information, and programs

that are not in use.

4. BP register is used to point to memory locations in the __________ segment.

5. The physical address ________is equivalent to the logical address 1234:567816.

6. _____________ used to store AH into flag register.

4000:0250

.

.

.

.

.

04

03

02

01

00

4000:024F

4000:024E

4000:024D

4000:024C . . . .

Figure (1)



3 of 6

Q17) Study the next program and answer the questions: MOV BP, 0200H

MOV AX, 1000H

MOV SS, AX

MOV SP, 0203H

PUSH AX

MOV AX, [BP + 1]

What is the address of top of stack before and after the PUSH instruction?

What is the address of bottom of stack before and after the PUSH instruction?

What is the duration needed to push the AX content in the stack in 10MHz 8086

system with three wait state?

What is the content of AX register after the end of the program?

What is the content of SP register after the end of the program?

Q18) Write a program segment for the following statements: 1. Move byte from memory location 2FFFFH to memory location 30000H.

2. Add 8-bit unsigned number in BH register to 16-bit unsigned number in DX register.

3. Invert bit 3 of SS register.

Q19) Compare between Primary and Secondary memory.

Q20) Write a program that loads a block of 10016 memory locations with the byte 7516.

The block is stored in the memory incrementally and starts at logical address

A000:300016.

Q21) Define the addressing mode, and then list the 8086 addressing modes and give

an example for each mode

Q22) Explain briefly the difference between the following. 1. NOT and NEG instructions.

2. Intersegment and Intrasegment jump instructions.

3. CMP and SUB instructions.

Q23) Name the dedicated operations assigned to the DX register.

Q24) Given SS=2000H and SP=0030H in an 8086-based microcomputer that

running at 10MHz with two wait states, answer the following: 1. What is the address of top of stack?

2. What is the address of bottom of stack?

3. How long does it take to perform the interrupt-acknowledge bus cycle sequence?

4. How long does it take the 8086 to push the values of the old flags, old CS, and old

IP to the stack?

5. How much stack space does this information take?

Q25) Write a program to move a block of 5010 consecutive word of data stored

incrementally at address 1234:020016 to memory location 080016 in the same

segment.



4 of 6

Q26) Write a program to apply the function Y= 4X + 73H to an array of 30010

unsigned bytes stored incrementally at address 1234:020016 in memory. Store

the result array in memory at address 080016 in the same segment.

Q27) Write a program segment for:

1. Multiply unsigned number in CX register by 0.12510.

2. Invert the carry flag.

3. Add DS register to BX register. Store result in BX register.

4. Increment 32-bit number stored in memory at address 4000H by one.

5. Rotate BL register to right 100H times.

Q28) Answer

1. How large is the instruction queue in the 8086?

2. Name two dedicated operations assigned to the AH register.

Q29) For the figure shown below, answer :

1. What is the value of CS and IP registers

after execution of instruction:

JMP DWORD [BX + 4] ?

2. What is the value of DX register after

execution of instruction: POP DX?

3. Is the word that stored in memory location

30021H aligned or misaligned?

4. What is the change in memory after

execution of instruction:

XOR [DI], CH ?

5. What is the value of DI register after


MOV DI, [BP + SI] ?

Q30) Write a program to create an array contains 3216 bytes in memory at address

ACDD:780D16. The array elements are [0 2 4 6 8 ... 9810]. Let the array be

stored incrementally.

Q31) Write a program segment for :

1. Decrement 32-bit number stored in memory at address 4000H by one.

2. Clear interrupt flag.

3. Increment DS register by one.

Memory Internal Register

30020 26 CS 5DE0

30021 00 DS 2FFF

30022 F7 SS 3002

30023 C0 ES 4000

30024 59 AX 0000

30025 A9 BX 0030

30026 36 CX 0003

30027 96 DX 0004

30028 56 SI 0003

30029 DE DI 0027

3002F 75 SP 0002

BP 0005



5 of 6

Q32) Answer

1. What is the maximum amount of memory that can be active at a given time in

the 8086?

2. Define the function of the Zero Flag.

3. Name two dedicated operations assigned to the CX register.

Q33) Answer the following: 1. W.P. to rotate AX content to right through carry 1710 times.

2. W.P. to copy one byte from memory location 7000016 to memory location 20E0016.

3. What is the value of SI after executing the program segment below?

Q34) For the figure shown below, answer

1. What is the value of AL register after

execution of instruction: MUL DL?

2. What are the values of CS and IP registers

after execution of instruction:

JMP 2000H?

3. What is the value of BH register after


ADD BH, [BP]?

4. Is the double word that stored in memory

location 00006H aligned or misaligned?

5. What is the change in memory after

execution of instruction: NOP ?

For more help, or to download this sheet go to :

http://goo.gl/SRBM6m

Memory Internal Register

30020 26 CS 5DE0

30021 00 DS 3000

30022 F7 SS 3002

30023 C0 ES 4000

30024 59 AX E001

30025 C3 BX 0230

30026 96 CX 0003

30027 06 DX 2F02

30028 56 SI 0003

30029 DE DI 0022

3002A 75 SP 0002

BP 0007

MOV SI, 0001H DEC SI DEC SI



6 of 6

التالية لالطالع فقط:االيعازات 7الى 1المحاضرات من في

Instruction Lectrue Description XLAT LEA LDS LES

4 Data transfer instructions

AAA, DAA, DAS, AAS DIV, IDIV IMUL AAM, AAD, CBW, CWD

5 BCD arithmetic Division Signed arithmetic

SAR SAL RCR RCL

6 Arithmetic shift Rotate through carry

------- 7 Jump instructions that depend on Sign Flag or Overflow Flag

------- ------- All loop and string instructions

For more help, or to download this sheet go to :

http://goo.gl/SRBM6m

Questions for lectures 8 and 9 Microprocessor

ونظم هندسة سيطرة 2017- 2016ثالث طبية د. وليد فواز

1

Questions for lecture 8:

1) What does status code S4S3 =01 mean in terms of the memory segment being

accessed?

Solution: Stack (relative to the SS segment)

2) Which output is used to signal external circuitry that a byte of data is available on

the upper half of the 8086’s data bus?

Solution: 𝑩𝑯𝑬̅̅ ̅̅ ̅̅ ̅

3) Which output is used to signal external circuitry in an 8086-based microcomputer

that valid data is on the bus during a write cycle?

Solution: 𝑾𝑹̅̅ ̅̅ ̅

4) At what speeds are 8086s generally available?

Solution: 5MHz, 8MHz, and 10MHz.

5) How many clock states are in an 8086 bus cycle that has no wait states?

Solution: Four cycles

6) What is the duration of the bus cycle for a 5-MHz 8086 that is running at full

speed and with no wait states?

Solution: 1/5MHz *4 cycles= 800ns

7) What is an idle state?

8) What is a wait state?

9) If an 8086 running at 10 MHz performs bus cycles with two wait states, what is

the duration of the bus cycle?

Solution: 1/10MHz *(4+2) cycles =600ns

10) In which bank of memory in an 8086-based microcomputer are odd-addressed

bytes of data stored? What bank select signal is used to enable this bank of

memory?

Solution: odd-addressed bytes resides in the high bank. Signal 𝑩𝑯𝑬̅̅ ̅̅ ̅̅ ̅ is used

to enable the high bank memory.

11) List the memory control signals together with their active logic levels that occur

when a word of data is written to memory address A000016 in a minimum-mode

8086 microcomputer system.

Solution:

Word from even-addressed memory (aligned word) => one cycle

𝑊𝑅̅̅ ̅̅ ̅ = 0

𝑅𝐷̅̅ ̅̅ = 1

𝐵𝐻𝐸̅̅ ̅̅ ̅̅ = 0

A0 = 0

DT/�̅� = 1



2

M/𝐼𝑂̅̅ ̅ = 1

12) Draw the minimum-mode memory write bus cycle of the 8086.

13) Draw the minimum-mode IO write bus cycle of the 8086.

14) Draw memory interface block diagram for minimum-mode 8086.

15) How many address lines must be decoded to generate five chip select signals?

Solution: three ( 23 =8, 8 > 5 توضيح )

اسئلة االمتحان اليومي الثالث

16) Define the minimum mode in 8086 microprocessor.

17) Calculate the time needed to move the data of the next instruction in 8MHz 8086

microprocessor: MOV [2001], AX

Solution:

∵ data is misaligned word

∴ two cycles are needed

T=1/8MHz * 2 * 4 =1000 ns =1 μ s

18) How many pins is the 8086’s address bus? How many pins are multiplexed with

the data bus?

Solution: There are 20 pins in the 8086’s address bus (A0-A19), 16 of them

are multiplexed with the data bus (AD0-AD15).

19) When accessing one byte at a memory location, what is the value (state) of M/IO̅

signal? What is the value of this signal when accessing one word at a memory

location?

Solutions: M/𝑰𝑶̅̅̅̅ equals 1 always when accessing memory location,

regardless of the data size (byte or word).

20) Classify the next pins as INPUT or OUPUT:DT/�̅� , 𝑹𝑫̅̅ ̅̅ ̅, 𝑾𝑹̅̅ ̅̅ ̅, and 𝑩𝑯𝑬̅̅ ̅̅ ̅̅ ̅.

Solution: All these pins are output signals

او يكون الجواب بشكل جدول كاالتي

Input signal Output signal

--- DT/�̅�

--- 𝑹𝑫̅̅ ̅̅ ̅

--- 𝑾𝑹̅̅ ̅̅ ̅

--- 𝑩𝑯𝑬̅̅ ̅̅ ̅̅ ̅

Questions for lecture 9:



3

21) Design 8086’s memory system consisting of 64K bytes of ROM memory, make

use of the devices in figure below. The memory is to reside over the address range

60000H through 6FFFFH .

Solution:

From 60000H to 6FFFFH = 64Kbyte =216

∴ Number of Chips = 64K/32K =216/215= 21 =2 chips of EPROM

Each chip is 32Kbyte

A19 to A16 fixed (01102 =616)

15 address line needed (A15 to A1) for each chip

A0 used to select low bank

End of solution

Address 𝐶𝐸̅̅ ̅̅ 𝑂𝐸̅̅ ̅̅ Data

EPROM (27C256)

A15-A1

A15-A1

6

A19

A18

A17

A16

A0

𝐵𝐻𝐸̅̅ ̅̅ ̅̅

D7-D0

D15-D8

𝑅𝐷̅̅ ̅̅

𝑅𝐷̅̅ ̅̅



4

22) Design 8086’s memory system consisting of 256K bytes of RAM memory using

the devices in figure below. RAM memory is to reside over the address range

C0000H through FFFFFH.

Solution:

From C0000H to FFFFFH = 256Kbyte =218

∴ Number of Chips = 256K/32K =218/215= 23 =8 chips of SRAM

Each chip is 32Kbyte

A19 to A18 fixed to (11)2 .

A17-A16 used to generate for CE , in each bank

address line needed (A15 to A1) for each chip

A0 used to select low bank

Address 𝐶𝐸̅̅ ̅̅ 𝑊𝐸̅̅ ̅̅ ̅ Data 𝑂𝐸̅̅ ̅̅

SRAM (43256A)

32K×8



5

End of solution

A15-A1

A15-A1

A19

A18

A0

𝐵𝐻𝐸̅̅ ̅̅ ̅̅

D7-D0

D15-D8

𝑅𝐷̅̅ ̅̅

𝑅𝐷̅̅ ̅̅

𝑊𝑅̅̅ ̅̅ ̅

𝑊𝑅̅̅ ̅̅ ̅

2 to 4 decoder

Y0

Y1

Y2

Y3

A

B

𝐺1

𝐺2𝐴̅̅ ̅̅ ̅̅

𝐺2𝐵̅̅ ̅̅ ̅̅

2 to 4 decoder

Y0

Y1

Y2

Y3

A

B

𝐺1

𝐺2𝐴̅̅ ̅̅ ̅̅

𝐺2𝐵̅̅ ̅̅ ̅̅

M/𝐼𝑂̅̅ ̅

M/𝐼𝑂̅̅ ̅

A16

A17

A16

A17

University of Technology Control and Systems Engineering Department

Final Exam

Page 1 of 6

Year: 2016-2017

Examiner: Dr. Waleed Fawwaz Time:3 Hours Date: 23/01/2017

Subject: Microprocessor (Medical System Engineering)

Note: Attempt 10 of 12 questions only (7 marks each)

Q1) Answer the following: (1 mark each)

1. Write the physical address for the logical address 2000:200016.

2. Write a possible logical address for the physical address FFFFF16.

3. List two registers that can be used as memory pointer with SS register.

4. List two registers that can be used as memory pointer with DS register.

5. List the names of three 8086’s segment registers.

6. What is the maximum amount of memory that can be active at a given time in 8086 system?

7. What is the address of the End of Stack if the SS register is 100016?

Q2) Draw the lower byte of the flag register and define names and functions of three flags only.

Q3) Which of the next instructions are valid (or invalid)? Explain why? (1 mark each)

1. ADD CL , SI

2. XOR DH , [SP]

3. INC IP

4. MOV [BL], AX

5. ROR AL , 03

6. ADD CS , AX

7. PUSH AX, [2000]

Q4) Write a program segment for each of the following:

1. Multiply AX by 0.12510. (2 mark)

2. Clear bit 0 of the word stored at address 300016.

(2 mark)

3. Store CX to the top of stack. (2 mark)

4. Rotate DX to left 5 times. (1 mark)

Q5) Write a program segment for each of the following:

1. Increment SS register by one. (2 mark)

2. Multiply CL by 2716. Store result in AX. (2 mark)

3. Decrement 32-bit number stored in memory at address 500016 by one. (2 mark)

4. Clear interrupt flag. (1 mark)

Q6) For Figure 1, answer the following: (1 mark each)

1. What is the value of carry flag after the execution of the instruction: ADD SI, 0001

2. What is the value of AX register after the execution of the instruction: NEG AX

3. What is the value of BX register after the execution of the instruction: MOV [BX], F000

4. What is the value of CX register after the execution of the instruction: AND CL, FE

5. What is the value of DX register after the execution of the instruction: XCHG DX, [000C]

6. What is the value of IP register after the execution of the instruction: JMP 1000:000A

7. What is the value of DI register after the execution of the instruction: XOR DI, [0008]

Memory Internal registers

90008 00 IP 22F0

90009 E0 CS 5DE0

9000A F7 DS 9000

9000B C0 SS C000

9000C 12 ES 4000

9000D 34 AX AAAA

9000E B6 BX 0002

9000F 96 CX 0F09

90010 1B DX 57C0

90011 0F SI FFFE

90012 7E DI 8000

SP C008

BP E005

Figure 1 - Question 6

Page 2 of 6

Q7) Write a program to compare one byte at address 3000:200016 with one byte at address

3000:200116. If the first byte is larger store 1 in address 3000:200216, else store 0. (Assume

unsigned numbers)

Q8) Write a program to apply the function Y= 2X + 1516 to an array of 30016 unsigned bytes

stored incrementally at address 1234:020016 in memory. Store the result array in memory at

address 080016 in the same segment.

Q9) Draw the 8086 minimum-mode memory write bus cycle.

Q10) Answer the following: (1 mark each)

1. For an 8086 system running at 10 MHz, calculate the time of one bus cycle.

2. For an 8086 system running at 10 MHz, calculate the time needed to read a word from address

location 1000:000016.

3. What are the values of 𝐵𝐻𝐸̅̅ ̅̅ ̅̅ and A0 signals during writing a word to address 1000:000D16?

4. What does status code S4S3 =01 mean in terms of the memory segment being accessed?

5. What signals are multiplexed with pins A16, A17, A18, and A19.

6. Classify the next pins as INPUT or OUPUT: MN/𝑴𝑿̅̅ ̅̅ ̅ and ALE.

7. How many pins are there in 8086 microprocessor?

Q11) Complete the following: (1 mark each)

1. If no bus cycles are required, the microprocessor performs what are known as _______.

2. Because the 8086 instructions can access 8-bit and/or 16-bit data, the memory space is always

organized as banks.

3. The 8086 microprocessor is classified as 16-bit microprocessor because _______.

4. The most significant byte of a misaligned word is stored in the _______ bank of the memory

space.

5. The 8086 programs are stored in the _______ segment of the memory space.

6. The 8086’s address bus is ________ while the data bus is bidirectional.

7. The size of the 8086’s IO address space is _________ bytes.

Q12) Design 8086’s memory system consisting of 512K bytes of RAM memory using the devices

in Figure 2. RAM memory is to reside over the address range 8000016 through FFFFF16.

RAM

128Kbyte

Decoder

2 to 4

Ad

dre

ss

Dat

a

𝐶𝐸 ̅̅ ̅̅̅

𝑊𝐸̅̅ ̅̅ ̅ 𝑅𝐸̅̅ ̅̅

G1

𝐺2𝐴̅̅ ̅̅ ̅̅ 𝐺2𝐵 ̅̅ ̅̅ ̅̅

A B

Figure 2 - Question 12

17 8

Page 3 of 6

الحلول:

Q1:

1. 22000

2. F000:FFFF او FFFF:000F او اي احتمال اخر

3. SP and BP

4. SI, DI , and BX اي اثنين من

5. CS, SS, DS, ES اي ثالثة من

6. 256Kbytes

7. 1000:0000

Q2:

7 6 5 4 3 2 1 0

SF ZF AF PF CF

من التالية:تعاريف ثالث اي مطلوب

1. The carry flag (CF): CF is set if there is a carry-out or a borrow-in for the most significant bit of the result during the execution of an instruction. Otherwise FF is reset.

2. The parity flag(PF): PF is set if the result produced by the instruction has even parity- that is, if it contains an even number of bits at the 1 logic level. If parity is odd, PF is reset.

3. The auxiliary flag (AF): AF is set if there is a carry-out from the low nibble into the high nibble or a borrow-in from the high nibble into the low nibble of the lower byte in a 16-bit word. Otherwise, AF is reset.

4. The zero flag (ZF): ZF is set if the result produced by an instruction is zero. Otherwise, ZF is reset.

5. The sign flag (SF): The MSB of the result is copied into SF. Thus, SF is set if the result is a negative number of reset if it is positive.

Q3:

No Valid or invalid Why?

1. Invalid Different sizes of registers (8-bit and 16-bit)

2. Invalid SP can’t be used as direct memory pointer to DS

Or

SP can be used only with PUSH and POP instruction

3. Invalid User can’t access IP register directly

Or

IP value increase automatically, and only jump instructions

can change IP value.

4. Invalid BL can’t be used as memory pointer.

Or

BX should be used instead of BL

5. Invalid For rotation more than once, the value should be in CL

register

6. Invalid CS register can’t be used with arithmetic instruction

7. Invalid Push instruction has only one operand

Page 4 of 6

Q4:

1.

MOV CL, 03

SHR AX,CL

او

SHR AX, 1

SHR AX, 1

SHR AX,1

2.

AND FFFE, [3000]

او

MOV AX , [3000]

AND AX, FFFE

MOV [3000], AX

3. PUSH CX

4.

MOV CX, 05

ROL DX, CL

Q5:

1.

MOV AX, SS

INC AX

MOV SS, AX

2.

MOV AL, 27

MUL CL

3.

SUB [5000], 0001

SBB [5002], 0000

4.

CLI

Q6:

1. CF=0

2. AX=5556

3. BX=0002 No change

4. CX=0F08

5. DX=3412

6. IP =000A

7. DI=6000

Page 5 of 6

Q7:

MOV AX, 3000

MOV DS, AX

MOV AL, [2000]

MOV [2002], 00

COMP AL, [2001]

JC *

MOV [2002], 01

* HLT

Q8:

MOV AX, 1234

MOV DS, AX

MOV CX, 0300

MOV SI , 0200

MOV DI , 0800

* MOV AL, [SI]

SHL AL, 1

ADD AL, 15

MOV [DI], AL

INC SI

INC DI

DEC CX

JNZ *

HLT

Q9:

Page 6 of 6

Q10

1. 1/10MHz * 4= 0.4 milli second =400ns

2. 1/10MHz * 4= 0.4 milli second =400ns ( توضيح aligned word one cycle only)

3. Misaligned word need two cycles

Cycle 1: 𝐵𝐻𝐸̅̅ ̅̅ ̅̅ =0 and A0 = 1

Cycle 2: 𝐵𝐻𝐸̅̅ ̅̅ ̅̅ =1 and A0 = 0

4. S4S3=01 => stack segment

5. Status pins أو S6-S3

6.

MN/MX = input

ALE = output

7. 40 pins

Q11:

1. Idle state

2. Two

3. Because it has 16 bit data bus

4. Low bank

5. Code segment

6. Unidirectional ( or three-state output)

7. 64kbytes

Q12 : see lecture 9

Documents

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