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The World o !ntegr"ted Circuits #LS!$%LS!&
Full-Custom ASICs
Semi-Custom ASICs
User Programmable
FPGAPLD
PLA/PAL CPLDs
Simplegates (nand/
nor/xor/xnor..)Complex
gates/cellsMuxes
PLA/PAL(layout aspect not
programma!le)
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Logic Design Using Multiplexers
A Tr"nsmission ("te # T)("te &
A
A
*ut
!n+,
Steering g"te-
When A+1. /!n0 is Steered to /*ut0-3!-e-. the T)g"te
conducts4Thus *ut + , 5hen A+1
*ut + A,
S6m7olic or T)g"te: *ut!n
A is the control input #C!& Norm"l C! connected to A
,u77led C! connected to A
T)g"te conducts
5hen A+1-
A
A
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9e ersing the connection o A: A 7u77le C! A norm"l C!
*ut!nA
AT)g"te conducts 5hen A+;-
Multiplexer #MU
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(ener"li?"tion o the TT:
S =
; 11 1
111 =+= S S Z S =
; 11 ;
;1 += S S Z S =
S =
1 1; ;
;1 += S S Z
+ S
S =
; ! ;
1 ! 1
1; SI I S Z += is the unctionimplemented 76 the "7o e 2:1 MU
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!1
2:1MU!!B
S2 S1 S ;
E:1 MU
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eneral D2C- ierarc!ical Design of a & n :% 0U1
First select inputs based on S 0 , using 2 n-1 2:1 Muxes; 2 n-1
inputs get selected on 2 n-1 lines The problem no reduces to that
o! a 2 n-1 :1 Mux "ontinue recursi#el$ %to a 2 n-2 :1, 2 n-&:1,
'(, ):1, 2:1 Mux design problems* until the+nal output is obtained(
"ost 2 n -1 2:1 Muxes .%2 n -1* gate inputs % is the gate-i/p cost
o! a 2:1 Mux* "ompare to at design: "ost %n 1*.2 n %each 1 st le#el
34 gate has n select i/psand an 56 i/p !or hich the select i/p
combination at the 34 gate represents integer
6; there are 2 n such 34 gates* 2 n %2nd le#el 78 gate i/ps* %n
2*.2 n gate inputs% ill actuall$ re9uire more !or n ), as large
gates re9uired !or a 2-le#el impl( arenot desirable %e(g(, dri#ing
resistance become too large*( More expensi#e !or n )%!or 2-le#el
design, i! at all that is possible*, and e#en more expensi#e !or a
multi-le#el design( 3ote that both costs are exp( in n, but linear
in the m o! inputs %m 2 n*, hich isthe important parameter(
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Design Strategy:
2:1
2:1
2:1Sn)1 S1
2n)1
:1MU
