Lecture 04 Control Units.ppt

7/23/2019 Lecture 04 Control Units.ppt

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Control Unit :

Hardwired vs. Microprogrammed Approach

Dr Shankar Balachandran

Indian Institute o !echnolog" Madras

shankar#cse.iitm.ernet.in$% &cto'er ())*





Control Unit

Correct se1uencing o control signals

Much like human 'rain controlling various

parts o 'od"

Se1uence and timing is the ke" An" a'erration will result in wrong operation



A Simpliied Control Unit

Control Unit

2etch Unit

Decode Unit

34ecution Unit

0rite Back Unit

2etch

Decode

34ecute

0rite Back



A ,ossi'le Implementation

( to %

Decoder

CLK

Mod-3

Counter



!iming Diagram

CLK

Fetch

Decode

Execute

Write Back



5et6s Sample !he Signals

1

0

0

0

0

1

0

0

0

0

1

0

0

0

0

1



Another 0a" to 7enerate Signals

$ ) ) )

) $ ) )

) ) $ )

) ) ) $



Hardwired vs Microprogrammed

HardwiredUse gates to generate signals

S1uee8e out the +uice or perormance

Dierent logic st"les possi'le

MicroprogrammedStore the control signals in the se1uence

9ust read rom the memor" ever" clock c"cle



A Model Computerichard 3ckert- SI7CS3 Bulletin- ;ol. ()- <o. =- Septem'er $>??@

Accumulator

A5U

egister B

,C

MA

MD

AM

I

Control

?

?

$(

$(

$(

$(

$(

$(

$(

%

$(

Bus

0

5M

I,

5,

3,

5D

3D

5A

3A

S

A3U

5B

5I

3I



More Details

5 5oad

3 Cop" to 'us

A-S Add and Su'tract

Sign 'it to control unit

I, Increment ,C

ACC

A5U

B

,C

MA

MD

AM

I

ControlBus

0

5M

I,

5,

3,

5D

3D

5A

3A

S

A3U

5B

5I

3I



5DA5oad

Accumulator$ AMem@

$. MA I

(. MD MMA@=. A MD

3I-5M

3D-5A

S!AStore

Accumulator ( Mem@ A

$. MA I

(.MD A

=. MMA@ MD

3I-5M

3A-5D

0

ADD = A AB $. AA5UAdd@ A-3U-5A

SUB % A AB $. AA5USu'@ S-3U-5A

MBA E B A $. BA 3A-5B

9M, * ,C Mem $. ,CI 3I-5,

9< F ,C Mem

I Gve lagis set

$. ,CI i <2 is set <2 : 3I-5,

H5! ?$E Stop Clock

2etch I <e4tInstruction

$. MA ,C

(. MD MMA@

=. I MD

3,-5M

3D-5I-I,

Mnemonic &pcode Action egister !ransers Active

Controls



Hardwired Unit

I

Decoder Control

Matri4

5DA S!A

ADD

SUB

MBA

9M,

9<

ing Counter

<2

!E !$

Halt

&pcode

Control Signals

C5J



!a'le with Se1uencing

I, 5, 3, 5M 0 5D 3D 5I 3I 5A 3A A S 3U 5B

2etch !( !) !) !$ !( !(

5DA != !% !E != !E

S!A != !E !% != !%

MBA != !=

ADD != != !=

SUB != != !=

9M, != !=

9< !=K2

!=K2

I, !(L !$!%K5DAL 5I!(L

5, !=K9M,!=K9<K<2L 0!EK S!AL A !=KADDL

3, !)L 5D !%KS!AL S !=KSUBL5M !)!=K5DA!=KS!A 3D!(!EK5DAL ..



Control Matri4

Implement using discrete gates

Usuall" done using ,5As

5arge control matrices are implemented

hierarchicall"2or speed

A well known process and design lows

are widespread



An Alternate Implementation

IStarting

Address

7enerator

u,C

Control

Store

CLK

$

Microinstruction

egister

<2

N CD

MA,

$K

)$

))

Control

Map CD Meaning

$ K From IR

) )

Unconditional

Branch within Microprogram

) $

NF=0 => Increment

NF=1 =>

Conditional Branch

=( 4 (%

H5!

Control &M9ump Address

%'it

opcode

C t l St



Control Store

2etch )

)) ))$$)))))))))))) ) ) ) )$

)$ ))))$))))))))))) ) ) ) )(

)( $))))))$$))))))) ) $ ) OO

5DA $ )= )))$)))))$)))))) ) ) ) )%

)% ))))$))))))))))) ) ) ) )E

)E )))))))$))$))))) ) ) ) ))S!A ( )* )))$)))))$)))))) ) ) ) )F

)F ))))))$))))$)))) ) ) ) )?

)? )))))$)))))))))) ) ) ) ))

ADD = )> ))))))))))$)$)$) ) ) ) ))

SUB % )A ))))))))))$))$$) ) ) ) ))MBA E )B )))))))))))$)))$ ) ) ) ))

9M, * )C )$)))))))$)))))) ) ) ) ))

9< F )D )))))))))))))))) $ ) ) )2

)3 )))))))))))))))) ) ) ) ))

)2 )$)))))))$)))))) ) ) ) ))34pansion ?3 $)$3

Instruction &pCodeuInstruction

Address Control Signals CD MA, H5! Addr. & <e4t

Control 0ord

3 l $ MBA ll d ' ADD



34ample $ G MBA ollowed '" ADD

2etch )

)) ))$$)))))))))))) ) ) ) )$

)$ ))))$))))))))))) ) ) ) )(

)( $))))))$$))))))) ) $ ) OO

5DA $ )= )))$)))))$)))))) ) ) ) )%

)% ))))$))))))))))) ) ) ) )E

)E )))))))$))$))))) ) ) ) ))

S!A ( )* )))$)))))$)))))) ) ) ) )F

)F ))))))$))))$)))) ) ) ) )?

)? )))))$)))))))))) ) ) ) ))

ADD = )> ))))))))))$)$)$) ) ) ) ))

SUB % )A ))))))))))$))$$) ) ) ) ))

MBA E )B )))))))))))$)))$ ) ) ) ))

9M, * )C )$)))))))$)))))) ) ) ) ))

9< F )D )))))))))))))))) $ ) ) )2

)3 )))))))))))))))) ) ) ) ))

)2 )$)))))))$)))))) ) ) ) ))

34pansion ?3 $)$3

)B)>

L

B

E

U

SAE

A

L

A

E

I

L

I

E

D

L

D

WRL

M

E

P

L

P

I

P



Se1uence or MBA-ADD

$. MA ,C

(. MD MMA@

=. I MD

BA $. MA ,C

(. MD MMA@

=. I MD

AA5UAdd@

))$$))))))))))))

))$$))))))))))))

))))$)))))))))))

))))$)))))))))))

$))))))$$)))))))

$))))))$$)))))))

)))))))))))$)))$

))))))))))$)$)$)

M&; B-A

ADD

LESAELELELWRLELI



34ample ( G 9< with

2lag Set

2etch )

)) ))$$)))))))))))) ) ) ) )$

)$ ))))$))))))))))) ) ) ) )(

)( $))))))$$))))))) ) $ ) OO

5DA $ )= )))$)))))$)))))) ) ) ) )%

)% ))))$))))))))))) ) ) ) )E

)E )))))))$))$))))) ) ) ) ))

S!A ( )* )))$)))))$)))))) ) ) ) )F

)F ))))))$))))$)))) ) ) ) )?

)? )))))$)))))))))) ) ) ) ))

ADD = )> ))))))))))$)$)$) ) ) ) ))

SUB % )A ))))))))))$))$$) ) ) ) ))

MBA E )B )))))))))))$)))$ ) ) ) ))

9M, * )C )$)))))))$)))))) ) ) ) ))

9< F )D )))))))))))))))) $ ) ) )2

)3 )))))))))))))))) ) ) ) ))

)2 )$)))))))$)))))) ) ) ) ))

34pansion ?3 $)$3

H5! 2 $2 )))))))))))))))) ) ) $ OO

)D

CD

I negative 25A7 is set- +ump to a new location '" skipping to uInstruction at )2

L

B

E

U

SAE

A

L

A

E

I

L

I

E

D

L

D

WRL

M

E

P

L

P

I

P

LESAELELELWRLELI



34ample = G 9< with

2lag <ot Set

2etch )

)) ))$$)))))))))))) ) ) ) )$

)$ ))))$))))))))))) ) ) ) )(

)( $))))))$$))))))) ) $ ) OO

5DA $ )= )))$)))))$)))))) ) ) ) )%

)% ))))$))))))))))) ) ) ) )E

)E )))))))$))$))))) ) ) ) ))

S!A ( )* )))$)))))$)))))) ) ) ) )F

)F ))))))$))))$)))) ) ) ) )?

)? )))))$)))))))))) ) ) ) ))

ADD = )> ))))))))))$)$)$) ) ) ) ))

SUB % )A ))))))))))$))$$) ) ) ) ))

MBA E )B )))))))))))$)))$ ) ) ) ))

9M, * )C )$)))))))$)))))) ) ) ) ))

9< F )D )))))))))))))))) $ ) ) )2

)3 )))))))))))))))) ) ) ) ))

)2 )$)))))))$)))))) ) ) ) ))

34pansion ?3 $)$3

H5! 2 $2 )))))))))))))))) ) ) $ OO

)D

CDCD

L

B

E

U

SAE

A

L

A

E

I

L

I

E

D

L

D

WRL

M

E

P

L

P

I

P



5et6s eview the

Microprogramming Model Store the microprogram in control store

2etch the instruction

7et the set o control signals rom the

control word

Move the microinstruction address

5ather- inse- epeat



0hat is Microcode/

Michael SlaterPs QMicroprocessor Based DesignQ pg.%(@:

Microcode tells the processor every detailed steprequired to execute each achine lan!ua!e instruction"Microcode is thus at an even ore detailed level thanachine lan!ua!e# and in $act de$ines the achinelan!ua!e" %n a standard icroprocessor# the icrocodeis stored in a &'M or a pro!raa(le lo!ic array )*+,that is part o$ the icroprocessor chip and cannot (eodi$ied (y the user".



!hought 34periment

0h" is the design a little clums"/

0hat can we do a'out it/



eason or Clumsiness

9< G Conditional 2lag check

0ithout an" condition check- the whole

process is ver" smooth

Solution G Avoid all conditional checks



eal 5ie

A little American 2oot'all Stor" !heor" vs. ,ractice

%n theory# there is no di$$erence (et/eentheory and practice

%n practice# theory and practice are t/odi$$erent thin!s alto!ether

5ive with condition checksJeep designs as clean as possi'le



A 7eneral Approach

I

Starting

and Branch

Address

7enerator

u,C

Control

Store

Control 0ord

34ternal Inputs

Conditional Codes



2ormat o Microinstructions

,ick "oursRour choice is as 'est as "our neigh'or6s

0hat we did :&ne 'it position per control signal&rder o the 'its /

Don6t matter Can result in long microinstructions

<ot the num'er o microinstructions- 'ut the width



A <ote A'out Densit"

&'serve that onl" a ew 'its are set to $

,oor usage o 'it space

!his scheme is called oriontal

Micropro!ra

Alternate ;ersion : 3ncode the 'its2ertical Micropro!ra



;ertical Microprogram

3ncode the 'its '" grouping similarelements together

7eneral Idea :7roup similar resources together

!here can 'e onl" one source or destinationregister

Some operations are mutuall" e4clusive ead vs 0rite o memor"



Design Issues

3ncoding reduces the 'itspaceBut re1uires decoders

Cost o decoder vs 'itspaceUsuall" decoder cost is ver" low



Another Idea

7roup concuurentl" active signals

3ver" meaningul com'ination gets a code

Comple4 decoder to interpret ever" code



;ertical vs Hori8ontal

Hori8ontal2aster

More areaMore common currentl"

Cheap transistors

;erticalSlower More microinstructions



Microse1uencing

&ther wa"s to save on hardware

3ver" instruction had its own

microprogram se1uence Also- instructions have several addressing

modes

&nl" the irst ew microinstructions dier

Can we share microcode/



A ,owerul !echni1ue in Sharing

Bit&ing 34ample !wo instructions share some microcode

3ventuall"- must 'ranch !he deault 'ranch one instruction6s@ is O) !he other 'ranch is stored at O$ Change the least signiicant 'its/@ to get a new address

Compare that with : Having two conditional 'ranches Store two ields- one or each 'ranch Both ver" unclean



!hought 34periment :

0hat i we provided e4plicit 'ranch

instead o storing ne4t ield in our

microprogram/ !"pical instruction set will need a lot o

'ranches

5ot o time will 'e wasted on 'ranching



A ,at on &ur Back

0e provided e4plicit ield or addressBranch location is now data

It is alread" saved

Caution :Microinstruction can get ver" wide

Solution :!here is no ree lunch.



Can we pipeline microetch/

A neat idea : 0h" wait till the current microop is over/ Branch ield gives ne4t operation

7et the ne4t op Caveat :

34ternal inputs and status lags ma" change the order 0hat a'out interrupts/

!he" are going to ollow "ou ever"where

Should have a mechanism that can invalidate microcodepreetch Similar to pipeline lush or instructions

Commonl" used



Historical ,erspectives

Hardwired 5ogic ,opular 'eore *)6s

&nl" wa" people did it

,opular now Speed Beneits

Microprogram ,opular in F)6s

Memor" was slower than C,U

<o onchip cache Best wa" is to store the microcode

<ow G Depends on who "ou ask/

Shades o gra" : 34tremes o spectrum are harder to ind nowada"s



!ools or Design

Hardwired An" state machine optimi8er Assigning states- minimi8ing tranisitions- races-

ha8ards-..

Microcoding Small ones can 'e in 'inar" 5arge ones G Use microassem'ler

;er" useul de'ug tool Can use microassem'ler simultaneousl" with actual hardware

development



Hardwired vs Microcoding

Hardwired units are aster and smaller 3mulation is eas" with microcoding

Hardwired design is comple4 i large Bugs in hardwired design cannot 'e i4ed

in ield

Hardwired control is not suited or loops5ooping with microcode can 'e made as ast



Hardwired vs Microcode vs ISC

ISC Simpler instruction set

Hardwired Implementation

ISC instructions are like microcodes Instructions come rom ICache instead o Control

Store

Dierence : Contents are not i4ed

Advantage : &nl" load what "ou want on the ICache Jeeps si8e smaller as compared to Control Stores



Microprogram vs Sotware Imagine 2loating ,oint Division

Solution $ : 0rite in sotware 5ong process

3rror proneMan" etches repeatedl" rom memor" or the given

se1uence o operations

Solution ( : Microcode 5ong process too G 'ut designer6s not programmers

elativel" error ree G more thorough design

e1uires man" c"cles 'ut etched and used locall"



3mulation A ver" common use o microcoding IBM S"stem=*)

=( 'it architecture $*'it registers

Secret : Most implementations were ?'it

Jeep cost low

Heav" microcoding ,rogrammers o'livious

In $>>(- International Meta S"stems IMS@ announcedthe =(E) Designed to emulate the 4?*- *?J- and *E)( architectures Uses customi8a'le microcode- among other techni1ues 0ent 'ust- never released



Another Interesting <ote

0rita'le Control Store0hat i "ou- a programmer- can write "our

own control store/<ot a mad scientist thought

Implemented in;AO ??)),D,$$*) IBM S"stem=F)



Current !rends

Microcode Update

5inu4 Utilit" icrocodectl

Companion to IA=( microcode driver It decodes and sends new microcode to the kernel

driver to 'e uploaded to Intel IA=( processors

Update is volatile G lost on re'oots

Microcode updates are also rolled into BI&Supdates t"picall" ead" even 'eore an &S is loaded



Intel Said..

!he ,entium@ ,ro processor and ,entium@ II processor ma"

contain design deects or errors known as errata that ma" cause the

product to deviate rom pu'lished speciications. Man" times- the

eects o the errata can 'e avoided '" implementing hardware or

sotware workarounds- which are documented in the ,entium ,ro

,rocessor Speciication Update and the ,entium II ,rocessor

Speciication Update. ,entium ,ro and ,entium II processors include a

eature called Qreprogramma'le microcodeQ- which allows certain t"pes

o errata to 'e worked around via microcode updates. !he microcode

updates reside in the s"stem BI&S and are loaded into the processor '" the s"stem BI&S during the ,ower&n Sel !est- or ,&S!.



Current !rends

H"perthreading in ,% A second logical C,U

Complete state o the s"stem in 'oth C,Us

Microcoding in ,%!wo pointers control low independentl"

Both processors share the &M entries Access is alternated 'etween the C,Us



!hank Rou

Documents

Lecture 04 Control Units.ppt