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Lecture 15:Extra More on Sinusoidal Steady-State Analysis & MT ReviewNilsson & Riedel 9.7-9.9, 9.12
ENG17 (Sec. 2): Circuits I
Spring 2014
May 20, 2014
13
Example
Use phasor diagram to find R that will cause resistor current (iR) to lag the source current (iS) by 45° when ω = 5 krad / s.