Lecture 20

Transistor Amplifiers (II)

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Contents:

Common-drain amplifier

Common-gate amplifier

Key questions

What other amplifier stages can one build with a

single MOSFET and a current source?

What is the uniqueness of these other stages?

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2. Common-drain amplifier

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5

How does it work?

•VGG, ISUP, and W/L selected to bias MOSFET in saturation, obtain

desired output bias point, and desired output swing.

•vGG ↑⇒ iD can’t change ⇒ vOUT ↑ (source follower)

• to first order, no voltage gain:

• but Rout small: effective voltage buffer stage (good for making

voltage amp in combination with common-source stage).

out sv v

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Small-signal analysis

Unloaded small-signal equivalent circuit model:

Then:

( / / )

in gs out

out m gs o oc

v v v

v g v r r

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/ /

mvo

m

O OC

gA

gr r

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Input impedance: Rin = ∞

Output impedance:

Small!

Loaded voltage gain:

1 1

1

/ /

out

mm

O OC

Rg

gr r

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L Lv vo

L outL

m

R RA A

R RR

g

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Effect of back bias: If MOSFET not fabricated on isolated p-well, then body is

tied up to wafer substrate (connected to VSS):

Two consequences:

Bias affected: VT depends on

Small signal figures of merit affected: signal shows up between B and S

(vBS = −vout).

0BS SS OUTV V V

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Small signal equivalent circuit model:

11

/ /

m mvo

m mbm mb

O OC

g gA

g gg g

r r

1 1

1

/ /

out

m mbm mb

O OC

Rg g

g gr r

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Relationship between circuit figures of merit and device parameters:

CD amp useful as a voltage buffer to drive small loads (in a

multistage amp, other stages will be used to provide voltage gain).

2m n ox D

Wg C I

L 2 2

mb m

p BS

g gV

3. Common gate amplifier

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Need to handle current mode signal sources:

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How does it work?

• Since source is signal input terminal, body cannot be tied up to

source (Csb is significant)

• iSUP, IBIAS, and W/L selected to bias MOSFET in saturation,

obtain desired output bias point, and desired output swing.

• no current gain: is = iout (current buffer)

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Bias: select ISUP, IBIAS, and W/L to get proper quiescent IOUT

and keep MOSFET in saturation

Select bias so that IOUT =0=> VOUT =0.

Assume MOSFET in saturation

(no channel modulation):

but VT depends on VBS:

Must solve these two equations iteratively

to get VS.

0SUP OUT BIASI I I

2( )2

D n ox GS T SUP BIAS

WI C V V I I

L

( 2 2 )T To n p BS pV V V

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Small signal circuit (unloaded)

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Not surprising, since in a MOSFET: ig =0.

1outs out io

s

ii i A

i

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Input resistance:

Do KCL on input node:

Then:

Very small.

( / / )0t OC L t

t m t mb t

o

v r R ii g v g v

r

/ /1

1

1

OC L

Oin

m mbm mb

O

r R

rR

g gg g

r

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Output resistance:

Do KCL on output node:

Notice also:

Then:

Very large, because of the feedback effect of RS.

0t gs

t m gs mb gs

O

v vi g v g v

r

gs t Sv i R

1

/ / 1 / / (1 )out OC O S m mb OC O m S

O

R r r R g g r r g Rr

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Summary of MOSFET amplifier stages:

In order to design amplifiers with suitable performance, need

to combine these stages ⇒multistage amplifiers

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CMOS multistage voltage amplifierGoals:

• high voltage gain

• high Rin

• low Rout

•Good starting point: CS stage

( / / ),

/ / ,

in

vo m O OC

out O OC

R

A g r r probably insufficient

R r r too high

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Add second CS stage to get more gain:

1 1 1 2 2 2

2 2

( / / ) ( / / )

/ / ,

in

vo m O OC m O OC

out O OC

R

A g r r g r r

ButR r r still high

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Add CD stage at output:

31 1 1 2 2 2

3 3

3 3

( / / ) ( / / ) , still high

1,now small

in

mvo m O OC m O OC

m mb

out

m mb

R

gA g r r g r r

g g

Rg g

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Amplifier requirements are often demanding:

• must adapt to specific kinds of signal source and load,

• must deliver sufficient gain

Single-transistor amplifier stages are very limited in what

they can accomplish

⇒ multistage amplifier.

Key conclusionsDifferent MOSFET stages designed to accomplish different goals:

• Common-source stage:

large voltage gain and transconductance, high input resistance, large

output resistance

excellent transconductance amplifier, reasonable voltage amplifier

• Common-drain stage:

no voltage gain, but high input resistance and low output resistance

good voltage buffer

• Common-gate stage:

no current gain, but low input resistance and high output resistance

good current buffer

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