LECTURE 28 DIFFERENTIAL-IN, DIFFERENTIAL-OUT OP AMPS · 2018-08-28 · LECTURE 28 – DIFFERENTIAL-IN, DIFFERENTIAL-OUT OP AMPS LECTURE ORGANIZATION Outline • Introduction • Examples

Lecture 28 – Differential-In, Differential-Out Op Amps (6/25/14) Page 28-1

CMOS Analog Circuit Design © P.E. Allen - 2016

LECTURE 28 – DIFFERENTIAL-IN, DIFFERENTIAL-OUT OP

AMPS

LECTURE ORGANIZATION

Outline

• Introduction

• Examples of differential output op amps

• Common mode output voltage stabilization

• Summary

CMOS Analog Circuit Design, 3rd Edition Reference

Pages 386-397



INTRODUCTION

Why Differential Output Op Amps?

• Cancellation of common mode signals including clock feedthrough

• Increased signal swing

• Cancellation of even-order harmonics

Symbol:

v1

v2

v1-v2t

t

t

A

-AA

-A

2A

-2A Fig. 7.3-1



Common Mode Output Voltage Stabilization

If the common mode gain not small, it may cause the common mode output voltage to

be poorly defined.

Illustration:

Remember that:

vOUT = Avd(vID) ± Acm(vCM)

VDD

vod

t

070506-01

VSS

0

VDD

vod

t

VSS

0

VDD

vod

t

VSS

0

CM output voltage properly defined,

Vcm = 0

CM output voltage too large,

Vcm= 0.5VDD

CM output voltage too small,

Vcm= 0.5VSS



EXAMPLES OF DIFFERENTIAL OUTPUT OP AMPS (OTA’S)

Two-Stage, Miller, Differential-In, Differential-Out Op Amp

Note that the

upper ICMR is

VDD - VSGP + VTN

(OCMR) = VDD+ |VSS| - VSDP(sat) - VDSN(sat)

The maximum peak-to-peak output voltage 2·OCMR

Conversion between differential outputs and single-ended outputs:

vi1 M1 M2

M3 M4

M5

M6M8

VDD

VSS

VBN+

-

Cc

M9

Cc

VBP+

-

vi2

vo1vo2RzRz

M7

Fig. 7.3-3



Two-Stage, Miller, Differential-In, Differential-Out Op Amp with Push-Pull Output

Comments:

• Able to actively source and sink output current

• Output quiescent current poorly defined

vi1M1 M2

M3 M4

M5

M6

M7

VDD

VSS

VBN+

-

Cc

M9

Cc

VBP+

-

vi2

vo1 vo2RzRz

M8

Fig. 7.3-6

M10 M12

M13

M14



Folded-Cascode, Differential Output Op Amp

• No longer has the low-frequency asymmetry in signal path gains.

• Class A

060717-01

VPB1

M4 M5

I6 VPB2

I4 I5

VDD

I7M6 M7

VNB2

M8 M9

M10M11

+

-vIN

vOUT

VNB1

I1 I2

M1 M2

M3I3

CL

VNB1

+-CL



Enhanced-Gain, Folded-Cascode, Differential Output Op Amp

What about the A amplifier?

Below is the upper A amplifier:

Note that VBias controls the dc voltage at the

input of the A amplifier through the negative

feedback loop.

• Balanced inputs

• Class A

060718-02

VDD

VPB1

VPB2 VPB2

VNB1 VBias

vin+ vin

-

vout+vout

- M1M2 M3

M4

M5 M6

M7 M8

M9 M10

M11M12

060718-01

vOUT

M4M5

M3

M7

M8 M9

M10 M11

M6

VDD

VPB1

+

-

vIN

M1 M2

VNB1

A+- +

-

+- +

-A

+-

VPB1



Push-Pull Cascode Op Amp with Differential-Outputs

• Output quiescent currents are well defined

• Self-biased circuits can be replaced with VNB2 and VPB2

VDD

VSS

VBias

R2 M22

M23

R1

M19

M20

M1 M2

M3 M4M5 M6M7 M8

M9 M10

M11

M12M13

M14

M15 M16M17

M18

M21

vo1

vi1 vi2vo2

Fig. 7.3-8



Folded-Cascode, Push-Pull, Differential Output Op Amp

I6 = I7 = I14 = I15 > 0.5I5

I5 = I1 + I2 + I3 + I4

Av = gmRout(diff)

060717-02

VPB1

M6 M7

I6

VPB2I4

I7

I9M8 M9

VNB2

M10 M11

M12 M13

+

-vIN

vOUTVNB1

I3

I2

M2 M3

M5I5

CL+-CL

I1

M1

VNB2

M18M19

M20M21

VPB1

M14 M15

I16 VPB2

I14 I15

VDD

I17

M16 M17

M4

I8

0.5gm1vin

0.5gm3vin

0.5gm2vin

0.5gm4vin

0.5gm3vin

0.5gm4vin0.5gm2vin

0.5gm1vin



Enhanced-Gain, Folded-Cascode with Push-Pull Outputs

• Gain approaches gm3rds

3

060718-06

VPB1

M6 M7

M8 M9

M20

M19

M18

M21

+

-vIN

VNB1

M2 M3

M5CL+-CL

M1

VNB2M14

M17M16

M15

VPB1

M10 M11

VPB2

VDD

M12 M13

M4

vOUT

A+- +

-

+- +

-AVNB2



Cross-Coupled Differential Amplifier Stage

The cross-coupled input stage allows the push-pull output quiescent current to be well

defined.

Operation:

Voltage loop vi1 - vi2 = -VGS1+ vGS1 + vSG4 - VSG4 = VSG3 - vSG3 - vGS2 + VGS2

Using the notation for ac, dc, and total variables gives,

vi2 - vi1 = vid = (vsg1 + vgs4) = -(vsg3 + vgs2)

If gm1 = gm2 = gm3 = gm4, then half of the differential input is applied across each

transistor with the correct polarity.

i1 = gm1vid

2 =

gm4vid

2 and i2 = -

gm2vid

2 = -

gm3vid

2

M1 M2

M3 M4

VGS2

VSG4

VGS1

VSG3

i1

i1i2

i2

vi1 vi2

Fig. 7.3-9

vGS1+

-

vSG4

+

-vSG3

+

-

vGS2+

-



Class AB, Differential Output Op Amp using a Cross-Coupled Differential Input

Stage

Quiescent output currents are defined by the current in the input cross-coupled

differential amplifier.

M1 M2

M3 M4

M5 M6

M7

VDD

VSS

VBias+

-

R1

M24

M25

R2

M27

M28

M8M9 M10

M11 M12

M13

M14

M15

M16

M17 M18

M19 M20

M21 M22

M26

M23

vo2

vi2vi1

vo1

Fig. 7.3-10



COMMON MODE OUTPUT VOLTAGE STABILIZATION

Common Mode Feedback Circuits

Because the common mode gain is undefined, any common mode signal at the input

can cause the output common mode voltage to be improperly defined. The common

mode output voltage is stabilized by sensing the common mode output voltage and using

negative feedback to adjust the common mode voltage to the desired value.

Model for the Output of Differential Output Op Amps:

Roi represents the self-resistance of the output sink/sources.

1.) If the common mode output voltage increases the sourcing current is too large.

2.) If the common mode output voltage decreases the sinking current is too large.

VDD

io1(source) Ro1

vo1

io1(sink) Ro3

io2(source)

io2(sink)

Ro2

Ro4

vo2

VDD

io1(source) Ro1

vo1

Io1(sink) Ro3

io2(source)

Io2(sink)

Ro2

Ro4

vo2

Class A Output Push-Pull Output 060718-08



Conceptual View of Common-Mode Feedback

Function of the common-mode feedback circuit:

1.) If the common-mode output voltage increases, decrease the upper currents sources or

increase the lower current sink until the common-mode voltage is equal to VCMREF.

2.) If the common-mode output voltage decreases, increase the upper currents sources or

decrease the lower current sink until the common-mode voltage is equal to VCMREF.



Two-Stage, Miller, Differential-In, Differential-Out Op Amp with Common-Mode

Feedback

Comments:

• Simple

• Unreferenced – value of common mode output voltage determined by the circuit

characteristics

vi1 M1 M2

M3 M4

M5

M6M7

VDD

VSS

VBN+

-

Cc

M9

Cc

VBP

+

-

vi2

vo1vo2RzRz

M8

Fig. 7.3-12

M10 M11



Common Mode Feedback Circuits

Implementation of common mode feedback circuit:

This scheme can be applied to any differential output amplifier.

CM Loop Gain = -gmC1Ro1 which can be large if the output of the differential output

amplifier is cascaded or a gain-enhanced cascode.

The common-mode loop gain may need to be compensated for proper dynamic

performance.

060718-10

vi1M1 M2

M3 M4

M5

VDD

IBias

VCM

vo1

MC2A

MC2B

MC1

MC3

MC4

MC5MB

I3 I4IC4

IC3Common-

mode feed-

back circuit

Ro1 Ro2

vi2

vo2



Common Mode Feedback Circuits – Continued

The previous circuit suffers when the input common mode voltage is low because the

transistors MC2A and MC2B have a poor negative input common mode voltage.

The following circuit alleviates this disadvantage:

060718-11

vi1M1 M2

M3 M4

M5

VDD

IBias

VCM

vo2vo1

vi2MC2MC1

MC3

MC4

MC5MB

I3 I4

IC4IC3

Common-

mode feed-

back circuitRCM1

RCM2



An Improved Common-Mode Feedback Circuit

The resistance loading of the previous circuit can be avoided in the following CM

feedback implementation:

This circuit is capable of sustaining a large differential voltage without loading the

output of the differential output op amp.

VDD

060718-12

VCMREF

RCM RCM

vo1 vo2

CM Correction Circuitry

M1 M2 M3 M4

M5 M6



Frequency Response of the CM Feedback Circuit

Consider the following CM feedback circuit implementation:

The CM feedback path has two poles – one at the gates of M10 and M11 and the

dominant output pole of the differential output op amp.

Can compensate with Miller capacitors as shown.

070506-02

VPB1

M4 M5

VPB2

VDD

M6 M7

VNB2M8

M10

M11

+

-vIN

vOUT

VNB1

M1 M2

M3 VCMREF

+-

M9

M12

M13 M14

M15 M16

CcCc



Improved CM Feedback Frequency Response

The circuit on the previous page can be modified to eliminate the pole at the gates of

M10 and M11 as follows:

• The need for compensation of the common mode loop no longer exists since there is

only one dominant pole

• The dominant pole of the differential amplifier becomes the dominant pole of the

common mode feedback

060718-14

VPB1

M4 M5

VPB2

VDD

M6 M7

VNB2M8

M10 M11

+

-vin

vo1

VNB1

M1 M2

M3

VCMREF

M9

M12

M13 M14

M16M15

VNB1

VNB2

M17

M18M19

vo2



Implications of the Common Mode Feedback Correction Bandwidth

We have seen from the previous slides that the bandwidth of the common mode feedback

correction circuit can be equal, less, or larger than the bandwidth of the differential gain

of the op amp.

Common mode feedback BW < Differential mode BW:

- Common mode feedback correction circuit responds slower than the differential

output voltage changes

- It is possible that the CM feedback correction circuit will not correct for the

highest frequency CM disturbances and the differential output signal may be

saturated or clipped

Common mode feedback BW ≈ Differential mode BW:

- The CM feedback correction circuit should be able to correct for all CM

disturbances

- The compensation of the differential mode can be used for the CM feedback

correction circuit

Common mode feedback BW > Differential mode BW:

- The CM feedback correction circuit will be able to correct for all CM disturbances

- Difficult to keep stable because of higher BW and can amplify noise



A Common Mode Feedback Correction Scheme for Discrete Time Applications

Correction Scheme:

Operation:

1.) During the 1 phase, both Ccm are charged to the desired value of Vocm and CMbias

= Vocm.

2.) During the 2 phase, the Ccm capacitors are connected between the differential

outputs and the CMbias node. The average value applied to the CMbias node will be

Vocm.



Example of a Common-Mode Output Voltage Stabilization Scheme for Discrete-

Time Applications

Common mode

adjustment phase:

Switches S1, S2 and S3

are closed. C1 and C2

are charged to the value

necessary for I12 and I13

to keep the common

mode output voltage at

VCM.

Amplification phase:

Switches S4 and S5 are

closed. If the common

mode output voltage is

not at VCM, the currents I12 and I13 will change to force the value of the common mode

output voltage back to VCM.

070506-03

VPB1

M4 M5

VPB2

VDD

M6 M7

VNB2M8

M10 M11

+

-vIN

vOUT

VNB1

M1 M2

M3

VCM

+-

M9

M12 M13 M14

M15

C1

C2

VNB1

S4

S5

S1

S2

S3

I12

I13

Discrete time common

mode correction circuit



Correction of Channel Charge and Clock Feedthrough

In the discrete-time common mode correction schemes, the switches can introduce

error due to channel charge and clock feedthrough.

Through simulation, these errors can be predicted and corrected by applying a

correction signal superimposed upon the error signal to achieve the desired (target)

common mode voltage.

General principle:



SUMMARY

• Advantages of differential output op amps:

- 6 dB increase in signal amplitude

- Cancellation of even harmonics

- Cancellation of common mode signals including clock feedthrough

• Disadvantages of differential output op amps:

- Need for common mode output voltage stabilization

- Compensation of common mode feedback loop

- Difficult to interface with single-ended circuits

• Most differential output op amps are truly balanced

• For push-pull outputs, the quiescent current should be well defined

• Common mode feedback schemes include,

- Continuous time

- Discrete time

Documents

LECTURE 28 DIFFERENTIAL-IN, DIFFERENTIAL-OUT OP AMPS · 2018-08-28 · LECTURE 28 – DIFFERENTIAL-IN, DIFFERENTIAL-OUT OP AMPS LECTURE ORGANIZATION Outline • Introduction • Examples