Lecture 4 Multiplier using FPGA

2007/09/28

Prof. C.M. Kyung

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1. GOAL is

(1) How to design more complex combinational circuit, multiplier, using HDL(Hardware Description Language) for a wide range of logic system.

(2) How to analyze and implement the two basic combinational multiplier forms-“array multiplier” and “parallel multiplier”.

(3) In particular, how to represent the multiplier through sequential circuit instead of combinational circuit.

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2. Multiplication(1) Multiplication for binary numbers

0 x 0 = 0, 0 x 1 = 0, 1 x 0 = 0, 1 x 1 = 1

(2) Shifting & adding operation (partial product & sum of product)

)(1000010

0000

)1000010(

1011

)10110(

1011

0000

)(0110

)(1011

productspartialforthaddingaftersumproductfinal

productpartialforth

productspartialthirdaddingaftersum

productpartialthird

productspartialtwofirstofsum

productpartialsencond

productpartialfirst

multiplierX

ndmultiplicaA

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3. Multiplier (1) Array multiplier

(2) Parallel multiplier

(3) Sequential multiplier

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3. Multiplier

(1) Array multiplier - Partial product generation and accumulation are

merged

A3X1

A2X1 A1X1 A0X1

A3X2

A3X3

A0X2A2X2 A1X2

A0X3A1X3A2X3

FA

FA

FA

FAFA

FAFA

FAFA

FA FAFA 0

000

A3X0 A0X0A1X0A2X0

P3P4P5P6P7 P0P1P2

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3. Multiplier

(1) Array multiplier - Partial product generation and accumulation are merged

- Classic shift-add multiplication- Adder structure used to combine all the bit products in a multiplier- Logical bit products AND of the bits from each input- Basic structure is simple to implement in FPGAs- Not make efficient use of the logic in many FPGAs- Larger and slower than other implementations

- Ripple carry array multiplier (also called row ripple form) - Carry save array multiplier

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3. Multiplier(1) Array multiplier

Ripple carry array multiplier

Carry save array multiplier

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(2) Parallel multiplier - High-speed multiplication Array Multiplier

- Reduce the number of partial products.- Speed up the multiplication. - The gain in speed is obtained at the expense of extra hardware. - Parallel multiplier can be implemented so as to support a high rate of pipelining.

Adder treeAdder tree

partial products multiplicand

resultresult

multiplier

Adder arrayAdder array

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(2) Parallel multiplier

: (3,2) counter 입력 : (2,2) counter 입력 : (3,2) counter와 (2,2) counter의 출력

Ripple Carry Adder

HA

HA

HA

FA

FA

FA

FA

FA

FA

FA

FA

FAFA

☞Carry save addition

Parallel multiplier

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(3) Sequential multiplier

- U = XA- Representation of X : signed-magnitude : 2’s complement : 1’ complement

- If X is positive,

P(j+1) = (P(j) + xj A) 2-1; j = 0,1,...,n-2, P(0) = 0

U = 2n-1P(n-1)

accumulated partial

products

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3. Problem statement

(1) Design m*n (unsigned) array multiplier

(2) Design k*k (unsigned) parallel multiplier

(3) Design k*k (unsigned) sequential multiplier

(4) For each multiplier(1~3), Verilog coding & simulation

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4. Experiment Requirements

(1) Verilog

(2) Quartus II

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5. References & Contact

(1) Textbook- Randy H. Katz, Contemporary Logic Design, (1994)

- Charles H. Roth Jr., Fundamentals of Logic Design, (2004)- Israel Koren, Computer Arithmetic Algorithms, (2002)

(2) 4th Week T.A. E-mailbs_choi@kaist.ac.kr arashi@odyssey.kaist.ac.kr (Ext. 8032)

(3) Lecture Homepage http://wink.kaist.ac.kr/course/ee306/