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ECE 551 - Digital System Design & Synthesis

Lecture Set 11 - Physical Design and Logic

Synthesis

Overview - 1� Physical Design Concepts

� Technology library components

� Layout elements and architectures

� Physical design flow

• Floorplanning

• Placement

• Routing

• Checking

• Engineering Change Orders (ECOs)

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Overview - 2

� Interaction of Physical Design With Synthesis

� Locations of interactions within flow

� Information interchange

� Physical versus logical hierarchy

� Synthesis/physical design strategies

� Synopsys Physical Compiler

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References

� Floorplan Manager - User Guide -Synopsys - Appendix A and Chapter 3

� Using LSI Logic and Synopsys Design Tools and Libraries - LSI Logic

� Design Compiler Reference Manual: Optimization and Timing Analysis -Chapter 9 - Links to Physical Design Tools

� Physical Compiler - User Guide - Synopsys

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Physical Design Concepts

� Technology library components

� Layout elements

� Physical design flow

� Physical Design Tool

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Technology Library

Components

� Logical or Synthesis Library� Logical design rules

� Cell function

� Cell timing data

� Physical Library� Physical design rules - process design rules and

electrical design rules

� Cell data - dimensions, pin location/dimensions, blockages, and timing information

� Technology data - values for layout elements such as wiring capacitance and resistance per unit length; die characteristics

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Layout Elements - 1

� Figure A-5 FPM (see next slide)

� Core

� Cell sites

� Cell rows (depends on style)

� Routing channels (depends on style)

� I/O pad ring

� Layout architectures previously covered

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Layout Elements - 2

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Physical Design Flow - 1

�Fig. A – 7 FPM (See next slide)

�Floorplanning

�Placement

�Routing

�Checking

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Physical Design Flow - 2

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Floorplanning

� Initial layout of hierarchical blocks in the design

� Floorplan attributes:

� Physical hierarchy

� Approximate location of hierarchical instances

� Approximate routing

� I/O pad placement

� Gives approximate data that is more accurate than, for example, statistical wire model data

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Placement

� Finalizing the exact location and orientation of the leaf instances in the design

� Objective of placement - typically minimize wire length within given constraints

� Major computational task requiring iteration

� Gives approximate data that is more accurate than floorplanning data

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Routing - 1

� Interconnects placed instances of cells

� Objective - minimize wire length and wire congestion within given constraints

� Use of channel-routing, over-the-cell routing, and routing layers

� Major computational task requiring iteration

� Provides the most accurate delay data

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Routing - 2

�Routing Stages

� Global routing - identifies general path for each net relative to other nets

� Detailed routing - implements specific paths based on the general paths obtained from global routing

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Checking

� Physical Design Rule Check

� Electrical Design Rule Checks

� Physical design verification against logical netlist.

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Engineering Change Orders

(ECOs)

� Minor incremental changes in a design that make changes only to deal with a specific problem.

� Affect only small part of netlist

� Applications: � Problem fixes late in the design process

� Changes in versions after chip deployed

� Examples: timing failure - add or delete logic to solve; design rule violation - change to faster drivers

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Interactions of Physical

Design with Synthesis - 1

� Location of Interactions within Flow� See Fig. A – 7 (See slide 9)

� Classical: Synthesis -> Full Physical Design -> Resynthesis -> Incremental Physical Design

� Modern: Synthesis -> Floorplanning -> Resynthesis … -> Placement -> … Resynthesis -> … -> Routing -> Resynthesis -> Incremental Placement -> Incremental Routing -> … -> Checking

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Interactions of Physical

Design with Synthesis - 2

�What are the advantages of modern approach?� Avoids repetition of compute-intensive

placement

� Avoids repetition of compute-intensive routing

� Gets interconnect delay information into synthesis at an early stage

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Information Interchange

� Forward annotation: synthesis -> physical design� Design netlist (EDIF, VHDL, Verilog)

� Design constraints (path delays, worst case path delays)(SDF -Standard Delay Format)

� Cluster information (PDEF - Physical Design Exchange format)

� Back annotation: physical design -> synthesis� Delays (SDF)

� Design parasitics (capacitance & resistance) (optionally SPEF)

� Cluster information (PDEF)

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Physical Versus Logical

Hierarchy - 1

� The hierarchies used in physical design may be different than those used in synthesis

� Physical hierarchy represents relationship between subdesigns in physical space rather than functional space.

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Physical Versus Logical

Hierarchy - 2

� Example: Separation of logic and memory and clustering of logic

Top

mem control

subbsuba

mem control

Logical

Physical

mem1+ mem2

control1+ control2

ROM

ROM

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Physical Clusters

� Uses: As placement constraints - causes subdesigns that are not logically together to be physically together. Useful for effective use of area and also delay control

� To guide re-optimization - Can be used to return cluster sizes and locations to permit location based optimization in synthesis

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Synthesis/Physical Design

Strategies

� Overall Strategy

� Reoptimization Methodology Steps

� Reoptimization Strategies

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Overall Strategy

� Iterate between Synopsys tools and layout tools, performing successive design refinement to converge on a stable solution. The final design:

� Meets target performance requirements

� Implements easily as physical chip

� No simple set of optimization guidelines due to unique design requirements

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Reoptimization

Methodology Steps - 1

� Read prelayout or previous design database

� Back-annotate all available physical design information

� Verify back-annotation

� Analyze the design to determine problems

� Optionally characterize subdesign if subdesign is to be reoptimized

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Reoptimization

Methodology Steps - 2

� Apply appropriate reoptimization tool

� Analyze the design to verify that reoptimization has worked

� Write the new design database

� Write the files for forward-annotation to physical design

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Reoptimizing and Controlling

Reoptimization - 1

� Incremental design improvement on individual module or entire chip

� Similar to compile command

� FPM works on worst case violator, i. e., the path with the worst negative slack

� To optimize more than one critical path use compile_default_critical range variable

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Reoptimizing and Controlling

Reoptimization - 2� Type of reoptimization based on data

availabilityPDEF

v2.0

SDF set_load Reop

Performed

Recommended?

Yes Yes Yes Loc-based

Reop

Strongly

Yes Yes Non-loc-based

Reop

Yes

Yes Limited Non-

loc-based

Reop

No

Yes Limited Non-

loc-based

Reop

No

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Reoptimizing and Controlling

Reoptimization - 3

� Options for reoptimize design - default: -map_effort medium

� -map_effort, -sizing, -pin_swap,

-buffer_insertion, -buffer_removal,

-no_design_rule or -only_design_rule,

-ignore_footprint, -ignore_cell_area,

-reorder_scan_chains, -area_recovery

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Reoptimizing and Controlling

Reoptimization - 4

� Strategies for ReoptimizationWithin: Use:

1% of timing goals -sizing; optionally with-pin_swap

1% to 5% of timing

goals

-map_effort low

5% to 10% of timinggoals

-map_effort medium

10% to 20% of timinggoals

-map_effort high -tolerance_to_change high

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Reoptimizing and Controlling

Reoptimization - 5

� Strategies for Reoptimization (continued)

� Floorplan Manager cannot fix large timing violations

� If not within 20% of timing goals, try custom wireload models and recompiling the RTL. Also, consider architectural and coding style changes.

� If -map_effort option not used, can employ it using individual transform specifications

� Critical path resynthesis is enabled by

-map_effort high

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Synopsys Physical Compiler

� Representative of deep submicron synthesis tools which integrate placement in order to consider wiring delays during synthesis.

� Integrates the following design processes:

� Synthesis

� Placement

� Static timing analysis

� Synthesizes and places logic and estimates routing length to obtain timing closure in a single pass

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Design Flow Using Physical

Compiler - 1Figure 1-3 PSYN: Design flow using Physical

Compiler (see next slide)

1. Synthesize an initial netlist and obtain basic constraints using PC or DC and, optionally, Design Budgeting

2. Generate a floorplan for the design and convert to an IEEE PDEF (Physical Design Exchange Format) file. Also can optionally extract net parasitics and SDF (Standard Delay Format) delay information.

� PDEF includes cluster size, cluster location, port locations, macro locations, and underlying site array

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Design Flow Using

Physical Compiler - 2

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Design Flow Using Physical

Compiler - 3

3. If necessary, run Design Budgeting on each cluster (using the net parasitics and SDF delay information) to get updated budgets for the clusters.

4. Annotate the PDEF to the design database file.

5. Run PC on each block

6. Report timing for each block

7. Report timing for the chip, optionally running Prime Time.

8. Provide placement information for detailed routing

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Fundamental Hierarchy

Relationship - 1

� The physical “clusters” in the floorplan and the modules instantiated in the top level of the logical hierarchy must correspond. Their ports must match.

� Example – See Figure 2-1 Logic Modules and Physical Clusters (see next slide)

� PC will do synthesis and placement of each top level module/physical cluster

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Fundamental Hierarchy

Relationship - 2

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PC Placement Modes� Two Distinct Placement Modes

� Timing Driven Mode – Attempts to place cells so that critical path nets are short. Driven by net timing slack.

� Congestion Mode – Spreads out cell placement while attempting to maintain timing. Attempts to avoid “hot spots” which are routing regions that are highly congested and may prevent routes or cause routes to be circuitous.

� Combined Mode – Attempts to balance timing control with congestion reduction.

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Comparison to Prior

Methodology

� Design process starts with both synthesis and floorplanning

� Placement is replace by cluster resynthesis and placement� Provides placement-based timing information to the

synthesis process

� This timing information can be used as the synthesis/placement process progresses

� If the timing estimates and placements are done well, no iterations of design involving routing necessary