Lecture2 IC Basics 2up

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    EE141

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    EECS141 1Lecture #2

    EE141EE141--Fall 2010Fall 2010

    Digital IntegratedDigital IntegratedCircuitsCircuits

    Lecture 2Lecture 2

    Integrated Circuit Basics:Integrated Circuit Basics:

    Manufacturing and CostManufacturing and Cost

    EE141

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    EECS141 2Lecture #2

    Administrative StuffAdministrative Stuff

    Discussions start this Friday

    Labs start next week

    Homework #1 is due this Thursday

    Everyone should have an EECSinstructional account

    Use cory, quasar, pulsar

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    EECS141 3Lecture #2

    HSPICE SyntaxHSPICE SyntaxSimple CMOS inverter

    .include '/home/ff/ee141/MODELS/gpdk090_mos.sp TT_s1v

    * netlistVdd vdd 0 1.2

    VIN in 0 PULSE 0 1.2 200ps 100ps 100ps 2ns 4nsM0 out in vdd vdd gpdk090_pmos1V L=100e-9 W=120e-9M1 out in gnd gnd gpdk090_nmos1V L=100e-9 W=120e-9R1 in gnd 10KR2 out vdd 100K

    * extra control information.options post=2 nomod

    * analysis.op.TRAN .01ns 3ns

    .DC VIN 0 1.2 .001

    .END

    EE141

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    EECS141 4Lecture #2

    Last LectureLast Lecture

    Last lecture

    Introduction, Moores law, future of ICs

    Todays lecture

    Introduce basics of integrated circuitmanufacturing and cost

    Reading: Ch 2.1, 2.2

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    EE141

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    EECS141 5Lecture #2

    CMOSCMOS

    ManufacturingManufacturing

    ProcessProcess

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    EECS141 6Lecture #2

    The MOS TransistorThe MOS TransistorPolysilicon

    Aluminum

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    EECS141 7Lecture #2

    The Manufacturing ProcessThe Manufacturing Process

    http://bwrc.eecs.berkeley.edu/IcBook

    For a complete walk-through of the process (64 steps), check the

    Book web-page

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    EECS141 8Lecture #2

    oxidation

    opticalmask

    processstep

    photoresist coatingphotoresistremoval (ashing)

    spin, rinse, dryacid etch

    photoresist

    stepper exposure

    development

    Typical operations in a single

    photolithographic cycle (from [Fullman]).

    PhotoPhoto--Lithographic ProcessLithographic Process

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    EECS141 9Lecture #2

    Patterning of SiOPatterning of SiO22

    Si-substrate

    Si-substrate Si-substrate

    (a) Silicon base material

    (b) After oxidation and depositionof negative photoresist

    (c) Stepper exposure

    Photoresist

    SiO2

    UV-light

    Patternedoptical mask

    Exposed resist

    SiO2

    Si-substrate

    Si-substrate

    Si-substrate

    SiO2

    SiO2

    (d) After development and etching of resist,chemical or plasma etch of SiO

    2

    (e) After etching

    (f) Final result after removal of resist

    Hardened resist

    Hardened resist

    Chemical or plasma

    etch

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    EECS141 10Lecture #2

    Advanced MetallizationAdvanced Metallization

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    EECS141 11Lecture #2

    A Modern CMOS ProcessA Modern CMOS Process

    p-well n-well

    p+

    p-epi

    SiO2

    AlCu

    poly

    n+

    SiO2

    p+

    gate-oxide

    Tungsten

    TiSi2

    DualDual--Well ShallowWell Shallow--TrenchTrench--Isolated CMOS ProcessIsolated CMOS Process

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    EECS141 12Lecture #2

    Transistor LayoutTransistor Layout

    p-well SiO2

    poly

    SiO2

    n+

    Cross-Sectional View

    Layout View

    poly

    p-well

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    EECS141 13Lecture #2

    CostCost

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    EECS141 14Lecture #2

    Cost of Integrated CircuitsCost of Integrated Circuits

    NRE (non-recurrent engineering) costs - fixed Independent of volume (i.e., number of units

    made/sold)

    Examples: design time and effort, maskgeneration, equipment, etc.

    Recurrent costs - variable

    proportional to volume

    Examples: silicon processing, packaging, test

    Most of these proportional to chip area

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    EECS141 15Lecture #2

    NRE Cost is IncreasingNRE Cost is Increasing

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    EECS141 16Lecture #2

    Total CostTotal CostCost per IC

    Variable cost

    volume

    costfixedICpercostvariableICpercost +=

    yieldtestfinal

    packagingofcosttestdieofcostdieofcostcostvariable

    ++=

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    EECS141 17Lecture #2

    Die CostDie Cost

    Single die

    Wafer

    yielddie*waferperdies

    waferofcostdieofcost =

    From: http://www.amd.com

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    EECS141 18Lecture #2

    Wafer sizeWafer size

    From: http://www.sandpile.org

    8 (200mm) 12 (300mm) 12 (300mm)

    90nm CMOS 90nm CMOS 65nm CMOS

    AMD Athlon

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    EECS141 19Lecture #2

    YieldYield

    %100waferperchipsofnumberTotal

    waferperchipsgoodofNo.=Y

    yieldDiewaferperDies

    costWafercostDie

    =

    ( )

    areadie2

    diameterwafer

    areadie

    diameter/2waferwaferperDies

    2

    =

    EE141

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    EECS141 20Lecture #2

    DefectsDefects

    defects per unit area die areadie yield 1 ,

    = +

    where is approximately 3

    ( )( )4

    -1 -3

    1die cost die area

    die/wafer die area yield die area

    Yield = 1/4 Yield = 19/24

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    EECS141 21Lecture #2

    Cost per TransistorCost per Transistor

    0.00000010.0000001

    0.0000010.000001

    0.000010.00001

    0.00010.0001

    0.0010.001

    0.010.01

    0.10.111

    19821982 19851985 19881988 19911991 19941994 19971997 20002000 20032003 20062006 20092009 20122012

    cost:cost:--perper--transistortransistor

    Fabrication cost per transistor

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    EECS141 22Lecture #2

    Next LectureNext Lecture

    CMOS transistors as switches

    How to build an inverter

    Design metrics