Lecture5 Memory 2up

8/3/2019 Lecture5 Memory 2up

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EECS141 1Lecture #5

EE141EE141--Fall 2010Fall 2010

Digital IntegratedDigital IntegratedCircuitsCircuits

Lecture 5Lecture 5

Overview of SemiconductorOverview of Semiconductor

MemoryMemory

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EECS141 2Lecture #5

AnnouncementsAnnouncements Please use the news group to ask questions

Dont need a new program: tryhttp://groups.google.com

For additional questions, send emails toee141@cory

Reaches entire teaching staff

Homework #2 due today

Homework #3 due next Thursday Labs start tomorrow


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EECS141 3Lecture #5

Class MaterialClass Material

Last lecture

Detailed Switch Model

CMOS Gates

Design Rules

Todays lecture

Overview of semiconductor memory

Reading (Chapter 12.1, 12.2.3, 12.3.1)

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EECS141 4Lecture #5

SemiconductorSemiconductor

MemoryMemory


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EECS141 5Lecture #5

Why Memory?Why Memory?

Intel 45nm Core 2

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EECS141 6Lecture #5

Semiconductor Memory ClassificationSemiconductor Memory Classification

Read-Write MemoryNon-Volatile

Read-Write

Memory

Read-Only Memory

EPROM

E2PROM

FLASH

Random

Access

Non-Random

Access

SRAM

DRAM

Mask-Programmed

Programmable (PROM)

FIFO

Shift Register

CAM

LIFO


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EECS141 7Lecture #5

Random Access Memories (RAM)Random Access Memories (RAM)

STATIC (SRAM)

DYNAMIC (DRAM)

Data stored as long as supply is applied

Larger (6 transistors/cell)

Fast

Differential (usually)

Periodic refresh required

Smaller (1-3 transistors/cell)

SlowerSingle Ended

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EECS141 8Lecture #5

Random Access Chip ArchitectureRandom Access Chip Architecture Conceptual: linear array

Each box holds some data

But this does not lead to a nice layout shape

Too long and skinny

Create a 2-D array

Decode Row and Column

address to get data


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EECS141 9Lecture #5

Basic Memory ArrayBasic Memory Array

CORE:- keep square within a 2:1 ratio- rows are word lines- columns are bit lines

DECODERS:- needed to reduce total numberof pins; N+M address lines for2N+M bits of storage

Ex: if N+M=20 220= 1Mb

MULTIPLEXING:- used to select one or more

columns for input or outputof data

- data in and out on columns

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EECS141 10Lecture #5

Basic Static Memory ElementBasic Static Memory Element

If D is high, D_b will be driven low

Which makes D stay high

Positive feedback


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Positive Feedback: BiPositive Feedback: Bi--StabilityStabilityVi1 Vo2

Vo2 = Vi 1

Vo1 = Vi 2

V

o

1

V

i

2

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V

o

1

V

i

2

5

V

o

1

Vi1

A

C

B

Vo2

Vi1 = Vo2

Vo1 Vi2

Vi2 = Vo1

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Writing into a CrossWriting into a Cross--Coupled PairCoupled Pair

Access transistor must be able to overpower the feedback


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Writing aWriting a11

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Memory CellMemory Cell

Complementary data values are written (read) from two sides


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SRAM ColumnSRAM Column

WL2

WL0

WL3

BL BL_B

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SRAM Array LayoutSRAM Array Layout


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65nm SRAM65nm SRAM

ST/Philips/Motorola

Access Transistor

Pull down Pull up

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DecodersDecoders

Word 0

Word 1

Word 2

Word N2 2

Word N2 1

Storagecell

M bits M bits

N

w or ds

S0

S1

S2

SN2 2

A 0

A 1

AK2 1

K = log2N

SN2 1

Word 0

Word 1

Word 2

Word N2 2

Word N2 1

Storagecell

S0

Input-Output(M bits)

Intuitive architecture for N x M memoryToo many select signals:

N words == N select signalsK = log2N

Decoder reduces the number of select signals

Input-Output(M bits)

De cod er


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Row DecodersRow Decoders

Collection of 2M complex logic gatesOrganized in regular and dense fashion

(N)AND Decoder

NOR Decoder

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Decoder Design ExampleDecoder Design Example

Look at decoder for 256x256 memoryblock (8KBytes)


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Problem SetupProblem Setup Goal: Build fastest, lowest possible power

decoder with static CMOS logic

What we know

Basically need 256 ANDgates, each one of themdrives one word line

N=8

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Possible AND8Possible AND8

Build 8-input NAND gate using 2-input gatesand inverters

Is this the best we can do?

Is this better than using fewer NAND4 gates?


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Possible DecoderPossible Decoder 256 8-input AND gates

Each built out oftree of NAND gatesand inverters

Need to drive a lotof capacitance (SRAMcells)

Whats the best way to do this?

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Next LectureNext Lecture

Buffer delay optimization

Documents

Lecture5 Memory 2up