LHCb Calorimeter Upgrade Meeting – 10th September 2012 – CERN

LHCb Calorimeter Upgrade Electronics:

ASIC solution statusE. Picatoste, D. Gascon

Universitat de Barcelona Institut de Ciències del Cosmos ICC-UB

2

FEB Prototype Tests:

10th September 2012 Calorimeter Upgrade Meeting

FEB

3

FEB Prototype Tests: Clock Tree

15th June 2012 Calorimeter Upgrade Meeting

WAVEFORM GENERATOR

USB

Clock 40MHz

Trigger

Signal

FPGA

PC with CAT sw

Clock 20MHz

out1 out2

Clock 10MHz

Clock 40MHz

ANALOG MEZZANINE

ADC out12 bit x 2 channel

ASICADC filter

4

ASIC Prototypes

Switched integrator

Track and Hold

MP2MP1

Q1

Re

Ib1 MN2

MP4MP3

MN1

Rf

Vee

Vcc

1 : K : mK : mK

Ib2

Ii

Io ∫

∫

I I

Current amplifier (mirrors)

TH

TH

AnalogueMultiplexer

Drv

ADC driver

First Prototype:ICECAL chipSiGe BiCMOS 0.35umAMS 2 mm2

Received: October 201012 chips

10th September 2012 Calorimeter Upgrade Meeting

Second Prototype: ICECAL2 chipSiGe BiCMOS 0.35umAMS 2 mm2

Received: October 201110 chips

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FEB Prototype Tests: Noise

15th June 2012 Calorimeter Upgrade Meeting

filter

• Optimize filter values for gain and noise

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FEB Prototype Tests: Noise

15th June 2012 Calorimeter Upgrade Meeting

• Noise measurements for one chip

With all setup Without cable No cable and 50Ohm

termination No chip

• Corrections: Gain Board noise

• Results compatible with previous measurements

Calibrations C/LSB (C)C/1LSB

expectedfactor

exp/cal Vo/LSB (V)  5,97109E-15 4,00E-15 1,49E+00 4,66E-04

Noise mean rms mean corr rms corr Chip Noisech2 3728 1,182 5565,053 1,764 1,597ch3 3784 1,136 5648,648 1,696 1,559ch2 CDS 0,7409 1,32 1,106 1,970 1,713ch3 CDS 0,4989 1,286 0,745 1,920 1,719ch2 no cable 3725 0,8218 5560,574 1,227 0,971ch3 no cable 3781 0,8422 5644,170 1,257 1,065ch2 no cable CDS 0,37 1,036 0,552 1,547 1,201ch3 no cable CDS 0,33 1,055 0,493 1,575 1,323ch2 terminated 3728 1,116 5565,053 1,666 1,488ch3 terminated 3785 1,104 5650,141 1,648 1,507

ch2 terminated CDS 0,6809 1,254 1,016 1,872 1,599ch3 terminated CDS 0,5969 1,314 0,891 1,962 1,766ch2 no chip 3758 0,5019      ch3 no chip 3759 0,4472      ch2 no chip CDS 0,2549 0,6525      ch3 no chip CDS 0,11 0,5725      

Gain correction

Extract board noise

7

FEB Prototype Tests: Linearity

15th June 2012 Calorimeter Upgrade Meeting

• Measurement of linearity seems OK Take into account the different gain

due to the filter• Reminder:

– Low voltage measurements present high relative errors

-5

-4

-3

-2

-1

0

1

2

3

4

5

0 0,5 1 1,5 2 2,5

Non

Lin

earit

y (%

)

Vout (V)

ASIC only setup

ASIC+FE setup

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FEB Prototype Tests: Plateau

15th June 2012 Calorimeter Upgrade Meeting

• Due to clock jitter, the signal at the output must be stable (<1%) for 4 ns.

• Input signal AWG generated similar to clipped.

• Method: Not possible to delay the 20MHz

clock with the present board Delay signal in 1ns increments Use LEMO cable

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DC-DC converters

15th June 2012 Calorimeter Upgrade Meeting

• Voltage source options: DC-DC converters Crate voltage source

• DC-DC converter requires noise measurements

• ASIC 1.65V needs very little current. Possible solutions: DC-DC converter Commercial LDO or voltage

reference Use ADC Vref with a buffer

COTS

DC-DC Output

voltage (V)

DC-DC Input

voltage (V)

Current per ch (A)

Total current (A)

3.3 5 (5-8) 0.1 3.2

ASIC

DC-DC Output

voltage (V)

DC-DC Input

voltage (V)

Current per ch (A)

Total current (A)

3.3 5 (5-8) 0.05 1.61.65 5 (5-8) 0.005 0.16

ADC

DC-DC Output

voltage (V)

DC-DC Input

voltage (V)

Current per ch (A)

Total current (A)

3.3 5 (5-8) 0.06 1.92

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• September Tests with soldered ASIC (no socket) DC-DC noise tests Tuneable blocks schematics

Input offset Zin Integrator RC

Block layout• October

Meeting Delay line (Joan Mauricio) I2C

Chip layout and integration• November

ASIC run

Plans

15th June 2012 Calorimeter Upgrade Meeting

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Back-up

15th June 2012 Calorimeter Upgrade Meeting

12

FEB Prototype Tests: Clock Tree

15th June 2012 Calorimeter Upgrade Meeting

Olivier Duarte / Thierry Caceres

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Measurements: Noise

15th June 2012 Calorimeter Upgrade Meeting

cabl

e+cl

ippi

ngN

o ca

ble

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Measurements: Linearity

15th June 2012 Calorimeter Upgrade Meeting

T/H linearity error (%)

Integrator linearity error (%)

V output (V)

1%

1.8 V

Second Prototype simulations show:•T/H linearity is lost at Vout~1.8V•Cause:

– Single ended limit to maximum output voltage of FDOA at the NMOS stage

•Possible solution:– Apply different offset to each pos/neg signal

to reduce overall signal excursion

• All chips and subchannels tested.

• Linearity seems OK• Reminder:

– Low voltage measurements present high relative errors

-5

-4

-3

-2

-1

0

1

2

3

4

5

0 0,5 1 1,5 2 2,5N

on L

inea

rity

(%)

Vout (V)

95,00

96,00

97,00

98,00

99,00

100,00

101,00

10 11 12 13 14 15 16 17 18 19 20 21 22

Sign

al/m

ax (%

)

Clock Delay (ns)

1dB

8dB

15dB

15

Plateau at the integrator output

• Due to clock jitter, the signal at the output must be stable (<1%) for 4 ns.• Input signal AWG generated similar to clipped.• Method:

– Delay clock signal in 1ns increments– Use LEMO cable

15th June 2012 Calorimeter Upgrade Meeting