LHCb Outer Tracker UpgradeAMC40 firmware

120 february 2013

Outline◦ OT architecture◦ Front end box architecture ◦ Actel TDC◦ Data GBT interface◦ Data format◦ Test Setup◦ AMC40/TP test setup

Antonio Pellegrino, Tom Sluijk, Wilco Vink,

One of the 432 Front Ends with 128 straw channels each

Outer Tracker

Antonio Pellegrino, Tom Sluijk, Wilco Vink 220 February 2013

LV,HV distr

Front-end box architecture

3Antonio Pellegrino, Tom Sluijk, Wilco Vink,20 february 2013

OT Front-end boxes

413 dec 2012

432 Front end boxes, each:◦ 1 master GBT / power board (replaces: GOL board)

TFC distribution 1 Master GBT (hardwired configured, except clocks) 1 SCA for monitoring (power, temperature, etc.)

◦ 4 Actel TDC boards (replaces: OTIS boards) 2 data transmitter GBT’s 1 SCA (Actel TDC conf. GBT conf., monitoring)

◦ 8 ASDBLR boards (unchanged)Total:

◦ 3888 GBT’s◦ 432 TFC Master GBT’s (Bidir)◦ 3456 Data GBT’s

◦ 2160 SCA’s

Tom Sluijk, Wilco Vink, Antonio Pellegrino

Front-end box

5

◦ 1 GBT master/power board (replaces: GOL board) Versatile link transceiver, <-> Master GBT

TFC signals 1 SCA for monitoring (power, temperature, etc.) 8 Optical data transmitters

4 dual transmitters versatile link OR 12-way optical transmitter, based on KK Ghan’s vcsel driver (8+4 spare)

Power supplies based on CERN SM01C DC/DC conv.◦ 4 Actel TDC boards (replaces: OTIS boards)

2 data transmitter GBT’s Wide bus format data transmitters One used for clocks, BxClk TpClk, TFC,clk Spare clocks for TDC

1 SCA Actel re-programming via JTAG GBT configuration 4 Threshold DAC Temperature monitoring Soft reset Actel

1 Actel Pro-asic A3PE1500 32 channel, 5-bits TDC Zero suppression

◦ 8 ASDBLR boards (unchanged)Antonio Pellegrino, Tom Sluijk, Wilco Vink,20 february 2013

Actel TDC

6

Pro-Asic A3PE1500 (4 FPGA’s/FE-box) 32 channel 5 bits TDC

◦ Based on 4 320 MHz clocks(2 edges and 90phase shifted)◦ fixed placement (3 variants: top, right, bottom)

Zero suppression Two wide-bus 28bits@160MHz GBT outputs

Antonio Pellegrino, Tom Sluijk, Wilco Vink,20 february 2013

Two options uses identical PCB, different Actel firmware◦8 Data GBT’s per FE-box

One ZS output bus per 16 channels No bandwidth limitations NZS full bandwidth readout capable

◦4 data GBT’s per FE-box One ZS output bus per 32 channels Bandwidth limit, lower cost, lower luminosity

◦Wide-bus GBT format 28b@160MHz

Data GBT interface

7Antonio Pellegrino, Tom Sluijk, Wilco Vink,20 february 2013

Two 16 ch. TDC in one FPGA Dual GBT’s

8

16 channel

TDC

Zero-supp16

stages

Readout GBT1Fifo

Actel FPGA

16 channel

TDC

Zero-supp16

stagesFifo Readou

t GBT2

Data Format (9 channels hit):

Padded ‘0’

8 bits Status4 bits BX cnt16 bits Hit pattern channel (0-15)027

5 bits Data5 bits Data5 bits Data5 bits Data5 bits Data

Padded ‘0’ 8 bits Status4 bits BX cnt16 bits Hit pattern channel (16-31)

5 bits Data5 bits Data5 bits Data5 bits Data

GBT2

GBT1

Max 4 words when all channels are hit

Max 4 words when all channels are hit

Antonio Pellegrino, Tom Sluijk, Wilco Vink,20 february 2013

32 channel TDC with single GBT

9

32 channel

TDC

Zero-supp32

stages

Readout GBTFifo

Actel FPGA

Data Format (9 channels hit):

8 bits Status4 bits BX cnt16 bits Hit pattern channel (0-15)16 bits Hit pattern channel(16-31)Data

5 bits Data5 bits Data 5 bits5 bits Data5 bits Data5 bits DatPadded ‘0’ s

027

5 bits Data5 bits Data5 bits Data

Max 8 words when all channels are hit

Antonio Pellegrino, Tom Sluijk, Wilco Vink,

GBT

20 february 2013

OTTOv2 Test Setup

10

StratixIV 230 evaluation board Dummy GBT, based on code Sophie Baron

Not yet implemented Small TFC Data buffer (512MB DDR3) I2C over Ethernet, dummy ECS/SCA Interfaces through 2 Wide bus buses with OTTOv2

OT TDC to Optical: OTTOv2 Prototype board with combined TDC board (OTIS) and Master GBT

board (GOL) Actel 32 channel TDC Snap 12 optical receiver/transmitter Versatile link:

Dual transmitter (data GBT) Bi-directional (master GBT)

SM01C radiation hard DC/DC power converters SCA Mezzanine (SCA pin-out not known) Threshold DAC

Antonio Pellegrino, Tom Sluijk, Wilco Vink,20 february 2013

Test setup

11Antonio Pellegrino, Tom Sluijk, Wilco Vink,20 february 2013

Test Setup

12

ASDBLRleft

ASDBLRright

Actel TDC SCASnap12 RxSnap12 Tx

Vers.Link

Power

Altera Dummy GBT slave Altera Dummy GBT master

1GbEth1GbEth

Antonio Pellegrino, Tom Sluijk, Wilco Vink,20 february 2013

AMC40/TP test setup overview

13Antonio Pellegrino, Tom Sluijk, Wilco Vink,20 february 2013

OTTOv2 with master/slave StratixIV◦ Data GBT emulated◦ Master GBT (not implemented)

TFC signals ECS via E-Link to SCA

Code available ??◦ Test setup as 1/4 Front end box◦ Needs GBT wide-bus FPGA code

AMC40/TP used for mini-DAQ and TFC/ECS◦ Needs AMC40/TP firmware

TFC/ECS DAQ

Mini-DAQ with AMC40/TP

14Antonio Pellegrino, Tom Sluijk, Wilco Vink,20 february 2013

Firmware “requirements” for first tests with OTTOv2 proto setup, First thoughts:

Dual data GBT input “data grabber”◦ Receives two GBT’s wide-bus data streams◦ Packet builder, MEP based on two links ???

Scalable, start with small MEP builder ???◦ DAQ->data-storage

Sends data through “standard” output to test DAQ (= 10GbE host PC) TFC/ECS

◦ Control of master GBT(dummy in StratixIV) Is this done before?

◦ Used as an TFC master TFC (PVSS <-> CCPC <-> GBT <-> SCA <-> OTTO) PC control software available? , start with command line CCPC ??

◦ Slow control ECS ECS (PVSS <-> CCPC <-> GBT <-> SCA <-> OTTO) PC control software available? , start with command line CCPC ??

AMC40/TP mini-DAQ

Antonio Pellegrino, Tom Sluijk, Wilco Vink 1520 February 2013