JORDAN READ jpread@live.com Hardware Engineer 650.799.4266 Active TS/SCI Clearance with Full-Scope Polygraph

Summary Engineering professional with a diverse background in high-speed digital and hardware design:

2+ years engineering experience in hardware and software development

Performed multiple large system-level integrations

Developing and implementing circuit to unit level components

Experience with high-speed circuit design, high-speed signal analysis

Responsible for end-to-end product development

Ability and experience with providing mentoring and training to interns and new hires

Create and deliver presentations to peers, senior staff and customers

Tools: VHDL, C, Bash, ISE, DxDesigner, AutoCAD, BitAlyzers, Pattern Generators, VNAs, O-Scopes, Excel, PowerPoint, Word,

Project, Google Docs.

Soft Skills: Strong ability in identifying existing obstacles and implementing improved methods, excellent written/verbal

communication skills, ability to actively engage and positively affect team members and customers, enthusiasm and drive to

consistently seek, deliver and update high quality technology solutions.

Professional Experience

Member of Technical Staff 1 – Circuit Design Northrop Grumman Corporation June 2015 - Present Responsible for end-to-end product development including design, testing, integration and delivery. Spearheaded a new foreign assignment program involving extensive evaluation of deployed antenna systems, recommending improvements, developing new solutions and implementing site upgrades. Led the re-design effort for two unit-level ground test system drawers from discrete components to an FPGA based design. Generate high-speed schematics (DxDesigner, IODesigner) and supporting documentation throughout process such as specifications, top-level architectures, fab drawings, requirements, ATPs, etc. Delivered complex VHDL updates five weeks ahead of schedule. The program resulted in a 43% lower cost per drawer, 3x higher reliability and a 70% reduction in average time to repair. Mentored two interns and three new hires, ensuring that they would be productive and successful in a short amount of time through structured company training. Intern Northrop Grumman Corporation June 2014 - June 2015 Generated high-speed schematics (DxDesigner, IODesigner) and supporting documentation throughout process such as specifications, top-level architectures, fab drawings, and requirements.

R&D Intern/FPGA Specialist Avinger Inc. July 2013 - Sept. 2013 Designed a high-speed circuit board that functioned as an FPGA/ADC/DSP bridge with external breakouts. Performed testing and troubleshooting on high-speed board. Supported the FPGA logic design for a new OCT system. Performed OCT data analysis and manipulation (MATLAB).

EDUCATION California Polytechnic State University San Luis Obispo, CA B.S. Electrical Engineering June 2015

Dale Carnegie Course March 2016 CompTIA Security+ March 2017