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Logic Design I (17.341)
Fall 2011
Lecture Outline
Class # 10
November 21, 2011
Dohn Bowden
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Today’s Lecture
• Administrative
• Main Logic Topic
• Homework
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CourseAdmin
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Administrative
• Admin for tonight …
– Syllabus Review
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Syllabus
• Syllabus
– Lecture changes … see syllabus
– Lab due dates have been modified as follows …• Lab #1 Due next week … 11/28/11• Lab #2 Due 12/12/11• Lab #3 Deleted• Lab #4 Deleted
– For planning purposes … Exam #3 is on 12/05/11 … in two weeks!
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Syllabus ReviewWeek Date Topics Chapter Lab Report Due
1 09/12/11 Introduction to digital systems and number systems 1
2 09/19/11 Binary Codes and Boolean Algebra 2
3 09/26/11 Boolean Algebra (continued) 3
4 10/03/11 Examination 1
X 10/10/11 No Class - Holiday
5 10/17/11 Application of Boolean Algebra 4
6 10/24/11 Karnaugh Maps and 5
7 10/31/11 Multi-Level Gate Circuits and Lab lecture 7
8 11/07/11 Examination 2
9 11/14/11 Combinational Circuit Design and Simulation Using Gates
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10 11/21/11 Multiplexers, Decoders. Encoder, and start PLD 9
11 11/28/11 PLD and Introduction to VHDL 10 1
12 12/05/11 Examination 3
13 12/12/11 Continue Intro to VHDL and Final Review 2
14 12/19/11 Final Exam
Exam #2
• Take home exam … I have not finished grading them …
– Will have them back next week
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Questions?
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Chapter 9 …
MULTIPLEXERS, DECODERS, AND PROGRAMMABLE LOGIC
DEVICES
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Objectives
Objectives
• Introduction• Multiplexers• Three-State Buffers• Decoders and Encoders• Read-Only Memories• Programmable Logic Devices … will start tonight• Complex Programmable Logic Devices … next week• Field Programmable Gate Arrays … next week
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Introduction
Introduction
• Thus far we have been concerned with basic principles of logic design
– Used gates as our basic building blocks
• Now we introduce the use of more complex integrated circuits ( ICs) in logic design …
– Multiplexers … decoders … encoders … and three-state buffers
• Read-Only Memories (ROMs) are described and used to implement multiple-output combinational logic circuits
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Introduction
• Will use the following in combinational logic design ...
– Programmable Logic Devices ( PLDs) … including …
• Programmable Logic Arrays ( PLAs)
• Programmable Array Logic devices ( PALs)
• Complex Programmable Logic Devices ( CPLDs)
• Field- Programmable Gate Arrays ( FPGAs)
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Multiplexers
Multiplexers
• A multiplexer has …
– A group of data inputs … and …
– A group of control inputs
• Used to select one of the data inputs and connect it to the output terminal
• A multiplexer … AKA … MUX …
– Acts like a switch that selects one input
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2-to-1 Multiplexer and Switch Analog
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Z = A′I0 + AI1
Data Inputs
Data Controls
Multiplexers
• 4 to 1 MUX needs 2 control inputs to select one data input …
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Multiplexers
• 8 to 1 MUX needs 3 control inputs to select one data input …
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Multiplexers
• 8 to 1 MUX output equation …
Z = A′B′C′I0 + A′B′CI1 + A′BC′I2 + A′BCI3 + AB′C′I4 + AB′CI5 + ABC′I6 + ABCI7
Values for A ... B … and C …
are a binary count!
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Multiplexers
• Internal Logic Diagram for 8-to-1 MUX …
Z = A′B′C′I0 + A′B′CI1 + A′BC′I2 + A′BCI3 + AB′C′I4 + AB′CI5 + ABC′I6 + ABCI7
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Multiplexers
• Multiplexers are frequently used in digital system design to select the data which is to be processed or stored
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Multiplexers
• The figure below is a … Quad Multiplexer used to select data
• A quadruple 2- to- 1 MUX is used to select …
– One … of … two 4-bit data words … by the value of Control Variable A
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Multiplexers
• If the control is … A = 0 …
• The values of x0 … x1 … x2 … and … x3 …
– Will appear at the z0 … z1 … z2 … and … z3 outputs
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Multiplexers
• If the control is … A = 1 …
• The values of y0 … y1 … y2 … and … y3 …
– Will appear at the at the outputs
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Multiplexers
• Several logic signals that perform a common function may be grouped together to form a bus
– Example … the sum outputs of a 4- bit binary adder can be grouped together to form a 4- bit bus
• Instead of drawing the individual wires that make up a bus …
– We represent a bus by a single heavy line
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Quad Multiplexer with Bus Inputs and Output
• The quad MUX … is redrawn … using …
– Bus inputs X and Y … and … bus output Z• The X bus represents the four signals x0 … x1 … x2 … and …
x3 …and … similarly for the Y and Z buses (4 signals)
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Three-State Buffers
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Buffers
Buffers
• A gate output can only be connected to a limited number of other device inputs with-out degrading the performance of a digital system
• A buffer may be used to increase the driving capability of a gate output
• Buffers are non-inverting …
– Logic value in … is the same as the logic value out
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Buffer
• Gate Circuit with Added Buffer …
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F = C
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Three-State Buffers
Three-State Buffers
• A logic circuit will not operate correctly if the outputs of two or more gates or other logic devices are directly connected to each other
• Example … if one gate has a 0 output (a low voltage) … and … another has a 1 output (a high voltage) …
– When the gate outputs are connected together the resulting output voltage may be some intermediate value that does not clearly represent either a 0 or a 1
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Three-State Buffers
• Use of three-state logic permits the outputs of two or more gates or other logic devices to be connected together
• The following is a three-state buffer and its logical equivalent
– Three-state buffers are also called tri-state buffers
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Three-State Buffers
• When …– The enable input B is 1 … the output C equals A– When B is 0 … the output C acts like an open circuit
• Output C is disconnected from the buffer output so that no current can flow
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Three-State Buffers
• When …• The output C is disconnected from the buffer …
– It is a Hi- Z (high- impedance) state of the output because the circuit offers a very high resistance or impedance to the flow of current
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Three-State Buffers
• Four Kinds of Three-State Buffers and associated truth tables …
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Three-State Buffers
• The enable is not inverted … so … the buffer output is enabled when B=1
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Three-State Buffers
• The buffer output is inverted … C = A’
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Three-State Buffers
• Enable is inverted … therefore buffer is enabled when B = 0
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Three-State Buffers
• Data Selection Using … Three-State Buffers
– When B = 1 … select input C– When B = 0 … select input A
• Therefore … D = B’A + BC
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Three-State Buffers
• For the following configuration (Circuit with Two Three-State Buffers) …
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Three-State Buffers
• If one buffer is disabled (output = Z) … F = input of other buffer
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Three-State Buffers
• If both buffers are disabled (output = Z) … F = Z
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Three-State Buffers
• If both buffers are enabled … F = X
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S1
S2
Three-State Buffers
• F is determined from the below table for all combinations …
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S1
S2
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Multiple Source Selection
Multiple Source Selection
• A multiplexer may be used to select one of several sources to drive a device input
• As an example … if an adder input must come from four different sources …
– A 4-to-1 MUX may be used to select one of the four sources
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Multiple Source Selection
• Below is a three-state bus …
• 4-Bit Adder with Four Sources for One Operand
– It uses three-state buffers to select one of the sources
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Multiple Source Selection
– Each buffer symbol actually represents …
• Four three-state buffers that have a common enable signal
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Bi-DirectionalInput / Output Pin
Bi-Directional Input/Output Pin
• Integrated circuits are often designed using bi-directional pins for input and output
– A microcontroller is an example with bi-directional pins
• Bi-directional means … the same pin can be used as an input pin … and …
– As an output pin … but … not both at the same time
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Bi-Directional Input/Output Pin
• The circuit output is connected to the pin through a three-state buffer
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Bi-Directional Input/Output Pin
• When the buffer is enabled …
– The pin is driven with the output signal
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Bi-Directional Input/Output Pin
• When the buffer is disabled …
– An external source can drive the input pin
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Decoders and Encoders
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Decoders
Decoders
• The decoder is another commonly used type of integrated circuit
• The decoder generates …
– All of the minterms of the three input variables
• Exactly one of the output lines will be 1 for each combination of the values of the input variables
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Decoders
• Diagram for a 3-to-8 Line Decoder …
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Decoders
• Diagram and truth table for a 3-to-8 Line Decoder …
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Exactly one of the output lines will be 1 for each combination of the values of the input variables
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4-to-10 line decoder
Decoders
• Below is a logic diagram for a 4-to-10 line decoder …
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Decoders
• Block diagram for the 4-to-10 line decoder …
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A B C D 7442
Decoders
• Truth table for the 4-to-10 line decoder …
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A B C D 7442
Decoders
• This decoder has inverted outputs (indicated by the small circles) …
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A B C D 7442
Decoders
• For each combination of the values of the inputs … exactly one of the output lines will be 0 …
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A B C D 7442
Decoders
• When a binary-coded-decimal digit is used as an input to this decoder … one of the output lines will go low to indicate which of the 10 decimal digits is present …
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A B C D 7442
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Multiple-Output Decoder Circuits
Multiple-Output Decoder Circuits
• An n-input decoder generates all of the minterms of n variables
• An n-variable functions can be realized by ORing together selected minterm outputs from a decoder
• If the decoder outputs are inverted … then … NAND gates can be used to generate the functions
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Multiple-Output Decoder Circuits
• Example … Realize the following using the decoder below
f1(a, b, c, d) = m1 + m2 + m4 f2(a, b, c, d) = m4 + m7 + m9
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A B C D 7442
Multiple-Output Decoder Circuits
• Example … Realize the following using the decoder belowf1(a, b, c, d) = m1 + m2 + m4 f2(a, b, c, d) = m4 + m7 + m9
• Rewriting f1 and f2 … we have … f1 = (m1′m2′m4′)′ f2 = (m4′m7′m9′)′
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A B C D 7442
Multiple-Output Decoder Circuits
• Example … Realize the following using the decoder belowf1 = (m1′m2′m4′)′ f2 = (m4′m7′m9′)′
• f1 and f2 … can be generated using NAND gates
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A B C D 7442
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Encoders
Encoders
• An encoder performs the inverse function of a decoder
– If input yi is 1 and the other inputs are 0 … then … abc outputs represent a binary number equal to i
• For example … if y3 = 1 … then … abc = 011
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y0 y1 y2 y3 y4 y5 y6 y7 a b c d 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 X 1 0 0 0 0 0 0 0 0 1 1 X X 1 0 0 0 0 0 0 1 0 1 X X X 1 0 0 0 0 0 1 1 1 X X X X 1 0 0 0 1 0 0 1 X X X X X 1 0 0 1 0 1 1 X X X X X X 1 0 1 1 0 1 X X X X X X X 1 1 1 1 1
Encoders
• The truth table below using the following scheme …
– If more than one input is 1 …
• The highest numbered input determines the output
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y0 y1 y2 y3 y4 y5 y6 y7 a b c d 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 X 1 0 0 0 0 0 0 0 0 1 1 X X 1 0 0 0 0 0 0 1 0 1 X X X 1 0 0 0 0 0 1 1 1 X X X X 1 0 0 0 1 0 0 1 X X X X X 1 0 0 1 0 1 1 X X X X X X 1 0 1 1 0 1 X X X X X X X 1 1 1 1 1
Encoders
• An extra output … d … is 1 … if any … input is 1 … otherwise d is 0
– This signal is needed to distinguish the case of all 0 inputs from the case where only y0 is 1
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y0 y1 y2 y3 y4 y5 y6 y7 a b c d 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 X 1 0 0 0 0 0 0 0 0 1 1 X X 1 0 0 0 0 0 0 1 0 1 X X X 1 0 0 0 0 0 1 1 1 X X X X 1 0 0 0 1 0 0 1 X X X X X 1 0 0 1 0 1 1 X X X X X X 1 0 1 1 0 1 X X X X X X X 1 1 1 1 1
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Programmable Logic Devices (PLDs)
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Programmable Logic Devices ( PLDs)
• Thus far we have seen combinational circuits that were fixed …
– They were fabricated as integrated circuits … or …
– By connecting together integrated circuits
• Programmable logic devices (PLDs) are fabricated with …
– Structures that implement logic functions … and …
– Structures that are used to control connections or to store information specifying the actual logic functions implemented
– Which requires programming … a hardware procedure that determines which functions are implemented
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Programmable Logic Devices ( PLDs)
• Basic programmable logic devices …
– The read- only memory (ROM)
– The programmable logic array (PLA) …and …
– The programmable array logic (PAL) device
– Complex Programmable Logic Devices (CPLD)
– Field-Programmable Gate Arrays (FPGA)
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Programmable Logic Devices ( PLDs)
• Most of the PLDs are comprised of two arrays of gates …
– An AND gate array … and …
– An OR gate array
• PLDs differ in the placement of programmable connections in the AND - OR array
– As we shall see …
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Notations …
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Connections
• There are two types of connections between two perpendicular lines …
– Programmable … and …
– Non-programmable
• Also known as a hard-wired connection
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Non-programmable Connections
• Non-programmable connection …
– Is denoted by a dot at the intersection of the two perpendicular lines …
– The connection is permanent and cannot be removed
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Programmable Connections
• Programmable connection …
– A switching element is used to connect two lines …
• Which is shown by an “X” at the intersection of the two lines
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Programmable Connections
• Programmable connection …
– Are not connected if the “X” is absent
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Programmable Connections
• Fuses or transistors are used as switching elements
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Programming Technologies
• The oldest of the programming technologies include fuses and anti-fuses
• Fuses … which are initially CLOSED … are …
– Selectively blown out by a higher than normal voltage to established OPEN connections
• The pattern of OPEN and CLOSED fuses establishes the connections defining the logic
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Programming Technologies
• Anti-fuses … the opposite of fuses …
• They contain a material that is initially nonconducting (OPEN)
• Anti-fuses are selectively (CLOSED) by …
– Applying a higher- than- normal voltage to provide a pattern of OPEN and CLOSED anti-fuses to define the logic
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Transistor Switching
• Based on storing charge on a floating gate.
– Stored negative charge on the floating gate makes the transistor impossible to turn ON
– The absence of stored negative charge makes it possible for the transistor to turn ON if a HIGH is applied to its regular gate
• Since it is possible to add or remove the stored charge …
– These technologies can permit erasure and reprogramming
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Phase Splitter
• A Phase Splitter is used to generate …
– The TRUE form … and …
– The COMPLEMENTED form of an input
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Programmable Gates
• For an n-input programmable gate …
– Only one line is drawn and connected to the gate
– A gate can be disconnected by removing the ”X”
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Read-Only Memories(ROM)
Read-Only Memories
• A read-only memory (ROM) consists of …
– An array of semiconductor devices that are interconnected to store an array of binary data
• Once binary data is stored in the ROM … it can be read out whenever desired … but …
– The data that is stored cannot be changed under normal operating conditions
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Read-Only Memories
• Below is a ROM which has three input lines and four output lines along with it’s truth table
• The truth table relates the ROM inputs and outputs• For each combination of input values on the three input lines, the
corresponding pattern of 0’ s and 1’ s appears on the ROM output lines.
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Read-Only Memories
• For each combination of input values on the three input lines … the corresponding pattern of 0’ s and 1’ s appears on the ROM output
• If the combination ABC = 010 is applied to the input lines … the pattern F0F1F2F3 = 0111 appears on the output lines
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Read-Only Memories
• Each of the output patterns that is stored in the ROM is called a word
• Because the ROM has three input lines … we have 23 eight different combinations of input values– Each input combination serves as an address which can select
one of the eight words stored in the memory
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Read-Only Memories
• For the ROM below … there are four output lines … therefore …
– Each word is four bits long … and …
• The size of this ROM is 8 words x 4 bits
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Read-Only Memories
• The input lines serve as an address to select one of the 2n words
• When an input combination is applied to the ROM … the pattern of 0’ s and 1’ s … which is stored in the corresponding word in the memory … appears at the output lines
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Read-Only Memories
• Typical sizes for commercially available ROMs range from …
– 32 words x 4 bits … to …
– 512K words x 8 bits … or … larger
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Read-Only Memories
• Basic ROM structure …
InputsFixed
AND array(decoder)
ProgrammableOR array OutputsProgrammable
Connections
Read-Only Memories
• When a pattern of n 0’s and 1’s is applied to the decoder inputs …
– Exactly one of the 2n decoder outputs is 1
• The decoder output line selects one of the words in the memory array … and …
– The bit pattern stored in this word is transferred to the memory output lines
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Read-Only Memories
• The AND gate array is fixed and non-programmable …
InputsFixed
AND array(decoder)
ProgrammableOR array OutputsProgrammable
Connections
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Read-Only Memories
• The OR gate array is programmable …
InputsFixed
AND array(decoder)
ProgrammableOR array OutputsProgrammable
Connections
Read-Only Memories
• The n-inputs to the ROM are also the inputs to the AND array …
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Read-Only Memories
• There are 2n inputs connected to each OR gate in the OR array of a ROM … when it has not yet been programmed!
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2n 2n
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Read-Only Memories
• ROMs have a fixed AND array constructed as …
– A decoder … and …
– Programmable connections for the output OR gates
• This forms what appears to be a structure for implementing …
– Sum- Of- Minterm equations for the outputs
– It also can be thought of as implementing a truth table
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Read-Only Memories
• Implementing a truth table …
– Connections to OR gates for 1s … and …
– No connections to an OR gates for 0s
• The ROM can be viewed as a memory in which …
– The outputs provide words of binary data that are …
• Selected by the inputs applied to the decoder
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Read-Only Memories
• Since the AND array of a ROM is a decoder …
– All the standard products or minterms of a function are …
• Available at the AND array outputs … if …
– The AND array inputs are the variables of the function
– The function can be implemented by removing unnecessary inputs to an OR gate in the OR array
• Functions have to be in minterm list form
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Read-Only Memories
• Data can also be stored in ROMs …
• A read-only memory (ROM) is essentially a device in which permanent binary information is stored
• The information must be specified by the designer and is then embedded into the ROM to form the required interconnection or electronic device pattern
• Once the pattern is established … it stays within the ROM even when power is turned off and on again … that is …
• A ROM is nonvolatile
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Read-Only Memories
• There are n inputs and m outputs
• The n inputs provide the address for the memory
– Address range is from 0 to (2n – 1)
• The m outputs give the data bits of the stored word that is selected by the address
– Each word has m bits
• The number of words in a ROM device is determined from the fact that n address input lines can specify 2n words
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Read-Only Memories
• For a 32 x 8 ROM ...
– The ROM consists of 32 words of 8 bits each
– There are five input lines that form the binary numbers from 0 through 31 for the address
• The five inputs are decoded into 32 distinct outputs by means of a 5 to 32- line decoder
• Each output of the decoder represents a memory address
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Read-Only Memories
• The 32 outputs from the AND array are connected through programmable connections to each of the eight OR gates
• Each OR gate must be considered as having 32 inputs
• Each output of the decoder is connected by a programming technology to one of the inputs of each OR gate
– Each OR gate has 32 internal programmable connections …
– There are eight OR gates … therefore …
• The ROM contains 256 (32 x 8) programmable connections
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Read-Only Memories
• In general … a 2n x m ROM will have …
– An internal n - to - 2n line decoder
– m OR gates
– Each OR gate has 2n inputs …
• Which are connected through programmable connections to each of the outputs of the decoder
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Read-Only Memories
• Depending on the programming technology and approaches … read-only memories have different names …
– ROM … mask programmed
– PROM … fuse or anti-fuse programmed
– EPROM … erasable floating gate programmed
– EEPROM or E2PROM … electrically erasable floating gate programmed
– FLASH Memory … electrically erasable floating gate with multiple erasure and programming modes
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Read-Only Memories
• ROM programming typically uses programming software that isolates the user from the details
• A ROM stores computer programs …
– Binary code produced by compilers and assemblers
– Programmed by tools that accept input … such as truth tables, Boolean equations
– In the case of FLASH memory … it accept binary patterns
• For example … photographs taken by a digital camera.
• In all of these cases … the input is transformed to a pattern of OPEN and CLOSED connections to the OR gates
Read-Only Memories
• As previously seen … we have a ROM as shown below …
• One possible internal structure for the ROM below is on the next slide …
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Read-Only Memories
• One possible internal structure of the 8- word x 4- bit ROM
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Read-Only Memories
• The decoder generates the eight minterms of the three input vari-ables
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Read-Only Memories
• The memory array forms the four output functions by ORingtogether selected minterms
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Read-Only Memories
• A switching element is placed at the intersection of a word line and an output line if the corresponding minterm is to be included in the output function … otherwise …the switching element is omitted (or not connected)
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Read-Only Memories
• Otherwise …the switching element is omitted … or not connected
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Read-Only Memories
• If a switching element connects an output line to a word line which is 1 … the output line will be 1
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Read-Only Memories
• Otherwise … the pull-down resistors causes the output line to be 0
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Read-Only Memories
• So the switching elements which are connected in the memory array effectively form an OR gate for each of the output functions
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Read-Only Memories
• As an example … m0 … m1 … m4 … and … m6 are ORed together to form F0
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Read-Only Memories
• The equivalent OR gate is shown below
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Example …
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Read-Only Memories
• Example … Implement the following four functions using a ROM
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Read-Only Memories
• We will need … a 2n x m ROM …
– An internal n - to - 2n line decoder is required … which is …
3 inputs … A … B … and C
so the decoder is a 3 to 8 decoder
4 output (m) … f1, f2, f3, f4
so the ROM is 8 x 4
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Read-Only Memories
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Read-Only Memories
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Read-Only Memories
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Read-Only Memories
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Read-Only Memories
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Example …
Read-Only Memories
• Example … realize a code converter that converts a 4- bit binary number to a hexadecimal digit and outputs the 7- bit ASCII code
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Read-Only Memories
• Example … realize a code converter that converts a 4- bit binary number to a hexadecimal digit and outputs the 7- bit ASCII code
• Below is the truth table for the converter
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Read-Only Memories
• Example … note that A5 = A4 … and A6 = A4’ … therefore the ROM needs only five outputs as seen by the logic circuit
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Read-Only Memories
• Example … Because there are four address lines … the ROM size is 16 words by 5 bits
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Read-Only Memories
• Example … Columns A4A3A2A1A0 of the truth table are stored in the ROM
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Read-Only Memories
• Example … Columns A4A3A2A1A0 of the truth table are stored in the ROM … shown is an internal diagram of the ROM
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Lab
Lab
• Any issues with Lab #1 thus far???
• Lab Booklets were passed out
• Use Student Logic Number 301
• Lab report criteria is available on the class web page
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Next Week …
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Next Week Topics
• Chapter 9 … Finish PLD
• Chapter 10 … start VHDL
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Home Work
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Homework
1. Lab #1
2. Read Chapter 9 and chapter 10
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References
1. None
