Logic Family Introduction and overview

Logic Families Introduction & Overview

Dr. D. Ezhilarasi

Ref: www.csee.wvu.edu/digital/book/chapters/

Logic Family Definition A circuit configuration or approach used to

produce a type of digital integrated circuit.

Consequence: different logic functions, when fabricated in the form of an IC with the same approach, or in other words belonging to the same logic family, will have identical electrical characteristics.

the set of digital ICs belonging to the same logic family are electrically compatible with each other

2

Digital logic families

Digital integrated circuits are classified not only by their

complexity or logical operation, but also by the specific

circuit technology to which they belong.

A logic family is a collection of different integrated-

circuit chips that have similar input, output, and internal

circuit characteristics, but they perform different logic

functions (AND, OR, NOT, etc.).

The electronic components used in the construction of

the basic circuit are usually used as the name of the

technology. The following are the most popular:

Common Characteristics of the Same Logic Family

Supply voltage range, speed of response, power dissipation, input and output logic levels, current sourcing and sinking capability, fan-out, noise margin, etc.

Consequence: choosing digital ICs from the same logic family guarantees that these ICs are compatible with respect to each other and that the system as a whole performs the intended logic function.

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Transistor Size Scaling Performance improves as size is decreased: shorter switching time, lower power consumption.

2 orders of magnitude reduction in transistor size in 30 years.

Moores Law

In 1965, Gordon Moore predicted that the number of transistors that can be integrated on a die would double every 18 to 14 months

i.e., grow exponentially with time

Considered a visionary million transistor/chip barrier was crossed in the 1980s

2300 transistors, 1 MHz clock (Intel 4004/4040) - 1971

42 Million transistors, 2 GHz clock (Intel P4) - 2001

140 Million transistors, (HP PA-8500)

Implementing Logic Circuits There are several varieties of transistors the

building blocks of logic gates the most important are:

BJT (bipolar junction transistors) one of the first to be invented

FET (field effect transistors) especially Metal-Oxide Semiconductor types (MOSFETs)

MOSFETs are of two types: NMOS and PMOS

TTL and CMOS Connecting BJTs together gives rise to a family of logic gates

known as TTL

Connecting NMOS and PMOS transistors together gives rise to the CMOS family of logic gates

BJT MOSFET

(NMOS, PMOS)

TTL CMOS

transistor types

logic gate families

Types of Logic Family 1 The entire range of digital ICs is fabricated using

either bipolar devices or MOS devices or a combination of the two.

Bipolar families: Diode logic (DL). (obsolete)

Resistor transistor logic (RTL). (obsolete)

Diode transistor logic (DTL). (obsolete)

Transistor Transistor logic (TTL).

Emitter Coupled Logic (ECL), also known as Current Mode Logic(CML).

Integrated Injection logic (I2L). (obsolete)

9

Types of Logic Family 2

MOS families: PMOS family (using P-channel MOSFETs) The NMOS family (using N-channel

MOSFETs) The CMOS family (using both N- and P-

channel devices). The Bi-MOS logic family uses both bipolar

and MOS devices.

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Electrical Parameters And Interpretation Of Data Sheets Voltages and Currents

Noise Margin

Power Dissipation

Propagation Delay

Speed-Power Product

Fan-In, Fan-Out

Comparison of Logic Families

Interpretation of Data Sheets

Digital Systems: Principles and Applications, 11/e Ronald J. Tocci, Neal S. Widmer, Gregory L. Moss

IC nomenclature & terminology is fairly standardized.


A logic-circuit output is generally required to drive several logic inputs.

Sometimes all ICs are from the same logic family. But many systems have a mix of various logic families.

The fan-outloading factoris the maximum number of logic inputs an output can drive reliably.

A logic gate can supply a maximum output current IOH(max), in the high state or IOL(max), in the low state

A logic gate requires a maximum input current IIH(max), in the high state or IIL(max), in the low state

Ratio of output and input current decide how many logic gates can be driven by a logic gate

fan-out(high) = IOH(max) / IIH (max) fan-out(low) = IOL(max) / IIL(max) overall fan-out = fan-out(high) or fan-out(low) whichever is lower

A typical figure of fan-out is ten (10)

Gate Drive Capability: Fan-Out

Speed: Rise & Fall Times

Rise Time Time from 10% to 90% of signal, Low to High

Fall Time Time from 90% to 10% of signal, High to Low

rise time

10% 90% 90% 10%

fall time


A logic signal always experiences a delay going through a circuit.

The two propagation delay times are defined as:

Propagation

delays.


Every IC requires a certain amount of electrical power to operate.

Supplied by one or more power-supply voltages connected at VCC (TTL) or VDD (MOS devices).

For many ICs, current drawn from the supply varies depending on logic states of the circuits on the chip.


The amount of power an IC requires is determined by the current, ICC (or IDD) it draws from the supply.

Actual power is the product ICC x VCC (IDD x VDD ).

In some logic circuits, average

current is computed based

on the assumption that gate

outputs are LOW half the

time and HIGH half the time.


Digital IC Terminology Power Requirements

The amount of power an IC requires is determined by the current, ICC (or IDD) it draws from the supply.

Actual power is the product ICC x VCC (IDD x VDD ).

can be rewritten to calculate

average power dissipated:

Power Dissipation

Static I2R losses due to passive components, no input signal

Dynamic I2R losses due to charging and discharging capacitances through resistances,

due to input signal

Noise Stray electric/magnetic fields can induce voltages on the connecting

wires between logic circuits Called noise, these unwanted, spurious signals can sometimes cause

unpredictable operation.

Noise Margin

Manufacturers specify voltage limits to represent the logical 0 or 1.

These limits are not the same at the input and output sides. For example, a particular Gate A may output a voltage of 4.8V when it

is supposed to output a HIGH but, at its input side, it can take a voltage of 3V as HIGH.

In this way, if any noise should corrupt the signal, there is some margin for error.

Noise Margin

If noise in the circuit is high enough it can push a logic 0 up or drop a logic 1 down into the indeterminate or illegal region

The magnitude of the voltage required to reach this level is the noise margin

Noise margin for logic high is: NMH = VOHmin VIHmin

VOHmin

VIHmin

VILmax

VOLmax logic 0

logic 1

indeterminate

input voltage


Noise immunity refers to the circuits ability to tolerate noise without changes in output voltage.

A quantitative measure is called noise margin.

High-state noise margin: Low-state noise margin:

Noise Margin

Difference between the worst case output voltage of one stage and worst case input voltage of next stage

Greater the difference, the more unwanted signal that can be added without causing incorrect gate operation

NMhigh = VOHmin - VIHmin NMlow = VILmax - VOLmax

Given the following parameters, calculate the noise margin of 74LS series.

Parameter 74LS

VIH(min) 2V

VIL(max) 0.8V

VOH(min) 2.7V

VOL(max) 0.4V

Solution:

High Level Noise Margin, VNH = VOH (min) - VIH (min)=2.7V-2.0V=0.7V

Low Level Noise Margin, VNL = VIL (max) - VOL (max)=0.8V-0.4V=0.4V

Worked Example


8-1 Digital IC Terminology Current Sourcing/Sinking

Current-sourcing action. When the output of gate 1 is HIGH, it supplies

current IIH to the input of gate 2. Which acts essentially as a resistance to ground.

The output of gate 1 is acting as a source of current for the gate 2 input.


8-1 Digital IC Terminology Current Sourcing/Sinking

Current-sinking action. Input circuitry of gate 2 is represented as a resistance tied to

+VCC the positive terminal of a power supply.

When gate 1 output goes LOW, current will flow from the input circuit of gate 2 back through the output resistance of gate 1, to ground.

Circuit output that drives the input of gate 2 must be able to sink a current, IIL , coming from that input.

Speed (propagation delay) and power consumption are the two most important performance parameters of a digital IC.

A simple means for measuring and comparing the overall performance of an IC family is the speed-power product (the smaller, the better).

For example, an IC has an average propagation delay of 10 ns an average power dissipation of 5 mW the speed-power product = (10 ns) x (5 mW) = 50 picoJoules (pJ)

Speed-Power Product

Electrical Characteristics

TTL faster (some versions)

strong drive capability

rugged

CMOS lower power consumption

simpler to make

greater packing density

better noise immunity

Complex ICs contain many millions of transistors

If constructed entirely from TTL type gates would melt

A combination of technologies (families) may be used

CMOS has become most popular and has had greatest development

Typical acceptable voltage ranges for positive logic 1 and logic 0

are shown below

A logic gate with an input at a voltage level within the indeterminate range will produce an unpredictable output level.

Logic Level & Voltage Range

Logic 1

Logic 0

5.0V

0V

2.5V

Indeterminate

0.8V

TTL

Logic 1

Logic 0

5.0V

Indeterminate

0V

1.5V

CMOS

3.5V

Logic Family

RTL (Resistor- transistor Logic) Example

33

Diode Basics

Essentially diode logic with transistor amplification reduced power consumption faster than RTL

TTL

The evolution from DTL to TTL can be seen by observing the placement of p-n junctions. For example, the diode D2 from DTL can be replaced by a transistor whose collector is pulled up to the power supply; transistor Q2 in Figure 1. The p-n junction of D2 is replaced by the BE junction of Q2 and with the current gain of the transistor, the current going into the base of Q3 is greatly increased, increasing the fanout. The input diodes and D1 are replaced by the multi-emitter NPN transistor, Q1, in Fig. 1 and represented by the drawing in Figure 2. we will consider the input transistor, Q1, to act just like two diodes. The transistor Q2, however, will operate in all three regions. The treatment of the output voltages and currents will be treated the same as the DTL gate and Q3 will either be cutoff or saturated, corresponding to an output high and an output low, respectively

ANALYSIS WITH ONE OR MORE INPUTS LOW

With an input low, Q3 should be cutoff. We will assume Q2 is cutoff

and then check our assumption. If Q2 is cutoff, then there can be no

current coming out of the collector of Q1, hence its base-collector

junction can be modeled as an open circuit. The base-emitter

junction of Q1 will be conducting. The circuit with these models

substituted for the transistors is shown in Figure 3. Note the

similarity to the DTL circuit under the same conditions. The two

unused inputs are assumed to be high, and are thus, modeled as

open. From this case, we can see that VoH = 5 volts with no load,

and

IinL = -I1 = -(5-0.9)/4K = -1.025 mA

Figure 3. TTL circuit model with one input low.

We turn now to finding VInLmax. We will use the criterion that Vin will be considered as a low as long as Q3 is

kept cutoff. If the base voltage for Q3 can be raised to 0.5 Volts without turning it on, then there will be 0.5 mA

current in the 1KW resistor. This current can only come from Q2, which means it must be conducting. Even

assuming all this 0.5 mA comes through the collector of Q2, the voltage drop across the 1.4 KW resistor will

be 0.7 Volts, not enough to cause the transistor to saturate. Thus, the active model for Q2 is appropriate as

shown in Figure 4.

This is considerably more than is going into the base of Q2, therefore, the input BE junction of Q1 will also

still be conducting. The maximum voltage at the input is

VinLmax = 1.9 - 0.7 = 1.2 Volts

IK

mA150 19

40 775

. ..

Because this current is coming out of the collector of Q1, the base- collector

junction of Q1 is on, and is modeled as a diode in Figure 4.

The voltage at B1, the base of Q1, is

VB1 = 0.5 + 0.7 + 0.7 = 1.9 Volts

The current coming down through the 4 KW resistor, I1, is

mAI mAB 016.0315.0

15.0

2

Figure 4. TTL circuit model to determine

VinLmax.If we assume that =30, the base

current in Q2 is

IK

mA150 2 3

40 675

. ..

IK

mA250 10

142 857

. .

..

CALCULATIONS WITH INPUT HIGH

The circuit model for the TTL gate with all inputs high is shown in Figure 5. Both Q2 and Q3 are modeled as

saturated, an assumption that must be verified. With the inputs high, Q1 is modeled as two diodes with the B-E

diodes cutoff, and B-C diode conducting.

Figure 5. TTL gate circuit model with all inputs high. The voltage

at the base of Q1 is VB1 = 0.8 + 0.8 + 0.7 = 2.3 Volts.

The current down through the 4 KW resistor, I1 is

All this current goes into the base of Q2.

IB2 = 0.675 mA

If Q2 is saturated, voltage at its collector terminal is

VC2 = 0.8 + 0.2 = 1.0 Volts

And the collector current is IC2 =

Clearly, if = 30, IB2 > IC2 , and, therefore, Q2 is saturated.

The current coming out of the emitter of Q2 is the sum of the base and collector currents. Part of

this current will go down through the 1 KW resistor to ground and the rest will enter the base of Q3.

IB3 = IB2 + IC2 - I3 = 0.675 + 2.857 - 0.8 = 2.732 mA

The maximum collector current that Q3 can carry and still be in saturation is IB3 =81.96 mA,

assuming =30. The maximum current the gate can sink when the output is low IoLmax = ICsatmax - I4 = 81.96 - 1.2 = 80.76 mA

Now let's turn our attention back to the input and determine VinHmin and IinH . We will define the input

voltage to be high as long as no current goes out the input terminal. Thus, all we have to do is keep

the input voltage high enough so that the B-E p-n junction of Q1 does not turn on. Thus, VinHmin = 2.3 - 0.6 = 1.7 Volts

CALCULATION OF IinH

With the input voltage at a high, say 5 volts, the transistor Q1 will be operating in the reverse active mode.

The B-E junction is reverse biased, and the B-C junction is forward biased with a base current of 0.675 mA.

If there were significant curent gain, you would expect to see a large current going into the input. However,

the reverse is typically on the order of 0.02. Thus,

This current would add to the current going into the base of Q2, but is ignored

because it is quite small and because R is made as small as possible and this input

current is a maximum and cannot be counted on.

THE TOTEM POLE OUTPUT STAGE One of the problems with the TTL gate circuit we have been analyzing is that the pull-up resistor on the output transistor will prevent rapid charging of any wiring capacitance on the output. One way to improve the rise time is to reduce the resistance value as is often done, but this also increases the power dissipation when the output is low. If we look at the circuit, we observe that when the transistor is saturated, it presents a very low effective resistance to ground. The problem arises when the output is high and the pull-up resistor is too large. Ideally we would like to have a very low resistance pull-up when the output is high, but a very high pull-up resistance when the output is low. In this way, we could get quick charging and very low power dissipation. The totem-pole output stage for TTL, shown in Figure 6, does just that. This circuit operates just like the original circuit except that Q4 is on when the output is high and off when the output is low. We need to verify this operation.

OUTPUT LOW Figure 7 shows the TTL circuit with all inputs high and the output low. The models for the transistors are shown as before, except diode D and transistor Q4 are added and shown as cutoff. The analysis of this circuit proceeds exactly the same as before. The currents, I1, I2, I3, and IB3 are the same as before. With the diode and Q4 not conducting, IoLmax is now the same as IC4max , 81.96 mA. We only need to show that the diode D and transistor Q4 are indeed off. The voltage at the bottom of the diode is 0.2 Volts and the voltage at the base of Q4 equal to the voltage at the collector of Q2; VC2 = (0.2 + 0.8) = 1.0 Volts. Thus, the voltage across the B-E junction of Q4 plus the diode is 0.8 Volts. If one conducts, the other must also. To take both out of cutoff would require at least 0.5 + 0.6 = 1.1 Volts. Thus, both are off.

Figure 7. TTL gate with totem-pole output circuit model with inputs high

OUTPUT HIGH This condition occurs when one or more inputs are low. The circuit is shown in Figure 8 with the appropriate models used for the transistors and the diode. In this case, Q2 and Q3 are both cutoff while Q4 and the diode are conducting. We have to assume here that there is some load and that the output current is not zero.

The current coming out the output terminal

IS (=-Io ) is the sum of the currents coming down

through the base and the collector. Thus,

IS = IB4 + IB4

Because each TTL load represents 13 mA, if we

assume there are 10 loads, then IS = 130 mA. The

base current is

IA

AB4130

14 2

m

m.

where we have assumed a of 30. Then taking the

path down through the 1.4 KW resistor to the output.

the output voltage is

Vo = 5.0 - 4.2mA1.4K - 0.7 -0.7 = 3.6 Volts The voltage drop across the 1.4 KW resistor is neglegible. Of course as the current increases, the output voltage will drop further.

Figure 8. TTL totem-pole circuit model with output high.

Tri-State Logic

Both output transistors of totem-pole output are turned off

Usually used to bus multiple signals on the same wire

Gates not enabled present high-Z to bus and therefore do not interfere with other gates putting signals on the bus

Tri-State Logic

Tri-state logic includes a switch at the output

In the figure below, the three states are illustrated: a) Logic High output

b) Logic Low output

c) High impedance (Hi-Z) output

TTL Subfamilies

76

Various series of the TTL Logic family

TTL Series Prefix Example

Standard TTL 74 7486

High-speed TTL 74H 74H86

Low-power TTL 74L 74L86

Schottky TTL 74S 74S86

Low-power Schottky TTL 74LS 74LS86

Advanced Schottky TTL 74AS 74AS86

Advanced Low-power Schottky TTL 74ALS 74ALS86

CMOS Sub families

4000A

4000B, 4000UB,

54/74C, 54/74HC, 54/74HCT, 54/74AC and 54/74ACT(TTL pin compatible)

78

Various series of the CMOS Logic family

CMOS Series Prefix Example

Original CMOS 40 4009

Pin compatible with TTL 74C 74H04

High-speed and pin compatible with TTL 74HC 74HC04

High-speed and electrically compatible with TTL 74HCT 74HCT04

Very High-speed and pin compatible with TTL 74VHC 74VHC04Very High-speed and electrically compatible with TTL 74VHCT 74VHCT04

Advanced High-speed and pin compatible with TTL 74AHC 74AHC04

Advanced High-speed and electrically compatible with TTL 74AHCT 74AHCT04

Fast and electrically compatible with TTL 74FCT 74 FCT 04

Fast and electrically compatible with TTL with TTL VOH 74FCT-T 74 FCT04T

Example Logic Families

General comparison or three commonly available logic families.

the most important to understand

TTL - Example SN74LS00 Recommended operating conditions

Vcc supply voltage 5V 0.5 V

input voltages VIH = 2V VIL = 0.8V

Electrical Characteristics output voltage VOH = 2.7V

(worst case) VOL = 0.5V

max input currents IIH = 20A IIL = -0.4mA

propagation delay tpd = 15 nS

noise margins for a logic 0 = 0.3V for a logic 1 = 0.7V

Fan-out 20 TTL loads

5 Volt

0 Volt

0.8

0.5

2.0

2.7

Input

Range

for 1

Input

Range

for 0

Output

Range

for 0

Output

Range

for 1

Wired-AND

Open collector outputs connected together to a common pull-up resistor

Any collector can pull the signal line low

Logically an AND gate

SSI Devices

Each package contains a code identifying the package

N74LS00

Manufacturers Code

N = National Semiconductors

SN = Signetics

Specification

Family

L

LS

H

Member

00 = Quad 2 input NAND

02 = Quad 2 input Nor

04 = Hex Invertors

20 = Dual 4 Input NAND

Different Families Dont all Speak the Same Language

Sometimes Things Get Lost or Added in the Translation*

Different families arent always on speaking terms with one another

The World of TTL

Success Drives Proliferation

New families introduced based on Higher performance Lower power New features New signaling threshold

Spawned over 32 unique families!

1960 2003

Success Drives Proliferation

Products introduced in the 1960 are near the end of their life cycle

Decreasing supplier base Increasing prices Not recommended for new

designs

Products considered to be mature are about 2 decades into their life cycle

High-volume production Multiple suppliers Low prices

Newer products are only a few years into their life cycle

High performance High level of vendor and

supplier support Newest technologies Higher prices

Characteristics: TTL and MOS

TTL stands for Transistor-Transistor Logic uses BJTs

MOS stands for Metal Oxide Semiconductor uses FETs

MOS can be classified into three sub-families: PMOS (P-channel)

NMOS (N-channel)

CMOS (Complementary MOS, most common)

Remember:

AB Y O/P

+Vcc

Q1

Q2

Q3

Q4

4K 1.6K 130R1 R2

R3

R4

1K

I CQ1

D 3

D1 D2

A B ICQ1

Q1

Q2

Q3

Q4

Y O/P

0 0 + ON OFF OFF ON 1



1 1 OFF ON ON OFF 0

A standard TTL NAND gate circuit

Table explaining the operation of the

TTL NAND gate circuit

TTL Circuit Operation

Transistor-Transistor Logic Families

Transistor-Transistor Logic Families:

74L Low power

74H High speed

74S Schottky

74LS Low power Schottky

74AS Advanced Schottky

74ALS Advance Low power Schottky

+VDD

O/P

I/P

S

D

D

S

Q

Q

1

2

I / P Q1 Q2 O / P

0 O N O F F 1

1 O F F O N 0

Table explaining the operation of

the CMOS inverter circuit A CMOS inverter circuit

MOS Circuit Operation

CMOS Family Evolution

CMOS Logic Trend: Reduction of dynamic losses (cross-conduction, capacitive charge/discharge cycles) by decreasing supply voltages:

12V5V 3.3V 2.5V 1.8V 1.5V

Reduction of IC power dissipation is the key to: lower cost (packaging)

higher integration

improved reliability


vi

vo

Comparison Logic Families


speed power product = a constant

Documents

Logic Family Introduction and overview