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Low Capacitance, Low Charge Injection,±15 V/+12 V, 4:1 iCMOS Multiplexer
Data Sheet ADG1204
Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.Tel: 781.329.4700 ©2005–2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com
FEATURES 1.5 pF off source capacitance <1 pC charge injection 33 V supply range 120 Ω on resistance Fully specified at ±15 V, +12 V No VL supply required 3 V logic-compatible inputs Rail-to-rail operation 14-lead TSSOP and 12-lead LFCSP Typical power consumption < 0.03 μW
APPLICATIONS Automatic test equipment Data acquisition systems Battery-powered systems Sample-and-hold systems Audio signal routing Video signal routing Communication systems
FUNCTIONAL BLOCK DIAGRAM
ADG1204
S2
S1
D
S4
S3
ENA1A0
1 OF 4DECODER
0477
9-00
1
Figure 1.
GENERAL DESCRIPTION The ADG1204 is a complementary metal-oxide semiconductor (CMOS) analog multiplexer, comprising four single channels designed on an iCMOS (industrial CMOS) process. iCMOS® is a modular manufacturing process that combines high voltage CMOS and bipolar technologies. It enables the development of a wide range of high performance analog ICs capable of 33 V operation in a footprint that no previous generation of high voltage devices has been able to achieve. Unlike analog ICs using conventional CMOS processes, iCMOS components can tolerate high supply voltages while providing increased performance, dramatically lower power consumption, and reduced package size.
The ultralow capacitance and charge injection of this multiplexer makes it an ideal solution for data acquisition and sample-and-hold applications, where low glitch and fast settling are required. Fast switching speed coupled with high signal bandwidth makes the device suitable for video signal switching. iCMOS construction ensures ultralow power dissipation, making the device ideally suited for portable and battery-powered instruments.
The ADG1204 switches one of four inputs to a common output, D, as determined by the 3-bit binary address lines: A0, A1, and EN. Logic 0 on the EN pin disables the device. Each switch conducts equally well in both directions when on and has an input signal range that extends to the supplies. In the off condition, signal levels up to the supplies are blocked. All switches exhibit break-before-make switching action.
PRODUCT HIGHLIGHTS 1. 1.5 pF off capacitance (±15 V supply). 2. <1 pC charge injection. 3. 3 V logic-compatible digital inputs: VIH = 2.0 V, VIL = 0.8
V. 4. No VL logic power supply required. 5. Ultralow power dissipation: <0.03 μW. 6. 14-lead TSSOP and 12-lead, 3 mm × 3 mm LFCSP
packages.
ADG1204 Data Sheet
Rev. C | Page 2 of 16
TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3
Dual Supply ................................................................................... 3 Single Supply ................................................................................. 5
Absolute Maximum Ratings ............................................................ 7
ESD Caution...................................................................................7 Pin Configurations and Function Descriptions ............................8
Truth Table .....................................................................................8 Typical Performance Characteristics ..............................................9 Test Circuits ..................................................................................... 12 Terminology .................................................................................... 14 Outline Dimensions ....................................................................... 15
Ordering Guide .......................................................................... 15
REVISION HISTORY 3/16—Rev. B to Rev. C Changed LFCSP_VQ to LFCSP ................................... Throughout Changes to Figure 3 .......................................................................... 8 Updated Outline Dimensions ....................................................... 15 Changes to Ordering Guide .......................................................... 15 2/09—Rev. A to Rev. B Changes to Power Requirements, IDD, Digital Inputs = 5 V Parameter, Table 1 ............................................................................. 4 Changes to Power Requirements, IDD, Digital Inputs = 5 V Parameter, Table 2 ............................................................................. 6 Updated Outline Dimensions ....................................................... 15
7/06—Rev. 0 to Rev. A Updated Format .................................................................. Universal Changes to Table 1 ............................................................................. 3 Changes to Table 2 ............................................................................. 5 Changes to the Terminology Section ........................................... 14 7/05—Revision 0: Initial Version
Data Sheet ADG1204
Rev. C | Page 3 of 16
SPECIFICATIONS DUAL SUPPLY VDD = 15 V ± 10%, VSS = −15 V ± 10%, GND = 0 V, unless otherwise noted.
Table 1. Y Version1
Parameter 25°C −40°C to +85°C
−40°C to +125°C Unit Test Conditions/Comments
ANALOG SWITCH Analog Signal Range VDD to VSS V On Resistance (RON) 120 Ω typ VS = ±10 V, IS = −1 mA; see Figure 21
190 230 260 Ω max VDD = +13.5 V, VSS = −13.5 V On Resistance Match Between 3.5 Ω typ VS = ±10 V, IS = −1 mA
Channels (ΔRON) 6 10 12 Ω max On Resistance Flatness (RFLAT(ON)) 20 Ω typ VS = −5 V, 0 V, +5 V; IS = −1 mA
57 72 79 Ω max LEAKAGE CURRENTS VDD = +16.5 V, VSS = −16.5 V
Source Off Leakage, IS (OFF) ±0.02 nA typ VS = ±10 V, VD = ∓10 V; see Figure 22 ±0.1 ±0.6 ±1 nA max Drain Off Leakage, ID (OFF) ±0.02 nA typ VS = ±10 V, VD = ∓10 V; see Figure 22 ±0.1 ±0.6 ±1 nA max Channel On Leakage, ID, IS (ON) ±0.02 nA typ VS = VD = ±10 V; see Figure 23
±0.2 ±0.6 ±1 nA max DIGITAL INPUTS
Input High Voltage, VINH 2.0 V min Input Low Voltage, VINL 0.8 V max Input Current, IINL or INH 0.005 µA typ VIN = VINL or VINH ±0.1 µA max Digital Input Capacitance, CIN 2.5 pF typ
DYNAMIC CHARACTERISTICS2 Transition Time, tTRANS 120 ns typ RL = 300 Ω, CL = 35 pF
150 180 200 ns max VS = 10 V; see Figure 24 tON (EN) 70 ns typ RL = 300 Ω, CL = 35 pF
85 100 110 ns max VS = 10 V; see Figure 26 tOFF (EN) 90 ns typ RL = 300 Ω, CL = 35 pF
110 135 155 ns max VS = 10 V; see Figure 26 Break-Before-Make Time Delay, tD 25 ns typ RL = 300 Ω, CL = 35 pF 10 ns min VS1 = VS2 = 10 V; see Figure 25 Charge Injection −0.7 pC typ VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 27 Off Isolation 85 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 28 Channel-to-Channel Crosstalk 80 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 30 Total Harmonic Distortion + Noise 0.15 % typ RL = 10 kΩ, 5 V rms, f = 20 Hz to 20 kHz;
see Figure 31 Bandwidth −3 dB 800 MHz typ RL = 50 Ω, CL = 5 pF; see Figure 29 CS (OFF) 1.2 pF typ f = 1 MHz, VS = 0 V 1.5 pF max f = 1 MHz, VS = 0 V CD (OFF) 3.6 pF typ f = 1 MHz, VS = 0 V 4.2 pF max f = 1 MHz, VS = 0 V CD, CS (ON) 5.5 pF typ f = 1 MHz, VS = 0 V 6.5 pF max f = 1 MHz, VS = 0 V
ADG1204 Data Sheet
Rev. C | Page 4 of 16
Y Version1
Parameter 25°C −40°C to +85°C
−40°C to +125°C Unit Test Conditions/Comments
POWER REQUIREMENTS VDD = +16.5 V, VSS = −16.5 V IDD 0.001 µA typ Digital inputs = 0 V or VDD 1.0 µA max IDD 170 µA typ Digital inputs = 5 V 285 µA max ISS 0.001 µA typ Digital inputs = 0 V or VDD 1.0 µA max ISS 0.001 µA typ Digital inputs = 5 V
1.0 µA max 1 Y version temperature range is −40°C to +125°C. 2 Guaranteed by design, not subject to production test.
Data Sheet ADG1204
Rev. C | Page 5 of 16
SINGLE SUPPLY VDD = 12 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.
Table 2. Y Version1
Parameter 25°C −40°C to +85°C
−40°C to +125°C Unit Test Conditions/Comments
ANALOG SWITCH Analog Signal Range 0 V to VDD V On Resistance (RON) 300 Ω typ VS = 0 V to 10 V, IS = −1 mA;
see Figure 21 475 567 625 Ω max VDD = 10.8 V, VSS = 0 V On Resistance Match Between Channels 5 Ω typ VS = 0 V to 10 V, IS = −1 mA
(ΔRON) 16 26 27 Ω max On Resistance Flatness (RFLAT(ON)) 60 Ω typ VS = 3 V, 6 V, 9 V; IS = −1 mA
LEAKAGE CURRENTS VDD = 13.2 V Source Off Leakage, IS (OFF) ±0.02 nA typ VS = 1 V/10 V, VD = 10 V/1 V; ±0.1 ±0.6 ±1 nA max see Figure 22 Drain Off Leakage, ID (OFF) ±0.02 nA typ VS = 1 V/10 V, VD = 10 V/1 V; ±0.1 ±0.6 ±1 nA max see Figure 22 Channel On Leakage, ID, IS (ON) ±0.02 nA typ VS = VD = 1 V or 10 V; see Figure 23
±0.2 ±0.6 ±1 nA max DIGITAL INPUTS
Input High Voltage, VINH 2.0 V min Input Low Voltage, VINL 0.8 V max Input Current, IINL or IINH 0.001 µA typ VIN = VINL or VINH
±0.1 µA max Digital Input Capacitance, CIN 2.5 pF typ
DYNAMIC CHARACTERISTICS2 Transition Time, tTRANS 150 ns typ RL = 300 Ω, CL = 35 pF
190 240 265 ns max VS = 8 V; see Figure 24 tON (EN) 95 ns typ RL = 300 Ω, CL = 35 pF 120 150 170 ns max VS = 8 V; see Figure 26 tOFF (EN) 100 ns typ RL = 300 Ω, CL = 35 pF 125 155 170 ns max VS = 8 V; see Figure 26 Break-Before-Make Time Delay, tD 50 ns typ RL = 300 Ω, CL = 35 pF 10 ns min VS1 = VS2 = 8 V; see Figure 25 Charge Injection −0.4 pC typ VS = 6 V, RS = 0 Ω, CL = 1 nF;
see Figure 27 Off Isolation 85 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 28 Channel-to-Channel Crosstalk 80 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 30 Bandwidth −3 db 550 MHz typ RL = 50 Ω, CL = 5 pF; see Figure 29 CS (OFF) 1.2 pF typ f = 1 MHz; VS = 6 V 1.5 pF max f = 1 MHz; VS = 6 V CD (OFF) 3.6 pF typ f = 1 MHz; VS = 6 V 4.2 pF max f = 1 MHz; VS = 6 V CD, CS (ON) 5.5 pF typ f = 1 MHz; VS = 6 V 6.5 pF max f = 1 MHz; VS = 6 V
ADG1204 Data Sheet
Rev. C | Page 6 of 16
Y Version1
Parameter 25°C −40°C to +85°C
−40°C to +125°C Unit Test Conditions/Comments
POWER REQUIREMENTS VDD = 13.2 V IDD 0.001 µA typ Digital inputs = 0 V or VDD 1.0 µA max IDD 170 µA typ Digital inputs = 5 V
285 µA max 1 Y version temperature range is −40°C to +125°C. 2 Guaranteed by design, not subject to production test.
Data Sheet ADG1204
Rev. C | Page 7 of 16
ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted.
Table 3. Parameter Rating VDD to VSS 35 V VDD to GND −0.3 V to +25 V VSS to GND +0.3 V to −25 V Analog Inputs1 VSS − 0.3 V to VDD + 0.3 V or
30 mA, whichever occurs first Digital Inputs1 GND − 0.3 V to VDD + 0.3 V or
30 mA, whichever occurs first Peak Current, S or D 100 mA (pulsed at 1 ms,
10% duty cycle maximum) Continuous Current 45 mA Operating Temperature Range
Automotive (Y Version) −40°C to +125°C Storage Temperature Range −65°C to +150°C Junction Temperature 150°C 14-Lead TSSOP, θJA Thermal
Impedance (4-Layer Board) 112°C/W
12-Lead LFCSP, θJA Thermal Impedance
80°C/W
Reflow Soldering Peak Temperature, Pb Free
260°C
1 Overvoltages at IN, S, or D are clamped by internal diodes. Current must be
limited to the maximum ratings given.
Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability.
Only one absolute maximum rating can be applied at any one time.
ESD CAUTION
ADG1204 Data Sheet
Rev. C | Page 8 of 16
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
TOP VIEW(Not to Scale)
1
2
3
4
5
6
7
NC = NO CONNECT
EN
VSS
S1
NC
D
S2
A0 14
13
12
11
10
9
8
GND
VDD
S3
NC
NC
S4
A1
0477
9-00
2
ADG1204
Figure 2. TSSOP Pin Configuration
VSS
S1
S2
GND
VDD
S3
D
NC S4
EN A0
A1
NOTES1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.2. THE EXPOSED PAD MUST BE TIED TO SUBSTRATE, VSS.
9
8
7
1
2
3
4 5 6
12 11 10
ADG1204TOP VIEW
(Not to Scale)
0477
9-00
3
Figure 3. LFCSP Pin Configuration
Table 4. Pin Function Descriptions Pin No.
Mnemonic Description TSSOP LFCSP 1 11 A0 Logic Control Input. 2 12 EN Active High Digital Input. When low, the device is disabled and all switches are off.
When high, Ax logic inputs determine on switches. 3 1 VSS Most Negative Power Supply Potential. 4 2 S1 Source Terminal. Can be an input or an output. 5 3 S2 Source Terminal. Can be an input or an output. 6 4 D Drain Terminal. Can be an input or an output. 7 to 9 5 NC No Connection. 10 6 S4 Source Terminal. Can be an input or an output. 11 7 S3 Source Terminal. Can be an input or an output. 12 8 VDD Most Positive Power Supply Potential. 13 9 GND Ground (0 V) Reference. 14 10 A1 Logic Control Input.
TRUTH TABLE
Table 5. EN A1 A0 S1 S2 S3 S4 0 X X Off Off Off Off 1 0 0 On Off Off Off 1 0 1 Off On Off Off 1 1 0 Off Off On Off 1 1 1 Off Off Off On
Data Sheet ADG1204
Rev. C | Page 9 of 16
TYPICAL PERFORMANCE CHARACTERISTICS
SOURCE OR DRAIN VOLTAGE (V)
ON
RES
ISTA
NC
E (Ω
)
200
180
160
140
120
100
60
80
0
20
40
–18 –15 –12 –9 –6 –3 3 9 150 6 12 18
0477
9-01
0
TA = +25°C
VDD = +15VVSS = –15V
VDD = +16.5VVSS = –16.5V
VDD = +13.5VVSS = –13.5V
Figure 4. On Resistance as a Function of VD (VS), Dual Supply
SOURCE OR DRAIN VOLTAGE (V)
ON
RES
ISTA
NC
E (Ω
)
450
400
350
300
250
150
200
0
50
100
–5 –4 –3 –2 –1 2 40 1 3 5
0477
9-00
4
VDD = +5.5VVSS = –5.5V
TA = +25°C
Figure 5. On Resistance as a Function of VD (VS), Dual Supply
VDD = 13.2VVSS = 0V
SOURCE OR DRAIN VOLTAGE (V)
ON
RES
ISTA
NC
E (Ω
)
450
400
350
300
250
150
200
0
50
100
0 2 4 6 8 10 12 14
0477
9-00
5
VDD = 12VVSS = 0V
VDD = 10.8VVSS = 0V
TA = 25°C
Figure 6. On Resistance as a Function of VD (VS), Single Supply
SOURCE OR DRAIN VOLTAGE (V)
ON
RES
ISTA
NC
E (Ω
)
250
150
200
0
50
100
–15 –10 –5 0 5 10 15
0477
9-00
6
VDD = +15VVSS = –15V
TA = +125°C
TA = +25°C
TA = +85°C
TA = –40°C
Figure 7. On Resistance as a Function of VD (VS) for Different Temperatures,
Dual Supply
SOURCE OR DRAIN VOLTAGE (V)
ON
RES
ISTA
NC
E (Ω
)
600
400
500
300
200
0
100
0 2 4 6 8 10 12
0477
9-00
7
VDD = +12VVSS = 0V
TA = +125°C
TA = +25°C
TA = +85°C
TA = –40°C
Figure 8. On Resistance as a Function of VD (VS) for Different Temperatures,
Single Supply
TEMPERATURE (°C)
LEA
KA
GE
(nA
)
0.30
0.20
0.25
0.15
0.10
0.05
0
–0.05
–0.10200 40 60 80 100 120
0477
9-00
8
IS (OFF)
ID (OFF)
ID, IS (ON)
VDD = +16.5VVSS = –16.5VVBIAS = +10V/–10V
Figure 9. Leakage Currents as a Function of Temperature, Dual Supply
ADG1204 Data Sheet
Rev. C | Page 10 of 16
TEMPERATURE (°C)
LEA
KA
GE
(nA
)
0.20
0.15
0.10
0.05
0
–0.15
–0.10
–0.05
–0.20200 40 60 80 100 120
0477
9-00
9
IS (OFF)
ID (OFF)
ID, IS (ON)
VDD = 13.2VVSS = 0VVBIAS = 10V/1V
Figure 10. Leakage Currents as a Function of Temperature, Single Supply
LOGIC, INX (V)
I DD
(µA
)
60
50
40
30
10
20
00 2 4 6 8 10 12 14
0477
9-01
1
VDD = +12V, VSS = 0V
VDD = +15V, VSS = –15V
IDD PER CHANNELTA = +25°C
Figure 11. IDD vs. Logic Level
VS (V)
CH
AR
GE
INJE
CTI
ON
(pC
)
6
4
2
0
–4
–2
–6–15 –10 –5 0 5 10 15
0477
9-01
4
VDD = +12V, VSS = 0V
VDD = +5V, VSS = –5V
VDD = +15V, VSS = –15V
SOURCE TO DRAINDRAIN TO SOURCETA = +25°C
Figure 12. Charge Injection vs. Source Voltage
TEMPERATURE (°C)
TIM
E (n
s)
250
200
150
100
50
0–40 –20 40200 60 80 100 120
0477
9-01
5
VDD = +12V, VSS = 0V
VDD = +15V, VSS = –15V
Figure 13. Transition Times vs. Temperature
FREQUENCY (Hz)
OFF
ISO
LATI
ON
(dB
)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–11010k 100k 1M 10M 100M 1G
0477
9-01
6
VDD = +15VVSS = –15VTA = +25°C
Figure 14. Off Isolation vs. Frequency
FREQUENCY (Hz)
CR
OSS
TALK
(dB
)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–120
–110
10k 100k 1M 10M 100M 1G
0477
9-01
7
VDD = +15VVSS = –15VTA = +25°C
S1 TO S2
S2 TO S4
Figure 15. Crosstalk vs. Frequency
Data Sheet ADG1204
Rev. C | Page 11 of 16
FREQUENCY (Hz)
ON
RES
PON
SE (d
B)
0
–10
–5
–15
–25
–20
–3010k 100k 1M 10M 1G100M 10G
0477
9-01
8
VDD = +15VVSS = –15VTA = +25°C
Figure 16. On Response vs. Frequency
FREQUENCY (Hz)
THD
+ N
(%)
10.00
1.00
0.10
0.0110 100 1k 10k 100k
0477
9-01
9
LOAD = +10kΩTA = +25°C
VDD = +5V, VSS = –5V, VS = +3.5Vrms
VDD = +15V, VSS = –15V, VS = +5Vrms
Figure 17. THD + N vs. Frequency
VBIAS (V)
CA
PAC
ITA
NC
E (p
F)
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0–10 –8 –6 –4 –2 0 2 4 6 8 10
0477
9-03
1
S2
S3
S1
S4
D
VDD = +15VVSS = –15VTA = +25°C
Figure 18. Off Capacitance vs. Source Voltage
VBIAS (V)
CA
PAC
ITA
NC
E (p
F)
6.5
6.1
6.3
5.9
5.7
5.5
5.3
5.1
4.9
4.7
4.5–10 –8 –6 –4 –2 0 2 4 6 8 10
0477
9-03
2
S2
S3
S1
S4
VDD = +15VVSS = –15VTA = +25°C
Figure 19. On Capacitance vs. Source Voltage
VBIAS (V)
CA
PAC
ITA
NC
E (p
F)
9
7
8
5
6
4
3
2
1
020 4 6 8 10 12
0477
9-03
3
SOURCE/DRAIN ON
SOURCE OFF
DRAIN OFF
VDD = 12VVSS = 0VTA = 25°C
Figure 20. Capacitance vs. Source Voltage, Single Supply
ADG1204 Data Sheet
Rev. C | Page 12 of 16
TEST CIRCUITS
IDS
S D
VS
0477
9-02
0
V
Figure 21. On Resistance
S D
VS
A A
VD
IS (OFF) ID (OFF)
0477
9-02
1
Figure 22. Off Leakage
S D A
VD
ID (ON)
NC
NC = NO CONNECT
0477
9-02
2
Figure 23. On Leakage
VS
S1
DGND CL
35pFRL300Ω
VOUT
50% 50%
90%90%
ADDRESSDRIVE (VIN))
VOUT
A0
A1
S4
S3
S2
VS1
VS4
EN2.4V
0V
3V
tTRANSITION
tTRANSITION
VDD0.1µF
VSS
VDD VSS
0.1µF
0477
9-02
3
Figure 24. Address to Output Switching Times
ADDRESSDRIVE (VIN)
VOUT
VS
S1
DGND CL
35pFRL300Ω
50Ω
VOUT
A0
A1
S4
S3
S2
VS1
EN2.4V
VDD0.1µF
VSS
VDD VSS
0.1µF
0477
9-02
4
tBBM
80% 80%
0V
3V
Figure 25. Break-Before-Make Time Delay
ENABLEDRIVE (VIN)
S1
DGND CL
35pFRL300Ω
VOUT
A0
A1
S4
S3
S2
VS
EN
VDD0.1µF
VSS
VDD VSS
0.1µF
VS 50Ω
0477
9-02
5
tOFF (EN)tON (EN)
50% 50%
0.9VO0.9VO
OUTPUT
0V
3V
VO
0V
Figure 26. Enable-to-Output Switching Delay
Data Sheet ADG1204
Rev. C | Page 13 of 16
S D
VS
GND
RS
SW OFF
QINJ = CL × ΔVOUT
SW OFF
SW ON
SW OFF SW OFF
A2A1
EN
VDD VSS
VDD
DECODER
VSS
VOUT
VOUT
VIN
VIN
ΔVOUT
CL1nF
0477
9-02
6
SW ON
Figure 27. Charge Injection
VOUT
50Ω
NETWORKANALYZER
RL50Ω
S
D
50Ω
OFF ISOLATION = 20 logVOUT
VS
VS
VDD VSS
0.1µFVDD
0.1µFVSS
GND
0477
9-02
7
Figure 28. Off Isolation
VOUT
50Ω
NETWORKANALYZER
RL50Ω
S
D
INSERTION LOSS = 20 logVOUT WITH SWITCH
VOUT WITHOUT SWITCH
VS
VDD VSS
0.1µFVDD
0.1µFVSS
GND
0477
9-02
8
Figure 29. Bandwidth
CHANNEL-TO-CHANNEL CROSSTALK = 20 logVOUT
GND
S1
DS2
VOUT
NETWORKANALYZER
RL50Ω
R50Ω
VS
VS
VDD VSS
0.1µFVDD
0.1µFVSS
0477
9-02
9
Figure 30. Channel-to-Channel Crosstalk
VOUT
RS
AUDIO PRECISION
RL10kΩ
IN
VIN
S
DVS
V p-p
VDD VSS
0.1µFVDD
0.1µFVSS
GND
0477
9-03
0
Figure 31. THD + Noise
ADG1204 Data Sheet
Rev. C | Page 14 of 16
TERMINOLOGY IDD The positive supply current.
ISS The negative supply current.
VD (VS) The analog voltage on Terminal D and Terminal S.
RON The ohmic resistance between D and S.
RFLAT(ON) Flatness is defined as the difference between the maximum and minimum value of on resistance, as measured over the specified analog signal range.
IS (OFF) The source leakage current with the switch off.
ID (OFF) The drain leakage current with the switch off.
ID, IS (ON) The channel leakage current with the switch on.
VINL The maximum input voltage for Logic 0.
VINH The minimum input voltage for Logic 1.
IINL (IINH) The input current of the digital input.
CS (OFF) The off switch source capacitance, which is measured with reference to ground.
CD (OFF) The off switch drain capacitance, which is measured with reference to ground.
CD, CS (On) The on switch capacitance, measured with reference to ground.
CIN The digital input capacitance.
tON (EN) The delay between applying the digital control input and the output switching on.
tOFF (EN) The delay between applying the digital control input and the output switching off.
tTRANS The delay time between the 50% and 90% points of the digital input and switch on condition when switching from one address state to another.
Charge Injection A measure of the glitch impulse transferred from the digital input to the analog output during switching.
Off Isolation A measure of unwanted signal coupling through an off switch.
Crosstalk A measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance.
Bandwidth The frequency at which the output is attenuated by −3 dB.
On Response The frequency response of the on switch.
Insertion Loss The loss due to the on resistance of the switch.
Total Harmonic Distortion + Noise (THD + N) The ratio of the harmonic amplitude plus noise of the signal to the fundamental.
Data Sheet ADG1204
Rev. C | Page 15 of 16
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MO-153-AB-1 0619
08-A
8°0°
4.504.404.30
14 8
71
6.40BSC
PIN 1
5.105.004.90
0.65 BSC
0.150.05 0.30
0.19
1.20MAX
1.051.000.80
0.200.09 0.75
0.600.45
COPLANARITY0.10
SEATINGPLANE
Figure 32. 14-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-14) Dimensions shown in millimeters
1.451.30 SQ1.15
1118
08-A
10.50BSC
BOTTOM VIEWTOP VIEW
12
46
7
9
10
3
EXPOSEDPAD
PIN 1INDICATOR
3.103.00 SQ2.90
0.700.600.50
SEATINGPLANE
0.05 MAX0.02 NOM
0.20 REF
0.25 MIN
COPLANARITY0.08
PIN 1INDICATOR
0.300.230.18
COMPLIANT TO JEDEC STANDARDS MO-220-WEED.
FOR PROPER CONNECTION OFTHE EXPOSED PAD, REFER TOTHE PIN CONFIGURATION ANDFUNCTION DESCRIPTIONSSECTION OF THIS DATA SHEET.
0.800.750.70
Figure 33. 12-Lead Lead Frame Chip Scale Package [LFCSP]
3 mm × 3 mm Body and 0.75 mm Package Height (CP-12-4)
Dimensions shown in millimeters
ORDERING GUIDE Model1 Temperature Range Package Description Package Option ADG1204YRUZ −40°C to +125°C 14-Lead Thin Shrink Small Outline Package [TSSOP] RU-14 ADG1204YRUZ-REEL −40°C to +125°C 14-Lead Thin Shrink Small Outline Package [TSSOP] RU-14 ADG1204YRUZ-REEL7 −40°C to +125°C 14-Lead Thin Shrink Small Outline Package [TSSOP] RU-14 ADG1204YCPZ-500RL7 −40°C to +125°C 12-Lead Lead Frame Chip Scale Package [LFCSP] CP-12-4 ADG1204YCPZ-REEL7 −40°C to +125°C 12-Lead Lead Frame Chip Scale Package [LFCSP] CP-12-4 1 Z = RoHS Compliant Part.
ADG1204 Data Sheet
Rev. C | Page 16 of 16
NOTES
©2005–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04779-0-3/16(C)
