Lowest VIN Possible for Switched-Inductor Boost Converters

Tianyu Chang, Graduate Student Member, IEEE, and Gabriel A. Rincón-Mora, Fellow, IEEE Georgia Institute of Technology, Atlanta, Georgia 30332-0250, U.S.A.

E-mail: tianyuchang@gatech.edu and Rincon-Mora@gatech.edu Abstract—The minimum input voltage from which switched-inductor boost converters can draw power is a critical parameter, especially for power supplies that draw power from low-voltage sources like thermoelectric generators. When a battery is absent or fully discharged, the power supply relies on a millivolt input to wake and supply the system. This paper explains and quantifies what determines this minimum threshold both with and without a charged battery present. Analyses show that CMOS converters can wake with 44 mV, but not output power until the input source voltage vS is 268 mV. With a charged battery, they can transfer energy with 4.6 mV, but not output net power until vS is 64 mV.

Keywords—Switched inductor, CMOS boost converter, power supply, charger, minimum input voltage, wake, startup.

I. SWITCHED-INDUCTOR BOOST CONVERTERS Wireless microsensors can save energy and save lives [1]–[4]. They can rely on 40–350-mV photovoltaic (PV) cells and thermoelectric generators (TEGs) for energy and power [5]. Chargers and regulators must therefore boost this 40–350 mV to 0.5–2.0 V so that wireless microsystems can operate.

With such a low input voltage vIN and a resistive source, input power is very low. The power supply should therefore be as power efficient as possible. This is why switched inductors (SLs) are so popular. When the battery is absent or fully discharged, however, the SL in Fig. 1 must wake with a low vIN. Even when the battery voltage is over the headroom voltage VHR of the CMOS circuit [6], vIN must still rise above a certain threshold for the boost converter to output net power.

SRCE

LOAD

vIN

CIN

LX SG DOvO

Switched-Inductor Boost Converter

Fig. 1. Sourced and loaded switched-inductor boost.

The value of this theoretical limit is absent in literature [5], [7], [10], and [13]. This paper therefore explains and quantifies the lowest possible voltage of the input source with which SL boost converters can wake and can output net power. Sections II and III derive this threshold without and with a charged battery present, respectively. Section IV then discusses the effects of temperature and Section V draws final conclusions.

II. WAKE THRESHOLDS MG in the SL boost from Fig. 2 closes to energize LX from vIN. When MG opens, LX's current iL charges CSW until DO forward-biases and steers iL into the output CO. But when the output (battery) is fully discharged, the SL relies on the low-voltage source vS to wake the microsystem. RS is the source resistance.

When the source vS raises vIN above the SL's first threshold, vIN supplies the ring oscillator and drives the switch MG. Below

this functional threshold vW(F), the oscillator does not work. vW(F) is therefore the lowest vS with which the SL can operate. The SL, however, cannot output power PO until input power PIN is high enough to supply the power lost in the SL. Thus, loss-limited output threshold vW(O) is the lowest vS such that the SL can output power when waking without a charged output.

vIN

CIN Osc.

RS

vS

LX RL vSW vO

DOCOCSWMG

vGG

iLiOSCiDRVvGG'

iRS

Fig. 2. Waking (input-supplied) switched-inductor boost.

A. Wake Functional Threshold In the ring oscillator, one inverter drives another. So vIL equals vOL, and vIH equals vOH, where vIH, vOH, vIL, and vOL are the high and the low voltage levels of the input and the output of an inverter, respectively. An inverter is a series stack of PMOS and NMOS, so the gate-source voltages vGS's and the drain-source voltages vDS's of the inverter's PMOS and NMOS add up to vIN: vIN = vSGP + vGSN = vSDP + vDSN, (1) where vIN is the oscillator's supply voltage as labeled in Fig. 2.

When vS is near vW(F), the ring oscillator is in sub-threshold (later validated by vW(F)'s value), and the boost hardly draws current from vS. So, vRS (the voltage across RS) is negligible and vIN is near vS. MOSFET sub-threshold current iM(ST) is [8]:

( ) GS DSM(ST) S

t t

v vWi I exp 1 expL nV V

⎡ ⎤⎛ ⎞ ⎛ ⎞−= −⎢ ⎥⎜ ⎟ ⎜ ⎟⎜ ⎟ ⎜ ⎟⎢ ⎥⎝ ⎠ ⎝ ⎠⎣ ⎦

, (2)

where n is sub-threshold slope factor, and Vt is thermal voltage. When the inverter's input is high and output is low, its PMOS current iMP(ST) equals its NMOS current iMN(ST), and vice versa: iMN ST( ) = iMP ST( ) vGSN=vIH , vDSN=vOL

(3)

and iMP ST( ) = iMN ST( ) vGSN=vIL , vDSN=vOH. (4)

The oscillator halts if vOH equals vOL, and it oscillates if vOH is higher than vOL [9]. Solving the lowest vS such that vOH is higher than vOL using (1) – (4) gives vW(F). Fig. 3 plots the calculated vW(F) versus PMOS and NMOS widths WP and WN.

5101 152 3

60

4 5 206 7

80

8 9 2510

100120

v W(F

) [m

V]

vW(F) when vOH > vOL

40

Fig. 3. Wake functional threshold across WP and WN.

In addition to [9], this paper finds the optimal WP and WN. In Fig. 3, the solid line labels the lowest vW(F) (denoted by vW(F)'). It shows that the optimal WP and WN can counter the

differences between PMOS and NMOS in mobility µ, sub-threshold slope factor n, and MOSFET threshold voltage vTH to balance their strengths, and thus can reduce vW(F). vW(F)' is 44 mV in simulation. By observation the optimal sizes satisfy:

( )( )

( )

( )

( ) ( )

S W(F)

S N TH P TH NN NP

P P P t N tS PN v v '

I v vW L n expI n n V n VW L=

µ ⎡⎛ ⎞ ⎛ ⎞⎤= = −⎜ ⎟ ⎜ ⎟⎢ ⎥µ ⎣⎝ ⎠ ⎝ ⎠⎦

. (5)

Fig. 4 plots the error compared with simulations using 0.18-µm CMOS. The highest error of the vW(F) analysis is 7.06%. With vTH variations, vW(F) is about 44–220 mV across corners.

v W(F

) Erro

r [%

]

–4100

8

4

25

8

6 20154 102 5

Fig. 4. Wake functional threshold error (compared with simulations).

B. Wake Loss-Limited Output Threshold This paper finds vW(O) in two steps. First, find the lowest vIN for the SL boost to output energy. Then, add vRS to vIN to get the minimum source voltage vW(O). High CIN suppresses the voltage ripple of vIN, so vIN, vRS, and iRS are roughly dc. To reduce cost, MG is not a native NMOS [10]. So, MG is in sub-threshold (later validated by vW(O)'s value) and its conduction resistance RMG is much higher than the inductor's equivalent series resistance (ESR) RL. Thus, RL is neglected. The boost is in Discontinuous Conduction Mode (DCM) since the current level is low. The wake-up process ends if vO is charged to VHR.

The boost converter in Fig. 2 can output energy if the inductor LX's peak energy EL(PK), along with the input energy EIN(D) provided by vIN during the drain phase, can charge CSW to one diode voltage vD above the output voltage vO: EIN(D) + EL(PK) > ECSW(VO + VD). (6) Parasitic pin capacitance CSW(PIN) and MG's drain capacitance add up to the total capacitance CSW. CSW's loss ECSW(VO+VD) is: ECSW(VO+VD) = 0.5CSW(vO + vD)2. (7) Fig. 5 shows that this high sub-threshold RMG limits the growth of LX's current iL. LX's highest current is iL(PK), and EL(PK) is:

( )

22 IN

X L(PK) XL PKMG

vE 0.5L i 0.5L

R⎛ ⎞= = ⎜ ⎟⎝ ⎠

. (8)

As iL drains CSW across drain time tD (LXCSW's quarter resonance period tLC/4), iL's sinusoid draws EIN(D) from vIN:

( ) ( ) ( )

LCIN D IN L(D.AVG) D ININ D IN D.AVG L PK

t2E v i t v i t v i4

⎛ ⎞⎛ ⎞= ≈ = ⎜ ⎟ ⎜ ⎟π⎝ ⎠ ⎝ ⎠, (9)

where iIN(D.AVG) and iL(D.AVG) are the averaged input current and averaged inductor current across the drain time tD (a quarter of tLC). Substitute (7), (8), and (9) into (6), and solve for vIN:

( ) SWIN O D MG

X MG LC

Cv v v R L R tπ

= +π +

. (10)

The oscillator's switching period tOSC is long since it is in sub-threshold. So iL is roughly a square wave (Fig. 5). Assuming the oscillator has 50% duty-cycle, LX's average current iL(AVG) is:

( ) ( )IN

L AVG L PKMG

vi 0.5i 0.5

R⎛ ⎞≈ = ⎜ ⎟⎝ ⎠

. (11)

The driver draws average current iC(MG.AVG) to charge/discharge MG's gate capacitance CG(MG) to turn on/off MG. iC(MG.AVG) is:

( )

( ) ING MG OX MG MG INC MG.AVG

OSC OSC

C v C "W L vi

t t= = , (12)

where WMG and LMG are MG's width and length. Neglecting the oscillator's current consumption iOSC, the theory finds vRS by:

( ) ( )RS S L(AVG) C(MG.AVG) SRS AVGv i R i i R= ≈ + . (13)

The theory then finds the minimum source voltage vW(O) by: vW(O) = vRS + vIN, (14) and vW(O) is the lowest vS such that vO can be charged to VHR.

0 tOSC0.5tOSC

i L [µ

A]

Time [s]–50

050

100150200

1.5tOSC

tE ≈ 0.5tOSC

Simulated: vS = vW(O)

0.25tOSC 0.75tOSC 1.25tOSC

tD = 0.25tLC

Fig. 5. Simulated inductor current during wake-up.

VHR is 1V, RS is 350 Ω (TEG resistance [11]), vD is 0.4 V, and tOSC is 100 µs in calculations and simulations. Fig. 6 plots the calculated vW(O) versus WMG and LX. Raising WMG lowers RMG and thus reduces the lowest vIN required to output energy. But raising WMG raises MG's parasitic capacitance. This raises iC(MG.AVG) and raises vRS. Therefore, the lowest source voltage vW(O) (denoted by vW(O)' in Fig. 6) for a given LX satisfies:

( )

( )W O

W O RS IN

MG MG MG v '

v v v0

W W W∂ ∂ ∂

= + =∂ ∂ ∂

. (15)

024250300350400

6

450500

10 810100

v W(O

) [m

V]

RS = 350 Ω 22 Ω ≤ RL ≤ 110 Ω CSW(PIN) = 8 pF vO = VHR = 1 V

Calculated:vW(O) when PO > 0

2

Fig. 6. Wake loss-limited output threshold across WMG and LX.

Fig. 7 plots the error compared with simulations using 0.18-µm CMOS. The highest error of the vW(O) analysis is 9.84%.

102

8

4

100

68

6410 2v W(O

) Erro

r [%

] 10

Fig. 7. Wake loss-limited output threshold error (compared with simulations).

Since the SL boost often wakes the system with a low vS [6], vW(O) is the bottleneck and should be minimized. A higher LX carries more energy for a given current, and thus can reduce vW(O). Since RMG is much higher than the inductor's ESR RL, we should use the highest LX within the system's volume constraints regardless of RL to minimize vW(O). For system miniaturization, miniature inductors should be used. Off-the-shelf miniature inductors can offer a highest LX of 10 mH (3.7 × 3 × 3.6 mm3) with 110 Ω ESR. With this miniature inductor, vW(O)' is 268 mV in simulations and is 280 mV in calculations.

0.7 0.8 0.9 1.0 1.1 1.2250

270

290

3.03.54.04.55.0

v W(O

)' [m

V]

Erro

r [%

]

VHR [V]

RL = 110 Ω LX = 10 mH

RS = 350 Ω CSW(PIN) = 8 pF

Fig. 8. Wake loss-limited output threshold across headroom level.

Fig. 8 plots the calculated and simulated vW(O)' versus VHR. Raising VHR raises the loss in CSW and raises vW(O)'. Thus, VHR should be the lowest voltage that meets system specifications.

III. STATIC THRESHOLDS When the SL boost's output vO is above VHR, which is the lowest voltage to supply the system's controller and to fully turn on power switches [6], vO supplies the controller and the gate-driver in Fig. 9. This way, the boost charges or regulates vO. Under this static steady-state condition, the static functional threshold vS(F) is the lowest vS such that the boost can operate.

Static transfer-limited threshold vS(X) is the lowest vS such that iL can charge CSW until comparator CPO closes MO [14] to let iL drain and transfer energy into CO. However, the boost does not output net power to vO until input power PIN is high enough to overcome all the power losses, including the power lost in the vO-supplied controller and the gate-drivers. Static loss-limited output threshold vS(O) is thus the lowest vS such that the boost can output net power when operating with a charged output.

vIN

CIN

RS

vS

LX RL vSW vO

MO

COCSWMGvGG

iL

vCTRL

vGO CPOiRS

Fig. 9. Static (output-supplied) switched-inductor boost.

A. Static Functional Threshold In static operation vO is above VHR, so the controller and the driver can always operate. Therefore, the SL boost can always draw energy from vS if vS is above 0 V. Therefore, vS(F) is 0 V. B. Static Transfer-Limited Threshold In static operation, the vO-supplied driver turns MG fully on. Thus, MG's on-resistance RMG is low (less than 1 Ω). Again, for miniaturized systems, the miniature inductor's ESR RL can be up to 110 Ω. Thus, RL overwhelms RMG, and RMG is neglected.

LX can transfer energy to vO if its peak energy EL(PK), along with the input energy EIN(D) offered by vIN across the drain phase, can overcome RL's loss ERL and charge CSW above vO: EIN(D) + EL(PK) > ECSW(VO) + ERL. (16) The boost operates differently to minimize vS(X). After vIN is charged to vS, the controller closes MG to energize LX. This maximizes the voltage across LX. Moreover, a high CIN holds vIN close to vS across the energizing time tE until iL reaches its limit. This maximizes EL(PK) and thus minimizes vS(X). EL(PK) is:

( )

2 22 IN S

X L(PK) X XL PKL L

v vE 0.5L i 0.5L 0.5L

R R⎛ ⎞ ⎛ ⎞= = ≈⎜ ⎟ ⎜ ⎟⎝ ⎠ ⎝ ⎠

. (17)

ECSW(VO) is the energy lost in CSW. ECSW(VO) is: ECSW(VO) = 0.5CSWvO

2. (18) Similarly, at vS(X), iL drains into CSW across a quarter of LX-CSW resonance period tLC. During this drain time tD, ERL is:

( )2

L PK2 LCRL L(D.RMS) L D L

i tE i R t R

42⎛ ⎞ ⎛ ⎞= ≈⎜ ⎟ ⎜ ⎟

⎝ ⎠⎝ ⎠, (19)

where iL(D.RMS) is LX's root-mean-square (RMS) current during tD. Like (9), during this drain time tD, vIN offers energy EIN(D):

( ) ( ) ( )

LCIN D S L(D.AVG) D SIN D IN D.AVG L PK

t2E v i t v i t v i4

⎛ ⎞⎛ ⎞= ≈ ≈ ⎜ ⎟ ⎜ ⎟π⎝ ⎠ ⎝ ⎠. (20)

Substitute (17), (18), (19), and (20) into (16), and solve for vS:

( ) ( ) ( )SW

S L OS XX L LC L LC

Cv v R v

L R t 4 R t= ≈

− + π. (21)

Fig. 10 plots the calculated vS(X) versus LX and RL when vO is 1.4 V. Fig. 11 shows that the highest error is 10.99%.

1008060

1020

1 402

30

3

40

4 5 206 7 8 9 10

v S(X

) [m

V] vS(X) when iL drains into vO

RS = 350 Ω CSW(PIN) = 8 pFvO = 1.4 V

Calculated0

Fig. 10. Static transfer-limited threshold across LX and RL.

For miniaturization, the inductor used in static operation must be the same inductor used for system wake-up (10 mH with 110 Ω ESR in this paper) to reduce system volume. In this case, vS(X) is 4.6 mV in simulation (4.36 mV in calculation).

2040210

4

608

6

6 80

8

4

10

1002v S(X

) Erro

r [%

]

5%

Fig. 11. Static transfer-limited threshold error (compared with simulations).

C. Static Loss-Limited Output Threshold Similarly, vIN, vRS, iRS are roughly dc in static operation, and the boost converter operates in DCM. The input power PIN is: PIN = PS – PRS, (22) where PS is the power from vS, PRS is the power burned in RS.

( )S IN

S S SRS AVGS

v vP v i v

R−⎛ ⎞= = ⎜ ⎟

⎝ ⎠, (23)

and ( )2S INRS

S

v vP

R−

= . (24)

At vS(O), vIN is much lower than vO, so drain time tD is much less than energizing time tE (Fig. 12). LX's peak current iL(PK) is:

( )

IN INE XL PK

X X

v vi t t

L L⎛ ⎞ ⎛ ⎞= ≈⎜ ⎟ ⎜ ⎟⎝ ⎠ ⎝ ⎠

, (25)

where tX = (tE + tD) is the time during which the boost converter draws and transfers energy. RL's power loss PRL is:

( )2

L PK2 SWXRL L(RMS) L L

SW X

i ftP i R R

t f3⎛ ⎞⎛ ⎞ ⎛ ⎞= ≈⎜ ⎟⎜ ⎟ ⎜ ⎟

⎝ ⎠ ⎝ ⎠⎝ ⎠, (26)

where iL(RMS) is the RMS value of iL, fX is the reciprocal of tX, and fSW is the switching frequency. CSW's power loss PCSW is: PCSW = 0.5CSWvO

2fSW. (27) Again, the inductor used in static operation is the same

inductor used for system wake-up. Thus, RL is much higher than RMG, and RL's ohmic loss PRL is much higher than RMG's conduction loss PMR. Also, for optimized power switches, the gate-drive loss PMC should be equal to the conduction loss PMR [12]. Thus, PMR and PMC are both negligible compared to PRL.

0100

200

i L [µ

A]

59 µs

tSW = 377 µs 0 0.50tSW 1.00tSW 1.50tSW

Time

vS = vS(O)' ≈ 64 mVLX = 10 mH RL = 110 ΩCSW(PIN) = 8 pF vO = 1.4 V

tE

0.25tSW 0.75tSW 1.25tSW

tD ≈ 2 µsSimulated

–100

Fig. 12. Inductor current at the static loss-limited output threshold.

Part of the controller is always on (i.e., voltage monitoring circuits), and draws steady state current iQ(SS). Its loss PQ(SS) is: PQ(SS) = iQ(SS)vO. (28)

The other part of the controller is duty-cycled (i.e., comparator CPO), and draws current iQ(X) only during tX. Its loss PQ(X) is:

( ) ( ) ( )SWX

O OQ X Q X Q XSW X

ftP i v i v

t f⎛ ⎞ ⎛ ⎞= =⎜ ⎟ ⎜ ⎟⎝ ⎠ ⎝ ⎠

. (29)

Neglecting PMR and PMC, the total loss is approximately: PLOSS ≈ PRL + PCSW + PQ(SS) + PQ(X). (30) The minimum vS such that PIN is no less than PLOSS is vS(O):

( )

( ) ( )

INS(O) S IN IN(AVG) S IN S INRS AVG

IN

RL CSW Q SS Q XLOSSS IN S IN

IN IN

Pv i R v i R v R v

vP P P PP

R v R v .v v

⎛ ⎞= + = + = +⎜ ⎟

⎝ ⎠+ + +⎛ ⎞⎛ ⎞

= + ≈ +⎜ ⎟⎜ ⎟ ⎜ ⎟⎝ ⎠ ⎝ ⎠

(31)

Figure 13 plots the simulated and calculated vS(O) when iQ(SS) is 151 nA [13], iQ(X) is 2.45 µA [14], and fX is 16.7 kHz. PIN rises when fSW climbs because the converter draws energy more frequently. Except, PCSW and PQ(X) also increase with fSW. So the lowest vS(O) (called vS(O)') results at the fSW that balances PIN, PCSW, and PQ(X). (vIN is not the 0.5vS that conventional maximum-power-point theory predicts because the inductor needed for wake-up adds RL's 110 Ω to RS. So with the values mentioned, theory predicts vS(O)' is 63 mV and simulations show that vS(O)' is 64 mV, where the highest error in Fig. 14 is 2.25%. vS(O)' in [15] is lower at 20 mV because RL in [15] is only 230 mΩ, which requires a bulkier LX.

0 1 2 3 4 5 6 7 8 9 106065707580

fSW [kHz]

v S(O

) [m

V]

vS(O)' ≈ 64 mV @ 2.65 kHz

vS(O)' ≈ 63 mV @ 2.71 kHz

LX = 10 mH RL = 110 Ω CSW(PIN) = 8 pF vO = 1.4 V

vS(O) when PIN > PLOSS

Fig. 13. Static loss-limited output threshold across switching frequency.

0 1 2 3 4 5 6 7 8 9 100.51.01.52.02.5

fSW [kHz]v S(O

) Erro

r [%

]

Fig. 14. Static loss-limited output threshold error (compared with simulations).

IV. EFFECTS OF TEMPERATURE Figure 15 plots vOH, vOL, and trip-point vTRIP of an optimally sized inverter under different supply voltages vS at 0°C, 27°C, and 85°C when normalized to the thermal voltage Vt. When vS is below vW(F)', vOH equals vOL, so the inverter cannot invert and cannot function. When vS is higher than vW(F)', vOH is higher than vOL. So the inverter can trip and the oscillator can function. Simulations at these three temperatures match and show that vW(F)' is 1.69Vt to 1.76Vt. During wake-up, MG is in sub-threshold, where current is largely the result of diffusion. So RMG falls as temperature climbs, which means iL(PK) and EL(PK) rise. vW(O)' therefore drops when temperature climbs.

Since wake-up requires an LX with a RL that is high and climbs with temperature, static operation suffers the same RL. vS(X) and vS(O) therefore rise with temperature. Table I summarizes the input source voltage thresholds and their simulated temperature coefficients (TCs).

V. CONCLUSIONS This paper theorizes the minimum input source voltage vS for

switched-inductor boost converters with and without a charged battery. Theory shows that without a charged battery, boost converters can wake with 44 mV, but not output power until vS is 268 mV. With a charged battery, they can transfer energy with 4.6 mV, but cannot output power until vS is 64 mV. Simulations using 0.18-µm CMOS validate this theory.

Vol

tage

[Vt]

0.001.252.503.755.00

0 1 2 3 4 5vS [Vt]vOL

vW(F)' ≈ 1.73Vt

Simulated at 0°C, 27°C, and 85°C

Fig. 15. Simulated vOH, vOL, and vTRIP across vS at 0°C, 27°C, and 85°C.

Table I: VOLTAGE THRESHOLDS AND TEMPERATURE COEEFFICENTS (TCS) vW(F) vW(O) vS(F) vS(X) vS(O) Unit

Theory 27°C 42.5 280 0 4.36 63 mV Simulated 27°C 44 268 0 4.6 64 mV

Error 3.4% 4.5% 0 5.2% 1.6% Simulated TC 150 –700 0 20 90 µV/°C

* RS = 350 Ω, LX = 10 mH, RL = 110 Ω at 27°C, and CSW(PIN) = 8 pF.

ACKNOWLEDGMENT The authors thank Drs. A. Blanco, O. Lazaro, and J. Morroni and Texas Instruments for their sponsorship and support.

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