MEC/P08/03/R02LESSON PLAN

Name: G.Sathya Designation/Dept: Lecturer/ECESub. Code: CS2202 Faculty Code: ECE13Sub. Name: Digital Principles and System Design Sem /Year: III/II CSE A

S.No Week No Date Period Topics to be covered Remarks

UNIT I BOOLEAN ALGEBRA AND LOGIC GATES

1.

1

20.07.09 1, 5 Introduction2. 21.07.09 3, 6 Review of binary number systems3. 22.07.09 3 Binary number system4. Binary arithmetic5. 23.07.09 4 Binary arithmetic6. 24.07.09 6 Binary codes7.

2

27.07.09 1, 5 Boolean algebra and theorems8. 28.07.09 3, 6 Boolean algebra and theorems9. 29.07.09 3 Boolean functions10. 30.07.09 4 Simplifications of Boolean

functions using Karnaugh map11. 31.07.09 6 Tabulation methods

12.

3

03.08.09 1, 5 Tabulation methods, Logic gates

13. 04.08.09 3, 6 Logic gates

14. 05.08.09 3 Logic gates

UNIT II COMBINATIONAL LOGIC

15.3

06.08.09 4 Introduction- Combinational circuits

16. 07.08.09 6 Combinational circuits17.

410.08.09 1, 5 Combinational circuits

18. 11.08.09 3, 6 Analysis and design procedures19. 12.08.09 3 Circuits for arithmetic operations20.19

5

17.08.09 4 Circuits for arithmetic operations

21.20

18.08.09 6 Code conversion

22.21

20.08.09 1, 5 Code conversion

23.22

21.08.09 3, 6 Code conversionIntroduction to Hardware Description Language (HDL)24.

2325.24

22.08.09 3

26.5

6

24.08.09 4 Introduction to Hardware Description Language (HDL)

27. 25.08.09 6 Problems

28. 27.08.09 5 Problems

29. 28.09.09 3, 6 Problems

30. 29.08.09 3 Problems

S.NoWeek

No Date Period Topics to be covered Remarks

UNIT III DESIGN WITH MSI DEVICES

31.27

7

31.08.09 4 Decoders

32.29

01.09.09 6 Encoder

33.30

03.09.09 1, 5 Multiplexers

34.31 04.09.09

3 Demultiplexers

35.32

6 Demultiplexers

36.33

05.09.09 3 Memory and programmable logic

37.

8

07.09.09 4 Memory and programmable logic38. 08.09.09 6

HDL for combinational circuits39. 10.09.09 1, 5

HDL for combinational circuits40. 11.09.09 3, 6

HDL for combinational circuits41. 12.09.09 3 Problems

42.

9

14.09.09 4 Problems

43. 15.09.09 6 Problems

UNIT IV SYNCHRONOUS SEQUENTIAL LOGIC

44.

9

17.09.09 1, 5 Sequential circuits

45. 18.09.09 3, 6 Flip flops

46. 19.09.09 3 Analysis and design procedures47.

10

22.09.09 4 State reduction

48. 23.09.09 6 State reduction49. 25.09.09 5 State assignment50. 26.09.09 3, 6 State assignment51.

11

29.09.09 352. 30.09.09 4 Shift registers

53. 01.10.09 6 Shift registers

54.

12

06.10.09 1, 5 Counters

07.10.09 3, 6 Counters

55. 08.10.09 3 Counters56. 09.10.09 4 HDL for sequential logic circuits

57. 10.10.09 6 HDL for Shift registers and counters.

S.No Week No Date Period Topics to be covered Remarks

UNIT V ASYNCHRONOUS SEQUENTIAL LOGIC

58.

13

13.10.09 1, 5 Analysis asynchronous sequential circuits

59. 14.10.09 3 Analysis asynchronous sequential circuits60. 6

61. 15.10.09 3 Design of asynchronous sequential circuits

62. 16.10.09 4 Design of asynchronous sequential circuits

63.

14

20.10.09 6 Reduction of state and flow tables64. 22.10.09 1, 5 Reduction of state and flow tables65. 23.10.09 3 Race –free state assignment

666. 24.10.09 3 Race –free state assignment67.

15

26.10.09 468. 27.10.09 6 Hazards.69. 28.10.09 5 Hazards.70. 29.10.09 3, 6 ASM chart 71. 31.10.09 3 ASM chart

TEXT BOOKS

1. M.Morris Mano, “Digital Design”, 3rd edition, Pearson Education, 2002.

REFERENCES

1. Charles H.Roth, Jr. “Fundamentals of Logic Design”, 4 th Edition, Jaico Publishing House, 2000.

2. Donald D.Givone, “Digital Principles and Design”, Tata McGraw-Hill, 2003.

Signature of Faculty Signature of HOD

Assignment No. Topics Date of

Submission

1 Problems 11.08.09

2 Problems 15.09.09

3 Multiplexers & Demultiplexers 29.09.08

4 Shift registers & Counters 13.10.09

5 Reduction of State & Flow tables 23.10.09