1

Lund Circuit Design Workshop, 2009

“Circuit Design for the Wireless Future”

Peter NilssonProfessor

Viktor ÖwallViktor ÖwallAssociate Professor

Digital ASIC GroupDepartment of Electrical and Information Technology

Digital ASIC Group: Project Overview

Digital Baseband OFDM Faster-

New

New

NewWeak

Inversion Baseband

than-NyquistMIMO-OFDM

Channel Estimation

OFDM Multi-tasking RadioWeak

Inversion Decoding

amfo

rmin

g ...

New New

Nanowires for Digital Design

Weak Inversion

Architectures

Parabolic Synthesis

Recon-figurable

Computing

Bea

Faster-than-Nyquist Signaling

Motivation:- Increased bandwidth efficiency

HSWC/SSF

OFDM symbols

Previous theoretical work shows advantages of FTN

Implementations of FTN based system do not exist tt

frequ

ency

system do not exist

Cost: increased processing complexity

Start: January 2007Deepak Dasalukunte

tFTNtOFDM

time

Compressed symbols

Objectives

Realize efficient hardware implementations of FTN

transceiverstransceivers

Primarily intended for OFDM based systems

At transmitter:

- Add-on blocks for efficient processing

At R i At Receiver:

- Iterative decoding to reduce interference from FTN symbols

2

Transmitter

FTN MapperOuter Encoder IFFTModulation Pulse Shaping

IOTA multicarrier modulation

IOTA reconstruction Rectangular reconstruction

IOTA multicarrier modulation

IOTA give better reconstruction than rectangular

LUT based architecture for a FTN mapper is implemented

and verified in hardware

IOTA = isotropic orthogonal transform algorithm

Receiver

Inverse IOTA Filter

Inverse FTN Mapper Outer DecoderFFT Inner Decoder -1

Results:Matlab model of an iterative decoder is developedPerformance MeasurementsHardware implementation is shown to be feasible

BER

Ongoing: Hardware architecture and implementationImprove receiver for fading channels

No compressionCompression 0.5

SNR

SVD Channel Estimator VR

Long Term Evolution (LTE)

MMSE estimators give good estimates but

High complexity

Idea:The energy are concentrated to the eigenvalues in the beginning

Only the first k eigenvalues are used

Presentation just

Motivation:SVD estimator with reduced complexitySame accuracy as MMSE, almost

Johan Löfgren

Presentation just after this one

Multibase an FP7 EU-project

Motivation:Scalable Multi tasking Baseband for Mobile Scalable Multi-tasking Baseband for Mobile Communications

ObjectivesMulti-tasking radio with concurrent data streamsScalable and reconfigurable multi-processors Specific focus on OFDM Standards, e.g. LTE and WI-FI

Start: July 2008Isael Diaz

802.11g/nLong Term Evolution (LTE)

3

Multi-base Functional Architecture

DigitalFront-End DecodingFFT Demodulation

Receiver

RF MAC

Time & Frequency

Synch.

Time & Frequency Tracking

Channel Estimation

LUND

Connected to SVD Channel

Estimator

DigitalFront-End CodingIFFT Modulation

Transmitter

RF MAC

Current Task in Digital ASIC Group

Current Task in Digital ASIC Group

Implementation of algorithms for multiple standards with concurrent support forstandards with concurrent support for

Synchronization Channel estimation

Silicon implementation of the architectureSilicon implementation of the architectureTapeout in March 2010

- LU, Ericsson, IMEC

Multiple Standard Synchronization

Types of SynchronizationPreamble detection (WI-FI)

Cyclic Prefix (CP) correlation (All)Cyclic Prefix (CP) correlation (All)

Preamble Signal Data

OFDM

CP Data CP

SymbolCopy

Results:1-bit sync. saves 90 % silicon

Reconfigurable Computing

Coarse-grained reconfigurable

MC

PC

PC

MC

MC

PC

PC

MC

R R

R

Vinnova/SoS

Coarse-grained reconfigurable

architecture

ASIC, FPGA and DSP alternative

A mesh of resource cells,

e.g. processing and memory cells

MC

PC

PC

MC

MC

PC

PC

MC

R R

R

Will be used in g g

Both local and global interconnections

Start: March 2009Chenxin Zhang

Will be used in Multibase as

well

4

Mapping of a Time-multiplexed FIR Filter

Memory: A FIFO for input data Z-1

h

Input bufferx(n) y(n)x

MAC

A ROM for filter coefficients

Self-synchronized

ROMControl reset

Input bufferMAC

yresource cells

Hence, no outer control needed

R

SROM

FIFOMAC

Coefficient ROM

MAC

Mapping of a 2048-point pipeline FFT

R-22

BF

29210

R-22

BF

2728

R-22

BF

2526

R-22

BF

2324

R-22

BF

2122 20

R-2BF

stage 1 stage 2 stage 3 stage 4 stage 5 stage 6

Mapped on an 8-by-8 reconfigurable cell array

SDFII-4

SDFII-3 DSP

BTFII

SDFII-1

SDFII-2

CORDIC

BTFI

SDFI-2

SDFI-1 DSP

BTFII

SDFII

ROM-1

CORDIC

ROM-3 DSP

ROM-2

ROM-4 DSP

DSP ROM-1

DSP

ROM-2

ROM-3

BTFI

DSP SDFI

R

R

R

DSP

R

CORDIC

MC

CORDIC

RR RR

R R

R

cell arrayBTF

I

SDFI DSP

BTFII ROM

SDFII

CORDIC

DSP

RAM

BTFII ROM

SDFII

CORDIC

ROM BTFII

CORDIC

SDFII

BTFI

DSP SDFI

ROM BTFII

CORDIC

SDFII

BTFI

DSP SDFI

R

R R

R

R

MC MC

DSP

MC MC

R

R R

R R

Presentation later today

Low Power Weak Inversion Radio

Ultra Portable Devices (UPD)An SSF project

UPD/SSF

RF Front-End DecodingDigital Baseband

Sigma Delta A-to-D

Converter

Antenna Interface

System level aspects

System Level Control

Two PhD projects in the Digital ASIC Group

AlternativesDigital DecodingAnalog before A-to-D conversionAnalog after digital baseband

Decoding in Weak Inversion UPD/SSF

Motivation:Ult l P

DigitalDigitalSigma Delta Antenna

D-to-A

Analog Decoding

Detection & Synch.

Analog Decoding

Alternative Decoding Approaches

Few Bits?

Ultra low Power Radio for medical applications, sensor networks, etc.

Digital DecodingRF Front-End

System Level Control

Digital Baseband

gA-to-D

Converter

Antenna Interface

Start: May 2009Reza Meraji

5

Size:Analog decoders use substantially

Why Analog Decoding?

)use substantially less die area

Suitability: Soft in/soft out C

hip

siz

e (u

m)

Algorithms use soft values in wireless channel decoding

Required SNR (dB)

Source: Christian Schlegel, Seminar Notes, 2005 ©

Power:Analog decoders

Why Analog Decoding?

(dB)

Analog decoders can consume 100 times less power

High Speed:

Req

uired

SN

R (

Limited by the settling time only

Power dissipation (mW)

Source: Christian Schlegel, Seminar Notes, 2005 ©

System view is important Previous work: only stand alone codersPrevious work: only simple codes

Challenges: Focus on System Aspects

Previous work: only simple codes

Parallel processing wanted: Limits the complexity to grow linearly with the coded data block size

Physical effects: Device mismatch, leakage, offset errors, etc. (65 nm)

The effects of device scaling on the analog decoder behavior is not clear enough

Digital Baseband in Weak InversionUPD/SSF

Motivation:Ultra low Power Radio for medical applications, sensor networks, etc. (in 65 nm)

Digital BasebandRF Front-End

System Level Control

DecodingSigma Delta

A-to-D Converter

Antenna Interface

Start: February 2009S. M. Yasser Sherazi

Ongoing:Sub-threshold characterizationArchitectures for digital baseband filtering

6

Digital Baseband in Weak Inversion

Gate oxide tunneling

Low leakage important

Junction BTBTJunction BTBT

Sub Threshold

Digital BasebandRF Front-End

System Level Control

DecodingSigma Delta

A-to-D Converter

Antenna Interface

Low leakage importantThree major sources of leakage

Normalized Average Leakage

1 2

VDD

12

14

Reverse Body Biasing – 65 nm

Sub-

Same VDD/GND

BTBT

1.0

0 50.7

1.2

I D (p

A)

12

4

10

6

8

threshold

Active

High V

BTBT

0.30.5

0.1

VBody Bias (V)1.00.6 0.80.40.20

2

0

Standby

Low GND

VDD

Energy Reduction Architectures VR/LU

MotivationEnergy reduction for low sample rate circuits

Connected to UPD

Architectural foldingA 6x6 matrix multiplication is folded by 3 and 6

HW reduction

Previously developed architecture tuned for sub-VT (pacemaker)

Joachim Rodrigues et. al.

Folding #Adder #Multiplier  Area [μm2] 

‐ 35 6 6794

3 25 2 3912

6 21 1 3456

Folded by 3

Sub-VT Operation Mode

Energy goes down with folding

C iti l Critical path speed

ner

gy

dis

sipat

ion

er c

lock

cyc

le (

pJ)

Fixed clock

Supply Voltage (V)

En

pe

7

Tapeout in 65 nm LL-HVT (High VT)

5 designsFolded 6 (1)Bit-serial (2)Parallel (3)(1) Parallel (3)Pipelined (4)Asynchronous (5)

Optimization techniques will be compared in sub-VT

N d l (EPFL)

(2)

(1)

(3)

New energy model (EPFL)270 times faster than SPICE, (average) With only 6% error in accuracy(4) (5)

Digital Design with Nano Wires

Motivation:High mobility

WWW/SSF

High mobilitySi - 1450 cm2/VsInAs 33000 cm2/Vs)

New geometrye geo et yWrap insulating gate

Start: January 2009Anil Dey

Nanowire Growth

Technology breakthrough for thin

Φ Down to 10 nm

breakthrough for thin nano wires

Makes circuit design feasible

Joint research: Solid State Physics & Circuit Design

Digital Circuitry

Circuitry designed with enhancement mode only

Inverter NOR-gate

Input A

Output GNDT1

T2

T2

VDD

Output Q

Input A

VDD

T1

GND

Input B

Layouts for mask sets

8

Transistor Dimensioning

Number of wires per transistorTypically up to 100 wires per transistoryp y p p

DiameterTypically 10 to 50 nm per transistor

G t l thGate lengthTypically 30 – 120 nm

Nano Wire Curve Fitting

Curve fitting on measured data

Good fitting using a model for

manual analysis

- Model: Shichman-Hodges +

velocity saturation compensation

Advanced model is

implemented in Cadence

Master’s ThesisMartin Berg & Kristofer Jansson

Parabolic Synthesis Architecture

Motivation: Approximate

The hardware architecture is based on second order parabolic

ppUnary functions, e.g. Sine, Cosine

Multiplication of sub-functions

Parallel

order parabolic functions

Parallel architecture: High throughput

Erik Hertz

SineApprox.

Parabolic Synthesis

Results: Architecture for unary functions such as

CharacteristicsHigh accuracy with a minimum of arithmetic su as

Sine CosineTangentArcsineArccosine Arctangent

operations

Short latency: Feasible for beam forming, compared to e.g. CORDIC

LogarithmExponentialDivisionSquare root

9

The Digital ASIC Group

Peter Nilsson- Professor Digital

Viktor Öwall- Associate Professor

Joachim Rodrigues- Assistant Professor

g Baseband

New

New

New

New New

Weak Inversion Baseband

OFDM Faster-than-Nyquist

MIMO-OFDM Channel

EstimationOFDM Multi-tasking RadioWeak

Inversion Decoding

Bea

mfo

rmin

g ...

Mats Torkelson- Adjunct Researcher

8 Ph.D. Students

Nanowires for Digital Design

Weak Inversion

Architectures

Parabolic Synthesis

Recon-figurable

Computing