Major Finaldoc With Correction

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1. INTRODUCTION

1.1 INTRODUCTION:

In the VLSI design timing, power, area are the three major constraints.

Optimizations in VLSI have been done on three factors: Area, Power and iming

!Speed". Area optimization means red#cing the space of $ogic which occ#p% on the

die. his is done in both front&end and bac'&end of design. In front&end design, proper

description of simp$ified (oo$ean e)pression and removing #n#sed states wi$$ $ead to

minimize the gate*transistor #ti$ization. Partition, +$oor p$anning, P$acement, and

ro#ting are perform in bac'&end of the design which is done b% A- too$. he A-

too$ have a specific a$gorithm for each process to prod#ce an area efficient design

simi$ar to Power optimization. Power optimization is to red#ce the power dissipation

of the design which s#ffers b% operating vo$tage, operating fre#enc%, and switching

activit%. he first two factors are mere$% specified in design constraints b#t switching

activit% is a parameter which varies d%namica$$%, based on the wa% which designs the

$ogic and inp#t vectors. iming optimization refers to meeting the #ser constraints in

efficient manner witho#t an% vio$ation otherwise, improving performance of the

design. /igh performance designs are achieved b% proper p$acement, ro#ting andsizing the e$ement. he word optimization is approached in different wa%s b%

merging, instead of sizing the memor% e$ement.

0#$tip$ication in hardware can be imp$emented in two wa%s either b% #sing more

hardware for achieving fast e)ec#tion or b% #sing $ess hardware and end #p with s$ow

e)ec#tion. he area and speed of the m#$tip$ier is an important iss#e, increment in

speed res#$ts in $arge area cons#mption and vice versa. 0#$tip$iers p$a% vita$ ro$e in

most of the high performance s%stems. Performance of a s%stem depend to a great

e)tent on the performance of m#$tip$ier th#s m#$tip$iers sho#$d be fast and cons#me

$ess area and hardware. his idea forced #s to st#d% and review abo#t the m#$tip$iers

speed, power cons#mption and Area occ#pied. (e$ow are three famo#s 0#$tip$iers

And their drawbac's name$%

• 1a$$ace ree 0#$tip$ier

• Arra% 0#$tip$ier

• (ooth 0#$tip$ier

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1. Wallace tree multiplier:

A Wallace tree is an efficient hardware imp$ementation of a digita$ circ#it that

m#$tip$ies two integers, devised b% A#stra$ian omp#ter Scientist hris 1a$$ace in

2345.

he 1a$$ace tree has three steps:

2. 0#$tip$% !that is & A6-" each bit of one of the arg#ments, b% each bit of the

other, %ie$ding res#$ts. -epending on position of the m#$tip$ied bits, the wires

carr% different weights, for e)amp$e wire of bit carr%ing res#$t of is 78 !see

e)p$anation of weights be$ow".

8. 9ed#ce the n#mber of partia$ prod#cts to two b% $a%ers of f#$$ and ha$f adders.

7. ro#p the wires in two n#mbers, and add them with a conventiona$ adder .

he second phase wor's as fo$$ows. As $ong as there are three or more wires with the

same weight add a fo$$owing $a%er:

• a'e an% three wires with the same weights and inp#t them into a f#$$ adder . he

res#$t wi$$ be an o#tp#t wire of the same weight and an o#tp#t wire with a higher

weight for each three inp#t wires.

• If there are two wires of the same weight $eft, inp#t them into a ha$f adder .

• If there is j#st one wire $eft, connect it to the ne)t $a%er.

he benefit of the 1a$$ace tree is that there are on$% red#ction $a%ers, and

each $a%er has propagation de$a%. As ma'ing the partia$ prod#cts is and

the fina$ addition is , the m#$tip$ication is on$% , not m#ch

s$ower than addition !however, m#ch more e)pensive in the gate co#nt". 6aive$%

adding partia$ prod#cts with reg#$ar adders wo#$d re#ire time. +rom

a comp$e)it% theoretic perspective, the 1a$$ace tree a$gorithm p#ts m#$tip$ication in

the c$ass .

2

http://en.wikipedia.org/wiki/Computational_complexity_theoryhttp://en.wikipedia.org/wiki/Computer_hardwarehttp://en.wikipedia.org/wiki/Computer_hardwarehttp://en.wikipedia.org/wiki/Computer_hardwarehttp://en.wikipedia.org/wiki/Chris_Wallace_(computer_scientist)http://en.wikipedia.org/wiki/Adder_(electronics)http://en.wikipedia.org/wiki/Full_adderhttp://en.wikipedia.org/wiki/Half_adderhttp://en.wikipedia.org/wiki/Computational_complexity_theoryhttp://en.wikipedia.org/wiki/Computational_complexity_theoryhttp://en.wikipedia.org/wiki/Computer_hardwarehttp://en.wikipedia.org/wiki/Chris_Wallace_(computer_scientist)http://en.wikipedia.org/wiki/Adder_(electronics)http://en.wikipedia.org/wiki/Full_adderhttp://en.wikipedia.org/wiki/Half_adderhttp://en.wikipedia.org/wiki/Computational_complexity_theoryhttp://en.wikipedia.org/wiki/Computational_complexity_theory


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hese comp#tations on$% consider gate de$a%s and don;t dea$ with wire de$a%s, which

can a$so be ver% s#bstantia$.

he 1a$$ace tree can be a$so represented b% a tree of 7*8 or 5*8 adders.

It is sometimes combined with (ooth encoding.

Fig 1.1 Weights

he weight of a wire is the radi) !to base 8" of the digit that the wire carries. In

genera$, < have inde)es of and = and since the weight

of is .

Fig: 1.2 Pattern

>)amp$e:

, m#$tip$%ing b% :

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http://en.wikipedia.org/wiki/Gate_delayhttp://en.wikipedia.org/wiki/Gate_delayhttp://en.wikipedia.org/wiki/Booth_encodinghttp://en.wikipedia.org/wiki/Radixhttp://en.wikipedia.org/wiki/Gate_delayhttp://en.wikipedia.org/wiki/Booth_encodinghttp://en.wikipedia.org/wiki/Radix


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2. +irst we m#$tip$% ever% bit b% ever% bit:

• weight 2 &

• weight 8 & ,

• weight 5 & , ,

• weight ? & , , ,

• weight 24 & , ,

• weight 78 & ,

• weight 45 &

8. 9ed#ction $a%er 2:

• Pass the on$% weight&2 wire thro#gh, o#tp#t: 2 weight&2 wire

• Add a ha$f adder for weight 8, o#tp#ts: 2 weight&8 wire, 2 weight&5 wire

• Add a f#$$ adder for weight 5, o#tp#ts: 2 weight&5 wire, 2 weight&? wire

• Add a f#$$ adder for weight ?, and pass the remaining wire thro#gh, o#tp#ts: 8 weight&

? wires, 2 weight&24 wire

• Add a f#$$ adder for weight 24, o#tp#ts: 2 weight&24 wire, 2 weight&78 wire

• Add a ha$f adder for weight 78, o#tp#ts: 2 weight&78 wire, 2 weight&45 wire

• Pass the on$% weight&45 wire thro#gh, o#tp#t: 2 weight&45 wire

7. 1ires at the o#tp#t of red#ction $a%er 2:

• weight 2 & 2

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• weight 8 & 2

• weight 5 & 8

• weight ? & 7

• weight 24 & 8

• weight 78 & 8

• weight 45 & 8

5. 9ed#ction $a%er 8:

• Add a f#$$ adder for weight ?, and ha$f adders for weights 5, 24, 78, 45

@. O#tp#ts:

• weight 2 & 2

• weight 8 & 2

• weight 5 & 2

• weight ? & 8

• weight 24 & 8

• weight 78 & 8

• weight 45 & 8

• weight 28? & 2

4. ro#p the wires into a pair integers and an adder to add them.

Drawac!:

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annot be imp$emented effective$% on +PA

Power cons#mption is /igh

omp$e)it% is /igh

"rra# $ultiplier:

-igita$ m#$tip$ication entai$s a se#ence of additions carried o#t on partia$ prod#cts.

Fig: 1.%

In Arra% m#$tip$ier partia$ prod#cts are independent$% comp#ted in para$$e$.Let #s

consider two binar% n#mbers A and ( of m and n bits respective$%,

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Fig: 1.&

here are mn s#mmands that are prod#ced in para$$e$ b% a set of mn n#mbers of

A6-gates.

If m ' n hen it wi$$ re#ire n(n)2* f#$$ adders, n ha$f&adders and n+n A6- gates and

worst case de$a% wo#$d be (2n,1*t- .where td is the time de$a% of gates

asic cell /0 a parallel arra# multiplier:

Fig: 1.

"rra# structure /0 parallel multiplier:

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Fig: 1.

onsider comp#ting the prod#ct of two 5&bit integer n#mbers given b% A7A8A2AB

!m#$tip$icand" and (7(8(2(B !m#$tip$ier". he prod#ct of these two n#mbers can be

formed as shown be$ow.

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Fig: 1.3

>ach of the A6-ed terms is referred to as a partia$ prod#ct. he fina$ prod#ct !the

res#$t" is formed b% acc#m#$ating !s#mming" down each co$#mn of partia$ prod#cts.

An% carries m#st be propagated from the right to the $eft across the co$#mns.

Since we are dea$ing with binar% n#mbers, the partia$ prod#cts red#ce to simp$e A6-

operations between the corresponding bits in the m#$tip$ier and m#$tip$icand. he

s#ms down each co$#mn can be imp$emented #sing one or more 2&bit binar% adders.

An% adder that ma% need to accept a carr% from the right m#st be a f#$$ adder. If there

is no possibi$it% of a carr% propagating in from the right, then a ha$f adder can be #sed

instead, if desired !a f#$$ adder can a$wa%s be #sed to imp$ement a ha$f adder if the

carr%&in is tied $ow". he diagram be$ow i$$#strates a combinationa$ circ#it for

performing the 5)5 binar%m#$tip$ication.

he initia$ $a%er of A6- gates forms the si)teen partia$ prod#cts that res#$t from

A6-ing a$$ combinations of the fo#r m#$tip$ier bits with the fo#r m#$tip$icand bits.

he co$#mn s#ms are formed #sing a combination of ha$f and f#$$ adders. Loo' again

at the first two i$$#strations of the binar% m#$tip$ication process above, and ma'e a

caref#$ comparison with the fig#re be$ow.

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Fig: 1.4

he adder b$oc's !indicated b% +A and /A" in the fig#re above are drawn in s#ch a

wa% that the two bits to be added enter from the top, an% carr% in from the right enters

from the right, and an% carr% o#t e)its from the $eft of each b$oc'. he o#tp#t from the

bottom of a b$oc' is the s#m.

he $east significant o#tp#t bit, SB !the first co$#mn", invo$ves on$% two inp#t bits and

is comp#ted as the simp$e o#tp#t of an A6- gate.

he ne)t o#tp#t bit, S2, invo$ves the s#m of two partia$ prod#cts. A ha$f adder is #sed

to form the s#m since there can be no carr% in from the first co$#mn.

he third o#tp#t bit, S8, is formed from the s#m of three !2&bit" partia$ prod#cts p$#s a

possib$e carr% in from the previo#s bit. his operation re#ires two cascaded adders

!one ha$f adder and one f#$$ adder" to s#m the fo#r possib$e inp#t bits !three partia$

prod#cts and one possib$e carr% in from the right".

he remaining o#tp#t bits are formed simi$ar$%. (eca#se in some co$#mns we m#st

add more than two binar% n#mbers, there ma% be more than one carr% o#t generated to

the $eft.

Drawac!s:

Low speed

0ore Area

0ore power

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//th5s $ultiplier:

(oothCs A$gorithm is a smart move for m#$tip$%ing signed n#mbers. It initiate with the

abi$it% to both add and s#btract there are m#$tip$e wa%s to comp#te a prod#ct .

(oothCs a$gorithm is a m#$tip$ication a$gorithm that #ti$izes twoCs comp$ement

notation of signed binar% n#mbers for m#$tip$ication . >ar$ier m#$tip$ication was in

genera$ imp$emented via se#ence of addition then s#btraction, and then shift

operations. 0#$tip$ication can be we$$ tho#ght&o#t as a series of repeated additions.

he n#mber which is to be added is 'nown as the m#$tip$icand, and the n#mber of

times it is added is 'nown as the m#$tip$ier, and the res#$t we get is the m#$tip$ication

res#$t. After >ach step of addition a partia$ prod#ct is generated. 1hen the operands

are integers, the prod#ct in genera$ is twice the $ength of operands in order to protect

the information content. his repetitive addition method that is recommended b% the

arithmetic definition is s$ow as it is a$wa%s rep$aced b% an a$gorithm that ma'es #se of

positiona$ depiction. 1e can decompose m#$tip$iers into two parts. he first part is

committed to the generation of partia$ prod#cts, and the second part co$$ects and then

adds them. he f#ndamenta$ m#$tip$ication princip$e is twofo$d i.e. eva$#ation of

partia$ prod#cts and gathering of the shifted partia$ prod#cts. It is performed b% the

consec#tive additions of the co$#mns of the shifted partia$ prod#ct matri).

he de$a%ed, gated case of the m#$tip$icand m#st a$$ be in the same co$#mn of the

shifted partia$ prod#ct matri). hen the% are added to form the prod#ct bit for the

partic#$ar form. 0#$tip$ication is th#s a m#$ti operand operation. o e)pand the

m#$tip$ication to both signed and #nsigned n#mbers, a s#itab$e n#mber s%stem wo#$d

be the depiction of n#mbers in twoCs comp$ement format.

$U6TIP6IC"TION "67ORIT8$:

A circ#it that m#$tip$ies two #nsigned n bit binar% n#mbers, #ses a 8 dimensiona$

arra% of identica$ s#bcirc#its. >ach of which contains a f#$$ adder and an Dand gate.‖

+or $arge n#mber of bits this approach ma% not be appropriate beca#se of the $arge

n#mber of gates needed. Another approach is to #se shift register in combination with

an adder to imp$ement the traditiona$ method of m#$tip$ication.

PEB= +or iEB to n&2 do If biE2 then

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PEPFA= >nd if= Left shift A=

>nd for=

Fig:1.9

Signed m#$tip$ication is a vigi$ant process. hro#gh #nsigned m#$tip$ication there is

no need to ta'e the sign of the n#mber into consideration. >ven tho#gh in signed

m#$tip$ication the same proced#re cannot be app$ied for the reason that the signed

n#mber is in a 8Cs comp$iment form which wo#$d give in an inacc#rate res#$t if

m#$tip$ied in an ana$ogo#s manner to #nsigned m#$tip$ication . h#s here (oothCs

a$gorithm comes in. (oothCs a$gorithm conserves the sign of the end res#$t. 1hi$e

doing m#$tip$ication, strings of Bs in the m#$tip$ier ca$$ for on$% shifting. 1hi$e doing

m#$tip$ication, strings of 2s in the m#$tip$ier need an operation on$% at each end. 1e

re#ire to add or s#btract mere$% at positions in the m#$tip$ier where there is a switch

from B to 2 or from 2 to B. In the fo$$owing f$ow chart we have, bE0#$tip$ier,

aE0#$tip$icand, mE Prod#ct . 6ow here we wi$$ re#ire twice as man% bits in o#r prod#ct as we a$read% have in o#r two operands. he $eftmost bit of o#r operands of

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both the m#$tip$icand and the m#$tip$ier is a$wa%s a sign bit, and canCt be #sed as part

of the va$#e. hen choose which operand wi$$ be m#$tip$ier and which wi$$ be

m#$tip$icand. If one operand and both are negative then the% are represented in two;s

comp$ement form. Start in on with a prod#ct that consists of the m#$tip$ier in the

compan% of an additiona$ G $eading zero bits. 6ow chec' the LS( and the previo#s

LS( of prod#ct to find o#t the arithmetic action. Add B as the previo#s LS( if it is the

+I9S pass. Probab$e arithmetic actions are if: BB:& no arithmetic operation is

performed on$% shifting is done. B2:& add m#$tip$icand to $eft ha$f part of prod#ct and

then shifting is done. 2B:& s#btract m#$tip$icand from $eft ha$f part of prod#ct and then

shifting is performed 22:& no arithmetic operation is performed on$% shifting is

;ample :

0#$tip$% 2B b% &H #sing @&bit n#mbers !2B&bit res#$t". 2B in binar% is B2B2B &2B in

binar% is 2B22B !th#s now we can add 2B22B when we need to s#btract m#$tip$icand"

&H in binar% is 22BB2 O#r e)pected res#$t sho#$d be !&HB" in binar% !222B2 22B2B".

Steps of a$gorithm are:

Step2:

!BBBBB 22BB2 B" now as $ast two bits are 2B so here BBBBBF2B22BE2B22B. 6ow we

get !2B22B 22BB2 B" now b% A9S !arithmetic right shift" we get !22B22 B22BB 2".

Step8:

as $ast two bits are B2 so, 22B22FB2B2BEBB2B2!carr% is ignored as beca#se addition

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as $ast two bits are 22, there is no change on$% A9S wi$$ ta'e p$ace, now we wi$$ get

!222B2 22B2B 2".

Step 4:

now ignoring the $ast bit we wi$$ get o#r prod#ct that is !222B2 22B2B" E &HB

Drawac!s:

0ost omp$e) A$gorithm

rade off (etween Speed and Area

Parameter "rra# multiplier Wallace tree

multiplier

//th multiplier

Operati/n spee- Less /igh /ighest

Time -ela# 0ore 0edi#m Less

"rea 0ore area 0edi#m 0inim#m

C/mple;it# $ess 0ore 0ost

P/wer c/nsumpti/n 0ost 0ore Less

These Drawac!s can e /


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a$gorithm , the #adratic resid#e n#mber s%stem!96S" , and recent$%, the red#ndant

comp$e) n#mber s%stem !96S" .($ah#t etc. A$$ proposed a techni#e for comp$e)

n#mber m#$tip$ication, where the a$gebraictransformation was #sed. his a$gebraic

transformationsaves one rea$ m#$tip$ication, at the e)pense of three additions as

compared to the direct method imp$ementation. A $eft to right arra% for the fast

m#$tip$ication has been reported in 8BB@, and the method is not f#rther e)tended

forcomp$e) m#$tip$ication. (#t, a$$ the above techni#esre#ire either $arge overhead

for pre*post processing or$ong $atenc%. +#rther man% design iss#es $i'e as

speed,acc#rac%, design overhead, power cons#mption etc., sho#$dnot be addressed for

fast m#$tip$ication .In a$gorithmicand str#ct#ra$ $eve$s, a $ot of m#$tip$ication

techni#es hadbeen deve$oped to enhance the efficienc% of the m#$tip$ier=which

enco#nters the red#ction of the partia$ Prod#ctsand*or the methods for their partia$

prod#cts addition ,b#tthe princip$e behind m#$tip$ication was same in a$$ cases. Vedic

0athematics is the ancient s%stem of Indianmathematics which has a #ni#e

techni#e of ca$c#$ationsbased on 24 S#tras !+orm#$ae". JKrdhva&tir%a'b%hamJ is a

Sans'rit word means vertica$$% and crosswise form#$a is#sed for fast 0#$tip$ication

A$$ these form#$as are adopted from ancient Indian Vedic 0athematics. In this wor'

we form#$ate this mathematics for designing the comp$e) m#$tip$ier architect#re in

transistor $eve$ with two c$ear goa$s in mind s#ch as: i" Simp$icit% and

mod#$arit%m#$tip$ications for VLSI imp$ementations and ii" hee$imination of carr%

propagation for rapid additions and s#btractions. 0ehta et a$.have been proposed a

m#$tip$ier design #sing JKrdhva&tir%a'b%hamJ s#tras, which was adopted from the

Vedas. he form#$ation #singthis s#tra is simi$ar to the modern arra% m#$tip$ication,

which a$so indicating the carr% propagation iss#es. 0#$tip$ier imp$ementation in the

gate $eve$!+PA" #sing Vedic 0athematics has a$read% been

reported b#t to the best of o#r 'now$edge ti$$ date there isno report on transistor

$eve$!ASI" imp$ementation of s#chcomp$e) m#$tip$ier. (% emp$o%ing the Vedic

mathematics, an 6 bit comp$e) n#mber m#$tip$ication was transformedinto fo#r

m#$tip$ications for rea$ and imaginar% terms of the fina$ prod#ct. In this paper we

report on a nove$ high speed comp$e) m#$tip$ier design #sing ancient Indian

Vedicmathematics.

The sutras of vedic mathematics with their meanings are listed inthe tale elow!

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"#$o "%T&' $'() ()'$*$+

1 ,An#r#p%e"&Sh#n%aman%ath# *f one value is in ratio- other is.ero

2 /halanaalanaham ierences and similarities

3 )adhiina)anunenaurvena

one more or less than therevious

one4 +unaasamuchhah actors of the sum is e:ual to

sum5 +uniitasamuchhah The roduct of the sum is

e:ual to sum6 $iilam$avatashcaramam (an from 9- efore 10

7 aravarta;oTiraham =erticall crosswise

14 =ashtisamanstih art and ?hole

15 ;aavadunam ?hatever the e@tent of its

deAcienc

Tale1! sutras of vedic mathematics

1.3 MATHEMATICAL FORMULATION OF VEDIC MATHS

he gifts of the ancient Indian mathematics in the wor$d histor% of mathematica$

science are not we$$ recognized.he contrib#tions of saint and mathematician in the

fie$d of n#mber theor%, ;Sri (haratirsnahirthaji 0aharaja;, in the form of Vedic

S#tras !form#$as" are significant forca$c#$ations. /e had e)p$ored the mathematica$

potentia$sfrom Vedic primers and showed that the mathematica$operations can be

carried o#t menta$$% to prod#ce fastanswers #sing the S#tras. Vedic 0athematics is

the ancient s%stem ofIndian mathematics which has a #ni#e techni#e of ca$c#$ations

based on 24 S#tras !+orm#$ae". JKrdhvatir%a'b%hamJ is a Sans'rit word means

vertica$$% andcrosswise form#$a is #sed for sma$$er n#mber m#$tip$ication. form#$a is

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#sed for $arge n#mber m#$tip$ication ands#btraction. A$$ these form#$as are adopted

from ancient Indian Vedic 0athematics.

1.& PROPO>D $U6TIP6IR "RC8ITC8UR D>I7N -esign +actors of 0#$tip$ication:

Latenc%, thro#ghp#t, area, and design comp$e)it% are the important factors to choose a

s#itab$e design for the re#irement. Latenc% is a meas#re of how $ong the inp#ts to a

device are stab$e #nti$ the fina$ res#$t avai$ab$e on o#tp#ts. hro#ghp#t is the meas#re

of how man% m#$tip$ications can be performed in a given period of time.

Krdhva ir%a'bh%am S#tra he basic S#tras and Krdhva ir%a'bh%am S#tra in the

Vedic 0athematics he$ps to do a$most a$$ the n#meric comp#tations in eas% and fast

manner. he S#tra which we emp$o% in this project is Krdhva ir%a'bh%am

!0#$tip$ication"

Descripti/n /0 >utra:

his is the genera$ form#$a app$icab$e to a$$ cases of m#$tip$ication . Krdhva

ir%a'bh%am means MVertica$$% and rosswiseN, which is the method of

m#$tip$ication fo$$owed.

I$$#stration:

Fig: 1.1? 2 it multiplicati/n # Ur-h


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Fig: 1.11 % it multiplicati/n # using Ur-h


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Design /0 &@& l/c! :

he design of 55 b$oc' is a simp$e arrangement of 88 b$oc's in an optimized

manner. he first step in the design of 55 b$oc' wi$$ be gro#ping the 8 bit of each 5

bit inp#t. hese pair terms wi$$ form vertica$ and crosswise prod#ct terms. >ach inp#t

bit&pair is hand$ed b% a separate 88 Vedic the schematic of a 55 b$oc' designed

#sing 88 b$oc's. he partia$ prod#cts represent the Krdhva vertica$ and cross prod#ct

terms. hen first two bits of right most 8)8 vedic m#$tip$ier o#tp#t wi$$ be send

direct$% to o#tp#t first two bits. 9emaining partia$ prod#cts wi$$ be hand$ed b% 5 (it

and 4 (it Adders as shown in the fig#re.

Fig:1.1% &;& =e-ic $ultiplier

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Design /0 4;4 =e-ic $ultiplier:

he design of ?? b$oc' is a simi$ar arrangement of 55 b$oc's in an optimized

manner . he first step in the design of ?? b$oc' wi$$ be gro#ping the 5 bit !nibb$e"

of each ? bit inp#t. hese #adr#p$e terms wi$$ form vertica$ and crosswise prod#ct

terms. >ach inp#t bit&#adr#p$e is hand$ed b% a separate 55 Vedic m#$tip$ier to

prod#ce partia$ prod#ct rows. hen first fo#r bits of right most 5)5 vedic m#$tip$ier

wi$$ be send to o#tp#t direct$% other bits are hand$ed with ?(it and 28 (it adders

respective$% as shown. he fig#re shows the schematic of an ?? b$oc' designed

#sing 55 b$oc's. he partia$ prod#cts represent the Krdhva vertica$ and cross prod#ct

terms.

Fig 1.1& 4;4 =e-ic $ultiplier

Design /0 a 1@1 $ultiplier

he design of 2424 b$oc' is a simi$ar arrangement of ?? b$oc's in an optimized

manner as in fig#re. he first step in the design of 2424 b$oc' wi$$ be gro#ping the ?

bit !b%te" of each 24 bit inp#t. hese $ower and #pper b%tes pairs of two inp#ts wi$$

form vertica$ and crosswise prod#ct terms. >ach inp#t b%te is hand$ed b% a separate

?? Vedic m#$tip$ier to prod#ce si)teen partia$ prod#ct rows. hen first ? (its of right

most m#$tip$ier o#tp#t are direct$% send to the o#tp#t then other bits are hand$ed b%

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85 (it and 24 (it Adders.

Fig: 1.1 1 it $ultiplier

2. >OFTW"R RAUIR$NT>

2.1 BI6INB:

Gi$in), Inc. is an American techno$og% compan%, primari$% a s#pp$ier of

programmab$e $ogic devices. It is 'nown for inventing the fie$d programmab$e gate

arra%!+PA" and as the first semicond#ctorcompan% with a fab$essman#fact#ring

mode$.

Gi$in) designs, deve$ops and mar'ets programmab$e $ogic prod#cts, inc$#ding

integrated circ#its !Is", software design too$s, predefined s%stem f#nctions de$ivered

as inte$$ect#a$ propert% !IP" cores, design services, c#stomer training, fie$d

engineering and technica$ s#pport. Gi$in) se$$s both +PAs and PL-s for e$ectronic

e#ipment man#fact#rers in end mar'ets s#ch as comm#nications, ind#stria$,

cons#mer , a#tomotive and data processing.

2.2BI6INB)I>:

Bilin; I> !Integrated >oftware nvironment" is a software too$ prod#ced b%

Gi$in) for s%nthesis and ana$%sis of /-L designs, enab$ing the deve$oper to

s%nthesize !Jcompi$eJ" their designs, perform timing ana$%sis, e)amine 9L

diagrams, sim#$ate a design;s reaction to different stim#$i, and config#re the target

device with the programmer .

21

http://en.wikipedia.org/wiki/Programmable_logic_devicehttp://en.wikipedia.org/wiki/Field_programmable_gate_arrayhttp://en.wikipedia.org/wiki/Field_programmable_gate_arrayhttp://en.wikipedia.org/wiki/Semiconductorhttp://en.wikipedia.org/wiki/Companyhttp://en.wikipedia.org/wiki/Fablesshttp://en.wikipedia.org/wiki/Manufacturinghttp://en.wikipedia.org/wiki/Communicationshttp://en.wikipedia.org/wiki/Industryhttp://en.wikipedia.org/wiki/Consumerhttp://en.wikipedia.org/wiki/Automotivehttp://en.wikipedia.org/wiki/Data_processinghttp://en.wikipedia.org/wiki/Xilinxhttp://en.wikipedia.org/wiki/Hardware_description_languagehttp://en.wikipedia.org/wiki/Logic_synthesishttp://en.wikipedia.org/wiki/Static_timing_analysishttp://en.wikipedia.org/wiki/Register_transfer_levelhttp://en.wikipedia.org/wiki/Programmer_(hardware)http://en.wikipedia.org/wiki/Programmable_logic_devicehttp://en.wikipedia.org/wiki/Field_programmable_gate_arrayhttp://en.wikipedia.org/wiki/Field_programmable_gate_arrayhttp://en.wikipedia.org/wiki/Semiconductorhttp://en.wikipedia.org/wiki/Companyhttp://en.wikipedia.org/wiki/Fablesshttp://en.wikipedia.org/wiki/Manufacturinghttp://en.wikipedia.org/wiki/Communicationshttp://en.wikipedia.org/wiki/Industryhttp://en.wikipedia.org/wiki/Consumerhttp://en.wikipedia.org/wiki/Automotivehttp://en.wikipedia.org/wiki/Data_processinghttp://en.wikipedia.org/wiki/Xilinxhttp://en.wikipedia.org/wiki/Hardware_description_languagehttp://en.wikipedia.org/wiki/Logic_synthesishttp://en.wikipedia.org/wiki/Static_timing_analysishttp://en.wikipedia.org/wiki/Register_transfer_levelhttp://en.wikipedia.org/wiki/Programmer_(hardware)


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ISim provides a comp$ete, f#$$&feat#red /-L sim#$ator integrated within IS>.

/-L sim#$ation now can be an even more f#ndamenta$ step within %o#r design f$ow

with the tight integration of the ISim within %o#r design environment.

I>im e# Features:

• 0i)ed $ang#age s#pport

• S#pports V/-L&37 and Veri$og 8BB2

• 6o specia$ $icense re#irements

• 0#$ti&hreaded compi$ation

• Post&Processing capabi$ities

• Standa$one 1aveform viewing capabi$ities

• -eb#g capabi$ities

• 1aveform tracing, waveform viewing, /-L so#rce deb#gging

• 0emor% >ditor for viewing and deb#gging memor% e$ements

• Sing$e c$ic' re&compi$e and re&$a#nch of sim#$ation

• Integrated with IS> -esign S#ite and P$anAhead app$ication

• >as% to #se & One&c$ic' compi$ation and sim#$ation

• Additiona$ mapping or compi$ation not re#ired.

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%. 8"RDW"R RAUIR$NT>

%.1 >P"RT"N %:

he Spartan&7 fami$% of +ie$d&Programmab$e ate Arra%s is specifica$$%

designed to meet the needs of high vo$#me, cost&sensitive cons#mer e$ectronic

app$ications. he eight&member fami$% offers densities ranging from @B,BBB to

@,BBB,BBB s%stem gates. he Spartan&7 fami$% is a s#perior a$ternative to mas'

programmed ASIs. +PAs avoid the high initia$ cost, the $ength% deve$opment

c%c$es, and the inherent inf$e)ibi$it% of conventiona$ ASIs. A$so, +PA

programmabi$it% permits design #pgrades in the fie$d with no hardware rep$acement

necessar%, an impossibi$it% with ASIs.

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%.1.1 "rchitectural Oach IO( s#pports bidirectiona$ data f$ow p$#s

7&state operation. went%&si) different signa$ standards, inc$#ding eight high&

performance differentia$ standards, are avai$ab$e as shown in ab$e 8. -o#b$e

-ata&9ate !--9" registers are inc$#ded. he -igita$$% ontro$$ed Impedance

!-I" feat#re provides a#tomatic on&chip terminations, simp$if%ing board

designs.

($oc' 9A0 provides data storage in the form of 2?&bit d#a$&port b$oc's.

0#$tip$ier b$oc's accept two 2?&bit binar% n#mbers as inp#ts and ca$c#$ate the

prod#ct.

-igita$ $oc' 0anager !-0" b$oc's provide se$f&ca$ibrating, f#$$% digita$

so$#tions for distrib#ting, de$a%ing, m#$tip$%ing, dividing, and phase shifting

c$oc' signa$s.

hese e$ements are organized as shown in +ig#re 2. A ring of IO(s s#rro#nds

a reg#$ar arra% of L(s. he G7S@B has a sing$e co$#mn of b$oc' 9A0

embedded in the arra%. hose devices ranging from the G7S8BB to the

G7S8BBB have two co$#mns of b$oc' 9A0. he G7S5BBB and G7S@BBB

devices have fo#r 9A0 co$#mns. >ach co$#mn is made #p of severa$ 2?&bit

9A0 b$oc's= each b$oc' is associated with a dedicated m#$tip$ier. he -0s

are positioned at the ends of the o#ter b$oc' 9A0 co$#mns.

he Spartan&7 fami$% feat#res a rich networ' of traces and switches that

interconnect a$$ five f#nctiona$ e$ements, transmitting signa$s among them.

>ach f#nctiona$ e$ement has an associated switch matri) that permits m#$tip$e

connections to the ro#ting.

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Fig %.1>partan)% Famil# "rchitecture

%.1.2 C/n0igurati/n:

Spartan&7 +PAs are programmed b% $oading config#ration data into rob#st

reprogrammab$e static 0OS config#ration $atches !Ls" that co$$ective$% contro$

a$$ f#nctiona$ e$ements and ro#ting reso#rces. (efore powering on the +PA,

config#ration data is stored e)terna$$% in a P9O0 or some other nonvo$ati$e medi#m

either on or off the board. After app$%ing power, the config#ration data is written tothe +PA #sing an% of five different modes: 0aster Para$$e$, S$ave Para$$e$, 0aster

Seria$, S$ave Seria$, and (o#ndar% Scan !QA". he 0aster and S$ave Para$$e$

modes #se an ?&bit&wide Se$ect0AP port.

he recommended memor% for storing the config#ration data is the $ow&cost Gi$in)

P$atform +$ash P9O0 fami$%, which inc$#des the G+BBS P9O0s for seria$

config#ration and the higher densit% G+BBP P9O0s for para$$e$ or seria$

config#ration.

%.2 P"C"7 $"RIN7:

+ig#re 5.8 shows the top mar'ing for Spartan&7 +PAs in the #ad&f$at

pac'ages.he M@N and M5IN part combinations ma% be d#a$ mar'ed as M@*5IN.

-evices with the d#a$ mar' can be #sed as either &@ or &5I devices. -evices with a

sing$e mar' are on$% g#aranteed for the mar'ed speed grade and temperat#re range.

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`

&. "PP6IC"TION>

&.1The Implementati/n /0 =e-ic "lg/rithms in Digital >ignal

Pr/cessing

Digital signal pr/cessing !-SP" is the techno$og% that is omnipresent in a$most ever%

>ngineering discip$ine. It is a$so the fastest growing techno$og% this cent#r% and,

therefore, it poses tremendo#s cha$$enges to the engineering comm#nit%. +aster

additions and m#$tip$ications are of e)treme importance in -SP for convo$#tion,

discrete +o#rier transforms digita$ fi$ters, etc. he core comp#ting process is a$wa%s a

m#$tip$ication ro#tine= therefore, -SP engineers are constant$% $oo'ing for new

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`

a$gorithms and hardware to imp$ement them. Vedic mathematics is the name given to

the ancient s%stem of mathematics, which was rediscovered, from the Vedas between

2322 and 232? b% Sri (harati rishna irthaji. he who$e of Vedic mathematics is

based on 24 s#tras !word form#$ae" and manifests a #nified str#ct#re of mathematics.

As s#ch, the methods are comp$ementar%, direct and eas%. he a#thors high$ight the

#se of m#$tip$ication process based on Vedic a$gorithms and its imp$ementations on

?B?@ and ?B?4 microprocessors, res#$ting in appreciab$e savings in processing time.

he e)p$oration of Vedic a$gorithms in the -SP domain ma% prove to be e)treme$%

advantageo#s. >ngineering instit#tions now see' to incorporate research&based st#dies

in Vedic mathematics for its app$ications in vario#s engineering processes. +#rther

research prospects ma% inc$#de the design and deve$opment of a Vedic -SP chip

#sing VLSI techno$og%.

&.2Discrete F/urier Trans0/rm (DFT* # using =e-ic $athematics

he Vedic mathematica$ methods s#ggested b% Shan'arachar%a Sri. (harti rishna

irthaji thro#gh his boo' offer efficient a$ternatives. he present seminar ana$%ses and

compares the imp$ementation of -+ a$gorithm b% e)isting and b% Vedic

mathematica$ techni#e . It is s#ggested that architect#ra$ $eve$ changes in the entire

comp#tation s%stem to accommodate the Vedic mathematica$ method sha$$ increase

the overa$$ efficienc% of -+ proced#re.

. R>U6T>

.1 1;1 =e-ic $ultiplier:

-evice Kti$ization S#mmar%:

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Fig:.? Dechematic

Sim#$ation res#$t of 24 bit m#$tip$ier:

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`

Fig.2 sh/ws the simulati/n result /0 a 1 it multiplier.

+rom the fig#re we can infer that the inp#t is given when enab$e is high and e)ponent

va$#e is determined.

.2 4;4 =e-ic $ultiplier:

Fig.%: RT6 >chematic /0 4;4 =e-ic $ultiplier

[email protected] shows the schematic diagram of ?)? 0#$tip$ier.

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Fig .&: >imulati/n result /0 4;4 multiplier

.% &;& =e-ic $ultiplier:

9L schematic of 5)5 Vedic 0#$tip$ier

Fig.: RT6 >chematic /0 &;& $ultiplier

+ig @.@ shows the schematic diagram of 5)5 0#$tip$ier

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Fig.: >imulati/n Result /0 &;& $ultiplier l/c!

+ig @.4 shows the sim#$ation res#$ts of a 5)5 m#$tip$ier b$oc'

.& 2;2 =e-ic $ultiplier:

9L Schematic of 8)8 Vedic 0#$tip$ier

Fig.3: RT6 >chematic /0 2;2 $ultiplicati/n l/c!

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Fig.4: >imulati/n result 0/r a 2;2 chematic

33


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`

Sim#$ation 9es#$t of 85 (it +#$$ Adder:

Fig: .1? >imulati/n Result

..2 1 it Full "--er:

9L Schematic of 24 (it +#$$ Adder:

Fig:.11 RT6 >chematic

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Fig:.12 >imulati/n Result

..% 12 it Full "--er


Fig: .1% RT6 >chematic

35


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`

Sim#$ation 9es#$t of 28 (it +#$$ Adder

Fig: .1& >imulati/n Result

..& 4 it Full "--er:

9L Schematic of ? (it +#$$ Adder:

Fig:.1 RT6 >chematic

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`

Sim#$ation 9es#$t of ?bit +#$$ adder:

Fig: .1 >imulati/n Result

.. it Full "--er:

9L Schematic of 4 (it +#$$ Adder

Fig: .13 RT6 >chematic

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Fig:.14 >imulati/n Result

.. & it Full "--er:



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Fig .2? >imulati/n Result

..3 1 it Full "--er:

9L Schematic of 2 (it +#$$ Adder


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Sim#$ation 9es#$t of 2 (it +#$$ Adder

Fig: .22 >imulati/n Result

..4 8al0 "--er:

9L Schematic of /a$f Adder:

Fig: .2% RT6 >chematic

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Sim#$ation 9es#$t of /a$f Adder:

Fig: .2& >imulati/n Result

. FP7" I$P6$NT"TION:

Fig .2: >partan % /ar-

+ig @.8@ shows the snapshot of Spartan 7 board.A,( are the inp#ts and c is the

o#tp#t.

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+ig @.2B:O#tp#t cE 2BH737?57H!B2BBBBBBBBBBBBBBB22BBBBBBBBBBBBB2B2" when

aE78H43!2BBBBBBBBBBBBBB2"and bE78HH7!2BBBBBBBBBBBB2B2"

. Timing Rep/rt:

6O>: />S> I0I6 6K0(>9S A9> O6L A S6/>SIS >SI0A>.

+O9 AK9A> I0I6 I6+O90AIO6 PL>AS> 9>+>9 O /> 9A> 9>PO9

>6>9A>- A+>9 PLA>&and&9OK>.

$oc' Information:

&&&&&&&&&&&&&&&&&&

6o c$oc' signa$s fo#nd in this design

As%nchrono#s ontro$ Signa$s Information:

&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&

6o as%nchrono#s contro$ signa$s fo#nd in this design

Timing >ummar#:

&&&&&&&&&&&&&&&

Speed rade: &@

0inim#m period: 6o path fo#nd

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`

0inim#m inp#t arriva$ time before c$oc': 6o path fo#nd

0a)im#m o#tp#t re#ired time after c$oc': 6o path fo#nd

0a)im#m combinationa$ path de$a%: 83.284ns

Timing Detail:

&&&&&&&&&&&&&&

A$$ va$#es disp$a%ed in nanoseconds !ns"

EEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEE

iming constraint: -efa#$t path ana$%sis

ota$ n#mber of paths * destination ports: 7B2H7 * 24

&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&

-e$a%: 83.284ns !Leve$s of Logic E 2?"

So#rce: aT2U !PA-"

-estination: cT2@U !PA-"

-ata Path: aT2U to cT2@U

ate 6et

e$$:in&Uo#t fano#t -e$a% -e$a% Logica$ 6ame !6et 6ame"

&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&& &&&&&&&&&&&&

I(K+:I&UO 85 B.H2@ 2.?88 a2I(K+ !a2I(K+"

LK8:IB&UO 5 B.5H3 B.?B8 z2*z@*fa2*0)ors#m9es#$t722 !635"

LK5:I7&UO 2 B.5H3 B.3H4 z2*z@*fa2*0)ors#m9es#$t84!z2*z@*fa2*0)ors#m9es#$t84"

LK7:IB&UO 8 B.5H3 B.H5@ z2*z@*fa2*0)ors#m9es#$t8? !z2*5T2U"

0KG+@:S&UO 7 B.@5B B.352 z2*zH*fa2*co#tf@ !z2*zH*c8"

LK7:I2&UO 8 B.5H3 B.?B5 z2*zH*fa7*0)ors#m9es#$t22 !63"

LK7:I8&UO 8 B.5H3 2.B5B z2*zH*fa7*co#t2 !z2*zH*c5"

LK5:IB&UO 8 B.5H3 2.B5B z2*zH*fa5*0)ors#m9es#$t4@ !BT4U"

LK7:IB&UO 8 B.5H3 B.32@ z@*fa8*co#t2 !z@*c7"

LK5:I2&UO 8 B.5H3 B.?B5 z@*fa7*0)ors#m9es#$t2 !5T7U"

LK7:I8&UO 8 B.5H3 B.H4? zH*fa7*co#t2 !zH*c5"

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`

LK5:I7&UO 8 B.5H3 B.32@ zH*fa5*co#t2 !zH*c@"

LK7:I2&UO 8 B.5H3 B.32@ zH*fa@*co#t2 !zH*c4"

LK7:I2&UO 5 B.5H3 B.353 zH*fa4*co#t2 !zH*cH"

LK7:I2&UO 8 B.5H3 B.?B5 zH*faH*co#t2 !zH*c?"

LK7:I8&UO 2 B.5H3 B.?@2 zH*fa3*co#t2 !zH*c2B"

LK5:I2&UO 2 B.5H3 B.4?2 zH*fa22*0)ors#m9es#$t2 !c2@O(K+"

O(K+:I&UO 5.3B3 c2@O(K+ !cT2@U"

&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&

T/tal 29.12ns !27.753ns $ogic, [email protected] ro#te"

!5@.?W $ogic, @5.8W ro#teB

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`

. CONC6U>ION "ND FUTUR >COP

0#$tip$ier design based on the form#$as of the ancient Indian Vedic 0athematics,

high$% s#itab$e for high speedcomp$e) arithmetic circ#its which are having wide

app$ication in VLSI signa$ processing. he imp$ementation was done on +PA

SPA9A6&7 and compared with the most$% #sed architect#re $i'e distrib#ted

arithmetic, para$$e$ adderbased imp$ementation, and a$gebraic transformation based

imp$ementation. his nove$ architect#re combines the advantages of the Vedic

mathematics for m#$tip$ication which enco#nters the stages and partia$ prod#ct

red#ction.he proposed comp$e) n#mber m#$tip$ier offered a de$a% of 83.28ns which

is2B percent faster than booths m#$tip$ier and improvement in terms of propagation

de$a% and power cons#mption respective$%.

he project can be f#rther e)tended b% increasing the bit size and f#rther e)tensions

can be done for signed n#mbers and comp$e) n#mbers a$so.

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3. RFRNC>

X2Y P. . Saha, A. (anerjee, and A. -andapat, J/igh SpeedLow Poweromp$e)

0#$tip$ier -esign Ksing Para$$e$Adders and S#btractorsNInternationa$ Qo#rna$ on

>$ectronic and >$ectrica$ >ngineering,!*Q>>>".

X8Y . S. 1a$$ace, JA s#ggestion for a fast m#$tip$ier,J$>>rans.>$ectronicomp#t.,

vo$. >&Z7, pp. 25&2H, -ec.2345.

X7Y .PrabirSaha, Arindam (anerjee, Partha (hattachar%%a, An#p-andapat, M/igh

speed ASI design of comp$e) m#$tip$ier#sing vedic mathematicsN , Proceeding of

the 8B22 I>>>St#dents; echno$og% S%mposi#m 25&24 Qan#ar%, 8B22, $Iharagp#r,

pp. 87H&852.

X5Y https:**$earn.digi$entinc.com*-oc#ments*8@3

X@Y http:**www.)i$in).com*s#pport*doc#mentation

X4Y http:**e$ectronicsfor#.com

XHY http:**en.wi'ipedia.org*wi'i*

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"PPNDIB

". INTRODUCTION TO =RI6O7

".1 O=R=IW:

/ardware description $ang#ages s#ch as Veri$og differ from software

programming $ang#ages beca#se the% inc$#de wa%s of describing the propagation time

and signa$ strengths !sensitivit%". here are two t%pes of assignment operators= a

b$oc'ing assignment !E", and a non&b$oc'ing !TE" assignment. he non&b$oc'ing

assignment a$$ows designers to describe a state&machine #pdate witho#t needing to

dec$are and #se temporar% storage variab$es. Since these concepts are part of Veri$og;s

$ang#age semantics, designers co#$d #ic'$% write descriptions of $arge circ#its in a

re$ative$% compact and concise form. At the time of Veri$og;s introd#ction !23?5",

Veri$og represented a tremendo#s prod#ctivit% improvement for circ#it designers who

were a$read% #sing graphica$ schematic capt#re software and specia$$% written

software programs to doc#ment and sim#$ate e$ectronic circ#its.

he designers of Veri$og wanted a $ang#age with s%nta) simi$ar to the

programming $ang#age, which was a$read% wide$% #sed in engineering softwaredeve$opment. Li'e , Veri$og is case&sensitive and has a basic preprocessor !tho#gh

$ess sophisticated than that of A6SI *FF". Its contro$ f$ow 'e%words !if*e$se, for,

whi$e, case, etc." are e#iva$ent, and its operator precedence is compatib$e with .

S%ntactic differences inc$#de: re#ired bit&widths for variab$e dec$arations,

demarcation of proced#ra$ b$oc's !Veri$og #ses begin*end instead of c#r$% braces [\",

and man% other minor differences. Veri$og re#ires that variab$es be given a definite

size. In these sizes are ass#med from the ;t%pe; of the variab$e !for instance aninteger t%pe ma% be ? bits".

A Veri$og design consists of a hierarch% of mod#$es. 0od#$es encaps#$ate

design hierarch%, and comm#nicate with other mod#$es thro#gh a set of dec$ared

inp#t, o#tp#t, and bidirectiona$ ports. Interna$$%, a mod#$e can contain an%

combination of the fo$$owing: net*variab$e dec$arations !wire, reg, integer, etc.",

conc#rrent and se#entia$ statement b$oc's, and instances of other mod#$es !s#b&

hierarchies". Se#entia$ statements are p$aced inside a begin*end b$oc' and e)ec#ted

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in se#entia$ order within the b$oc'. /owever, the b$oc's themse$ves are e)ec#ted

conc#rrent$%, ma'ing Veri$og a dataf$ow $ang#age.

Veri$og;s concept of ;wire; consists of both signa$ va$#es !5&state: J2, B, f$oating,

#ndefinedJ" and signa$ strengths !strong, wea', etc.". his s%stem a$$ows abstract

mode$ing of shared signa$ $ines, where m#$tip$e so#rces drive a common net. 1hen a

wire has m#$tip$e drivers, the wire;s !readab$e" va$#e is reso$ved b% a f#nction of the

so#rce drivers and their strengths.

A s#bset of statements in the Veri$og $ang#age are s%nthesizab$e. Veri$og mod#$es that

conform to a s%nthesizab$e coding st%$e, 'nown as 9L !register&transfer $eve$", can

be ph%sica$$% rea$ized b% s%nthesis software. S%nthesis software a$gorithmica$$%

transforms the !abstract" Veri$og so#rce into a net$ist, a $ogica$$% e#iva$ent

description consisting on$% of e$ementar% $ogic primitives !A6-, O9, 6O, f$ip&

f$ops, etc." that are avai$ab$e in a specific +PA or VLSI techno$og%. +#rther

manip#$ations to the net$ist #$timate$% $ead to a circ#it fabrication b$#eprint !s#ch as a

photo mas' set for an ASI or a bitstream fi$e for an +PA".

".1.1 eginning:

Veri$og was one of the first modernXc$arification neededY hardware description

$ang#ages to be invented.Xcitation neededY It was created b% Prabh#oe$ and Phi$

0oorb% d#ring the winter of 23?7*23?5. he wording for this process was

JA#tomated Integrated -esign S%stemsJ !$ater renamed to atewa% -esign

A#tomation in 23?@" as a hardware mode$ing $ang#age. atewa% -esign A#tomation

was p#rchased b% adence -esign S%stems in 233B. adence now has f#$$ proprietar%

rights to atewa%;s Veri$og and the Veri$og&GL, the /-L&sim#$ator that wo#$d

become the de facto standard !of Veri$og $ogic sim#$ators" for the ne)t decade.

Origina$$%, Veri$og was intended to describe and a$$ow sim#$ation= on$% afterwards

was s#pport for s%nthesis added.

".1.2 =eril/g)9:

1ith the increasing s#ccess of V/-L at the time, adence decided to ma'e the

$ang#age avai$ab$e for open standardization. adence transferred Veri$og into the

p#b$ic domain #nder the Open Veri$og Internationa$ !OVI" !now 'nown as Acce$$era"

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organization. Veri$og was $ater s#bmitted to I>>> and became I>>> Standard 2745&

233@, common$% referred to as Veri$og&3@.

".1.% =eril/g 2??1:

>)tensions to Veri$og&3@ were s#bmitted bac' to I>>> to cover the deficiencies that

#sers had fo#nd in the origina$ Veri$og standard. hese e)tensions became I>>>

Standard 2745&8BB2 'nown as Veri$og&8BB2.

Veri$og&8BB2 is a significant #pgrade from Veri$og&3@. +irst, it adds e)p$icit s#pport

for !8;s comp$ement" signed nets and variab$es. Previo#s$%, code a#thors had to

perform signed operations #sing aw'ward bit&$eve$ manip#$ations !for e)amp$e, the

carr%&o#t bit of a simp$e ?&bit addition re#ired an e)p$icit description of the (oo$ean

a$gebra to determine its correct va$#e". he same f#nction #nder Veri$og&8BB2 can be

more s#ccinct$% described b% one of the b#i$t&in operators: F, &, *, , UUU. A

generate*endgenerate constr#ct !simi$ar to V/-L;s generate*endgenerate" a$$ows

Veri$og&8BB2 to contro$ instance and statement instantiation thro#gh norma$ decision

operators !case*if*e$se". Ksing generate*endgenerate, Veri$og&8BB2 can instantiate an

arra% of instances, with contro$ over the connectivit% of the individ#a$ instances. +i$e

I*O has been improved b% severa$ new s%stem tas's. And fina$$%, a few s%nta)additions were introd#ced to improve code readabi$it% !e.g. a$wa%s ], named

parameter override, &st%$e f#nction*tas'*mod#$e header dec$aration".

Veri$og&8BB2 is the dominant f$avor of Veri$og s#pported b% the majorit% of

commercia$ >-A software pac'ages.

".1.& =eril/g 2??:

6ot to be conf#sed with S%stemVeri$og, Veri$og 8BB@ !I>>> Standard 2745&8BB@"

consists of minor corrections, spec c$arifications, and a few new $ang#age feat#res

!s#ch as the #wire 'e%word".

A separate part of the Veri$og standard, Veri$og&A0S, attempts to integrate ana$og and

mi)ed signa$ mode$ing with traditiona$ Veri$og.

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".1. >#stem =eril/g:

S%stem Veri$og is a s#perset of Veri$og&8BB@, with man% new feat#res and capabi$ities

to aid design verification and design mode$ing. As of 8BB3, the S%stem Veri$og and

Veri$og $ang#age standards were merged into S%stem Veri$og 8BB3 !I>>> Standard

2?BB&8BB3".

he advent of hardware verification $ang#ages s#ch as OpenVera, and Verisit%;s e

$ang#age enco#raged the deve$opment of S#per$og b% o&-esign A#tomation Inc.

o&-esign A#tomation Inc was $ater p#rchased b% S%nops%s. he fo#ndations of

S#per$og and Vera were donated to Acce$$era, which $ater became the I>>> standard

P2?BB&8BB@: S%stemVeri$og.

;ample:

A he$$o wor$d program $oo's $i'e this:

mod#$e main=

initia$

begin

^disp$a%!J/e$$o wor$d_J"=

^finish=

end

endmod#$e

A simp$e e)amp$e of two f$ip&f$ops fo$$ows:

mod#$etop$eve$!c$oc',reset"=

inp#t c$oc'=

inp#t reset=

reg f$op2=

reg f$op8=

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a$wa%s ] !posedge reset or posedge c$oc'"

if !reset"

begin

f$op2 TE B=

f$op8 TE 2=

end

e$se

begin

f$op2 TE f$op8=

f$op8 TE f$op2=

end

endmod#$e

he JTEJ operator in Veri$og is another aspect of its being a hardware description

$ang#age as opposed to a norma$ proced#ra$ $ang#age. his is 'nown as a Jnon&

b$oc'ingJ assignment. Its action doesn;t register #nti$ the ne)t c$oc' c%c$e. his means

that the order of the assignments is irre$evant and wi$$ prod#ce the same res#$t: f$op2

and f$op8 wi$$ swap va$#es ever% c$oc'.

he other assignment operator, JEJ, is referred to as a b$oc'ing assignment. 1hen JEJ

assignment is #sed, for the p#rposes of $ogic, the target variab$e is #pdated

immediate$%. In the above e)amp$e, had the statements #sed the JEJ b$oc'ing operator

instead of JTEJ, f$op2 and f$op8 wo#$d not have been swapped. Instead, as in

traditiona$ programming, the compi$er wo#$d #nderstand to simp$% set f$op2 e#a$ to

f$op8 !and s#bse#ent$% ignore the red#ndant $ogic to set f$op8 e#a$ to f$op2".

An e)amp$e co#nter circ#it fo$$ows:

mod#$e -iv8B) !rst, c$', cet, cep, co#nt, tc"=

parameter size E @=

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parameter $ength E 8B=

inp#trst= ** hese inp#ts*o#tp#ts represent

inp#tc$'= ** connections to the mod#$e.

inp#tcet=

inp#tcep=

o#tp#t Xsize&2:BY co#nt=

o#tp#ttc=

reg Xsize&2:BY co#nt= ** Signa$s assigned within an a$wa%s !or initia$"b$oc' m#st be of** t%pe reg

wiretc= ** Other signa$s are of t%pe wire

** he a$wa%s statement be$ow is a para$$e$

** e)ec#tion statement that

** e)ec#tes an% time the signa$s

** rst or c$' transition from $ow to high

a$wa%s ] !posedgec$' or posedgerst"

if !rst" ** his ca#ses reset of the cntr

co#ntTE [size[2;bB\\=

e$se

if !cet``cep" ** >nab$es both tr#e

begin

if !co#nt EE $ength&2"

co#ntTE [size[2;bB\\=

e$se

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co#ntTE co#nt F 2;b2=

end

** the va$#e of tc is contin#o#s$% assigned

** the va$#e of the e)pression

assigntc E !cet`` !co#nt EE $ength&2""=

endmod#$e

"n e;ample /0 -ela#s:

reg a, b, c, d=

wire e=

a$wa%s ]!b or e"

begin

a E b ` e=

b E a b=

@ c E b=

d E 4 c e=

end

he a$wa%s c$a#se above i$$#strates the other t%pe of method of #se, i.e. it e)ec#tes

whenever an% of the entities in the $ist !the b or e" changes. 1hen one of thesechanges, a is immediate$% assigned a new va$#e, and d#e to the b$oc'ing assignment,

b is assigned a new va$#e afterward !ta'ing into acco#nt the new va$#e of a". After a

de$a% of @ time #nits, c is assigned the va$#e of b and the va$#e of c e is t#c'ed awa%

in an invisib$e store. hen after 4 more time #nits, d is assigned the va$#e that was

t#c'ed awa%.

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Signa$s that are driven from within a process !an initia$ or a$wa%s b$oc'" m#st be of

t%pe reg. Signa$s that are driven from o#tside a process m#st be of t%pe wire. he

'e%word reg does not necessari$% imp$% a hardware register.

".2 DFINITION OF CON>T"NT>:

he definition of constants in Veri$og s#pports the addition of a width parameter. he

basic s%nta) is:

T1idth in bitsU;Tbase $etterUTn#mberU

>)amp$es:

28;h287 & /e)adecima$ 287 !#sing 28 bits"

8B;d55 & -ecima$ 55 !#sing 8B bits & B e)tension is a#tomatic"

5;b2B2B & (inar% 2B2B !#sing 5 bits"

4;oHH & Octa$ HH !#sing 4 bits"

>#nthesieale c/nstructs:

here are severa$ statements in Veri$og that have no ana$og in rea$ hardware, e.g.

^disp$a%. onse#ent$%, m#ch of the $ang#age can not be #sed to describe hardware.

he e)amp$es presented here are the c$assic s#bset of the $ang#age that has a direct

mapping to rea$ gates.

** 0#) e)amp$es & hree wa%s to do the same thing.

** he first e)amp$e #ses contin#o#s assignment

wire o#t=

assign o#t E se$ a : b= ** the second e)amp$e #ses a proced#re to accomp$ish the

**same thing.

reg o#t=

a$wa%s ]!a or b or se$"

begin

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case!se$"

2;bB: o#t E b=

2;b2: o#t E a=

endcase

end

** +ina$$% & %o# can #se if*e$se in a proced#ra$ str#ct#re.

reg o#t=

a$wa%s ]!a or b or se$"

if !se$"

o#t E a=

e$se

o#t E b=

he ne)t interesting str#ct#re is a transparent $atch= it wi$$ pass the inp#t to the o#tp#t

when the gate signa$ is set for Jpass&thro#ghJ, and capt#res the inp#t and stores it

#pon transition of the gate signa$ to Jho$dJ. he o#tp#t wi$$ remain stab$e regard$ess

of the inp#t signa$ whi$e the gate is set to Jho$dJ. In the e)amp$e be$ow the Jpass&

thro#ghJ $eve$ of the gate wo#$d be when the va$#e of the if c$a#se is tr#e, i.e. gate E

2. his is read Jif gate is tr#e, the din is fed to $atcho#t contin#o#s$%.J Once the if

c$a#se is fa$se, the $ast va$#e at $atcho#t wi$$ remain and is independent of the va$#e

of din.

** ransparent $atch e)amp$e

reg$atcho#t=

a$wa%s ]!gate or din"

if!gate"

$atcho#t E din= ** Pass thro#gh state

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** 6ote that the e$se isn;t re#ired here. he variab$e

** $atcho#t wi$$ fo$$ow the va$#e of din whi$e gate is

** high. 1hen gate goes $ow, $atcho#t wi$$ remain constant.

he f$ip&f$op is the ne)t significant temp$ate= in Veri$og, the -&f$op is the simp$est,

and it can be mode$ed as:

reg =

a$wa%s ]!posedgec$'"

TE d=

he significant thing to notice in the e)amp$e is the #se of the non&b$oc'ing

assignment. A basic r#$e of th#mb is to #se TE when there is a posedge or negedge

statement within the a$wa%s c$a#se.

A variant of the -&f$op is one with an as%nchrono#s reset= there is a convention that

the reset state wi$$ be the first if c$a#se within the statement.

reg =

a$wa%s ]!posedgec$' or posedge reset"

if!reset"

TE B=

e$se

TE d=

he ne)t variant is inc$#ding both an as%nchrono#s reset and as%nchrono#s set

condition= again the convention comes into p$a%, i.e. the reset term is fo$$owed b% the

set term.

reg =

a$wa%s ]!posedgec$' or posedge reset or posedge set"

if!reset"

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TE B=

e$se

if!set"

TE 2=

e$se

TE d=

6ote: If this mode$ is #sed to mode$ a Set*9eset f$ip f$op then sim#$ation errors can

res#$t. onsider the fo$$owing test se#ence of events. 2" reset goes high 8" c$' goes

high 7" set goes high 5" c$' goes high again @" reset goes $ow fo$$owed b% 4" set going

$ow. Ass#me no set#p and ho$d vio$ations.

In this e)amp$e the a$wa%s ] statement wo#$d first e)ec#te when the rising edge of

reset occ#rs which wo#$d p$ace to a va$#e of B. he ne)t time the a$wa%s b$oc'

e)ec#tes wo#$d be the rising edge of c$' which again wo#$d 'eep at a va$#e of B.

he a$wa%s b$oc' then e)ec#tes when set goes high which beca#se reset is high forces

to remain at B. his condition ma% or ma% not be correct depending on the act#a$

f$ip f$op. /owever, this is not the main prob$em with this mode$. 6otice that when

reset goes $ow, that set is sti$$ high. In a rea$ f$ip f$op this wi$$ ca#se the o#tp#t to go to

a 2. /owever, in this mode$ it wi$$ not occ#r beca#se the a$wa%s b$oc' is triggered b%

rising edges of set and reset & not $eve$s. A different approach ma% be necessar% for

set*reset f$ip f$ops.

he fina$ basic variant is one that imp$ements a -&f$op with a m#) feeding its inp#t.

he m#) has a d&inp#t and feedbac' from the f$op itse$f. his a$$ows a gated $oad

f#nction.

** (asic str#ct#re with an >GPLII feedbac' path


if!gate"

TE d=

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e$se

TE = ** e)p$icit feedbac' path

** he more common str#ct#re ASSK0>S the feedbac' is present

** his is a safe ass#mption since this is how the

** hardware compi$er wi$$ interpret it. his str#ct#re

** $oo's m#ch $i'e a $atch. he differences are the

** ;;;]!posedgec$'";;; and the non&b$oc'ing ;;;TE;;;


if!gate"

TE d= ** the Je$seJ m#) is Jimp$iedJ

6ote that there are no Jinitia$J b$oc's mentioned in this description. here is a sp$it

between +PA and ASI s%nthesis too$s on this str#ct#re. +PA too$s a$$ow initia$

b$oc's where reg va$#es are estab$ished instead of #sing a JresetJ signa$. ASI

s%nthesis too$s don;t s#pport s#ch a statement. he reason is that an +PA;s initia$

state is something that is down$oaded into the memor% tab$es of the +PA. An ASI

is an act#a$ hardware imp$ementation.

".% INITI"6 "ND "6W"E>:

here are two separate wa%s of dec$aring a Veri$og process. hese are the a$wa%s and

the initia$ 'e%words. he a$wa%s 'e%word indicates a free&r#nning process. he initia$

'e%word indicates a process e)ec#tes e)act$% once. (oth constr#cts begin e)ec#tion at

sim#$ator time B, and both e)ec#te #nti$ the end of the b$oc'. Once an a$wa%s b$oc'

has reached its end, it is resched#$ed !again". It is a common misconception to be$ieve

that an initia$ b$oc' wi$$ e)ec#te before an a$wa%s b$oc'. In fact, it is better to thin' of

the initia$&b$oc' as a specia$&case of the a$wa%s&b$oc', one which terminates after it

comp$etes for the first time.

;amples

initia$

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begin

a E 2= ** Assign a va$#e to reg a at time B

2= ** 1ait 2 time #nit

b E a= ** Assign the va$#e of reg a to reg b

end

a$wa%s ]!a or b" ** An% time a or b /A6>, r#n the process

begin

if !a"

c E b=

e$se

d E b=

end ** -one with this b$oc', now ret#rn to the top !i.e. the ] event&contro$"

a$wa%s ]!posedge a"** 9#n whenever reg a has a $ow to high change

a TE b=

hese are the c$assic #ses for these two 'e%words, b#t there are two significant

additiona$ #ses. he most common of these is an a$wa%s 'e%word witho#t the ]!..."

sensitivit% $ist. It is possib$e to #se a$wa%s as shown be$ow:

a$wa%s

begin ** A$wa%s begins e)ec#ting at time B and 6>V>9 stops

c$' E B= ** Set c$' to B

2= ** 1ait for 2 time #nit

c$' E 2= ** Set c$' to 2


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end ** eeps e)ec#ting & so contin#e bac' at the top of the begin

he a$wa%s 'e%word acts simi$ar to the JJ constr#ct whi$e!2" [..\ in the sense that it

wi$$ e)ec#te forever.

he other interesting e)ception is the #se of the initia$ 'e%word with the addition of

the forever 'e%word.

he e)amp$e be$ow is f#nctiona$$% identica$ to the a$wa%s e)amp$e above.

initia$ forever ** Start at time B and repeat the begin*end forever

begin

c$' E B= ** Set c$' to B

2= ** 1ait for 2 time #nit

c$' E 2= ** Set c$' to 2


end

F/r!G/in:

he for'*join pair are #sed b% Veri$og to create para$$e$ processes. A$$ statements !or

b$oc's" between a for'*join pair begin e)ec#tion sim#$taneo#s$% #pon e)ec#tion f$ow

hitting the for'. >)ec#tion contin#es after the join #pon comp$etion of the $ongest

r#nning statement or b$oc' between the for' and join.

initia$

for'

^write!JAJ"= ** Print har A

^write!J(J"= ** Print har (

begin


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^write!JJ"=** Print har

end

join

he wa% the above is written, it is possib$e to have either the se#ences JA(J or

J(AJ print o#t. he order of sim#$ation between the first ^write and the second

^write depends on the sim#$ator imp$ementation, and ma% p#rposef#$$% be

randomized b% the sim#$ator. his a$$ows the sim#$ation to contain both accidenta$

race conditions as we$$ as intentiona$ non&deterministic behavior.

6otice that V/-L cannot d%namica$$% spawn m#$tip$e processes $i'e Veri$og.

Race c/n-iti/ns

he order of e)ec#tion isn;t a$wa%s g#aranteed within Veri$og. his can best be

i$$#strated b% a c$assic e)amp$e. onsider the code snippet be$ow:

initia$

a E B=

initia$

b E a=

initia$

begin

2=

^disp$a%!JVa$#e aEWa Va$#e of bEWbJ,a,b"=

end

1hat wi$$ be printed o#t for the va$#es of a and b -epending on the order of

e)ec#tion of the initia$ b$oc's, it co#$d be zero and zero, or a$ternate$% zero and some

other arbitrar% #ninitia$ized va$#e. he ^disp$a% statement wi$$ a$wa%s e)ec#te after

both assignment b$oc's have comp$eted, d#e to the 2 de$a%

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. INTRODUCTION TO =6>I

Ver%&$arge&sca$e integration !VLSI" is the process of creating integrated

circ#its b% combining tho#sands of transistor&based circ#its into a sing$e chip. VLSI

began in the 23HBs when comp$e) semicond#ctor and comm#nication techno$ogies

were being deve$oped. he microprocessor is a VLSI device. he term is no $onger as

common as it once was, as chips have increased in comp$e)it% into the h#ndreds of

mi$$ions of transistors.

.1 O=R=IW:

he first semicond#ctor chips he$d one transistor each. S#bse#ent advancesadded more and more transistors, and, as a conse#ence, more individ#a$ f#nctions or

s%stems were integrated over time. he first integrated circ#its he$d on$% a few

devices, perhaps as man% as ten diodes, transistors, resistors and capacitors, ma'ing it

possib$e to fabricate one or more $ogic gates on a sing$e device. 6ow 'nown

retrospective$% as Jsma$$&sca$e integrationJ !SSI", improvements in techni#e $ed to

devices with h#ndreds of $ogic gates, 'nown as $arge&sca$e integration !LSI", i.e.

s%stems with at $east a tho#sand $ogic gates. #rrent techno$og% has moved far past

this mar' and toda%;s microprocessors have man% mi$$ions of gates and h#ndreds of

mi$$ions of individ#a$ transistors.

At one time, there was an effort to name and ca$ibrate vario#s $eve$s of $arge&

sca$e integration above VLSI. erms $i'e K$tra&$arge&sca$e Integration !KLSI" were

#sed. (#t the h#ge n#mber of gates and transistors avai$ab$e on common devices has

rendered s#ch fine distinctions moot. erms s#ggesting greater than VLSI $eve$s of

integration are no $onger in widespread #se. >ven VLSI is now somewhat #aint,

given the common ass#mption that a$$ microprocessors are VLSI or better.

As of ear$% 8BB?, bi$$ion&transistor processors are commercia$$% avai$ab$e, an

e)amp$e of which is Inte$;s 0ontecito Itani#m chip. his is e)pected to become more

commonp$ace as semicond#ctor fabrication moves from the c#rrent generation of 4@

nm processes to the ne)t 5@ nm generations !whi$e e)periencing new cha$$enges s#ch

as increased variation across process corners". Another notab$e e)amp$e is 6VI-IARs

8?B series PK.

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his microprocessor is #ni#e in the fact that its 2.5 (i$$ion transistor co#nt,

capab$e of a teraf$op of performance, is a$most entire$% dedicated to $ogic !Itani#m;s

transistor co#nt is $arge$% d#e to the 850( L7 cache". #rrent designs, as opposed to

the ear$iest devices, #se e)tensive design a#tomation and a#tomated $ogic s%nthesis to

$a% o#t the transistors, enab$ing higher $eve$s of comp$e)it% in the res#$ting $ogic

f#nctiona$it%. ertain high&performance $ogic b$oc's $i'e the S9A0 ce$$, however,

are sti$$ designed b% hand to ens#re the highest efficienc% !sometimes b% bending or

brea'ing estab$ished design r#$es to obtain the $ast bit of performance b% trading

stabi$it%".

.2 =6>I:

VLSI stands for JVer% Large Sca$e IntegrationJ. his is the fie$d

whichInvo$ves pac'ing more and more $ogic devices into sma$$er and sma$$er areas.

2. Simp$% we sa% Integrated circ#it is man% transistors on one chip.

8. -esign*man#fact#ring of e)treme$% sma$$, comp$e) circ#itr% #sing modified

semicond#ctor materia$.

7. Integrated circ#it !I" ma% contain mi$$ions of transistors, each a few mm in

size.5. App$ications wide ranging: most e$ectronic $ogic devices.

.% =6>I D>I7N F6OW:

.%.1 Digital Circuit:

-igita$ Is of SSI and 0SI t%pes have become #niversa$$% standardized and

have been accepted for #se. 1henever a designer has to rea$ize a digita$ f#nction, he

#ses a standard set of Is a$ong with a minima$ set of additiona$ discrete circ#itr%.

onsider a simp$e e)amp$e of rea$izing a f#nction as

Q nF2 E Q n F ! A B"

/ere on, A, and B are (oo$ean variab$es, with Q n being the va$#e of Q at the

nth time step. /ere A B signifies the $ogica$ A6- of A and B= the CFR s%mbo$ signifies

the $ogica$ O9 of the $ogic variab$es on either side. A circ#it to rea$ize the f#nction is

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On

(

`

shown in +ig#re. he circ#it can be rea$ized in terms of two Is < an A&O&I gate and a

f$ip&f$op. It can be direct$% wired #p, tested, and #sed.

Fig .1: >imple -igital circuit

1ith comparative$% $arger circ#its, the tas' most$% red#ces to one of

identif%ing the set of Is necessar% for the job and interconnecting= rare$% does one

have to resort to a micro $eve$ design. he accepted approach to digita$ design here is

a mi) of the top&down and bottomp approaches as fo$$ows.

-ecide the re#irements at the s%stem $eve$ and trans$ate them to circ#it re#irements.

Identif% the major f#nctiona$ b$oc's re#ired $i'e timer, -0A #nit, register fi$e etc.,

sa% as in the design of a processor.

1henever a f#nction can be rea$ized #sing a standard I, #se the same


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S%stem re#irements

irc#it re#irements

IsOther components

P( $a%o#t

1iring ` testing

+ina$ circ#it

`

Kse additiona$ components $i'e transistor, diode, resistor, capacitor, etc.,

wherever essentia$.

Fig .2: Pr/cess 0l/wchart

Once the above steps are gone thro#gh, a paper design is read%. Starting with

the paper design, one has to do a circ#it $a%o#t. he ph%sica$ $ocation of a$$ the

components is tentative$% decided= the% are interconnected and the Ccirc#it&onpaperR is

made read%. Once a paper design is done, a $a%o#t is carried o#t and a net&$ist

prepared. (ased on this, the P( is fabricated and pop#$ated and a$$ the pop#$ated

cards tested and deb#gged.

At the deb#gging stage one ma% enco#nter three t%pes of prob$ems:

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+#nctiona$ mismatch: he rea$ized and e)pected f#nctions are different. One

ma% have to go thro#gh the re$evant f#nctiona$ b$oc' caref#$$% and $ocate an%

error $ogica$$%. +ina$$% the necessar% correction has to be carried o#t in

hardware.

iming mismatch: he prob$em can manifest in different forms. One

possibi$it% is d#e to the signa$ going thro#gh different propagation de$a%s in

two paths and arriving at a point with a timing mismatch. his can ca#se

fa#$t% operation. Another possibi$it% is a race condition in a circ#it invo$ving

as%nchrono#s feedbac'. his 'ind of prob$em ma% ca$$ for e$aborate

deb#gging. he preferred practice is to do deb#gging at sma$$er mod#$e stages

and ens#ring that feedbac' thro#gh $arger $oops is avoided: It becomes

essentia$ to chec' for the e)istence of $ong as%nchrono#s $oops.

Over$oad: Some signa$s ma% be over$oaded to s#ch an e)tent that the signa$

transition ma% be #nd#$% de$a%ed or even s#ppressed. he prob$em manifests

as ref$ections and erratic behavior in some cases !he signa$ has to be s#itab$%

b#ffered here.". In fact, over$oad on a signa$ can $ead to timing mismatches.

he above have to be carried o#t after comp$etion of the protot%pe P(

man#fact#ring= it invo$ves cost, time, and a$so a redesigning process to deve$op a b#g

free design.

8ist/r# /0 >cale Integrati/n:

Late 5Bs ransistor invented at (e$$ Labs

Late @Bs +irst I !Q&++ b% Qac' i$b% at I"

>ar$% 4Bs Sma$$ Sca$e Integration !SSI"

2Bs of transistors on a chip

Late 4Bs 0edi#m Sca$e Integration !0SI"

2BBs of transistors on a chip

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>ar$% HBs Large Sca$e Integration !LSI"

2BBBs of transistor on a chip

>ar$% ?Bs VLSI 2B,BBBs of transistors on a

chip !$ater 2BB,BBBs ` now 2,BBB,BBBs"

K$tra LSI is sometimes #sed for 2,BBB,BBBs

SSI & Sma$$&Sca$e Integration !B&2B8"

0SI & 0edi#m&Sca$e Integration !2B8&2B7"

LSI & Large&Sca$e Integration !2B7&2B@"

VLSI & Ver% Large&Sca$e Integration !2B@&2BH"

KLSI & K$tra Large&Sca$e Integration !UE2BH"

.%.2 =6>I Design:

he comp$e)it% of VLSIs being designed and #sed toda% ma'es the man#a$

approach to design impractica$. -esign a#tomation is the order of the da%. 1ith the

rapid techno$ogica$ deve$opments in the $ast two decades, the stat#s of VLSI

techno$og% is characterized b% the fo$$owing:

A stead% increase in the size and hence the f#nctiona$it% of the Is.

A stead% red#ction in feat#re size and hence increase in the speed of operation

as we$$ as gate or transistor densit%.

A stead% improvement in the predictabi$it% of circ#it behavior.

A stead% increase in the variet% and size of software too$s for VLSI design.

he above deve$opments have res#$ted in a pro$iferation of approaches toVLSI design. 1e brief$% describe the proced#re of a#tomated design f$ow. he aim is

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more to bring o#t the ro$e of a /ardware -escription Lang#age !/-L" in the design

process. An abstraction based mode$ is the basis of the a#tomated design.

.%.% "stracti/n $/-el:

he mode$ divides the who$e design c%c$e into vario#s domains. 1ith s#ch an

abstraction thro#gh a division process the design is carried o#t in different $a%ers. he

designer at one $a%er can f#nction witho#t bothering abo#t the $a%ers above or be$ow.

he thic' horizonta$ $ines separating the $a%ers in the fig#re signif% the

compartmenta$ization. As an e)amp$e, $et #s consider design at the gate $eve$. he

circ#it to be designed wo#$d be described in terms of tr#th tab$es and state tab$es.

1ith these as avai$ab$e inp#ts, he has to e)press them as (oo$ean $ogic e#ations andrea$ize them in terms of gates and f$ip&f$ops. In t#rn, these form the inp#ts to the $a%er

immediate$% be$ow. ompartmenta$ization of the approach to design in the manner

described here is the essence of abstraction= it is the basis for deve$opment and #se of

A- too$s in VLSI design at vario#s $eve$s.

he design methods at different $eve$s #se the respective aids s#ch as (oo$ean

e#ations, tr#th tab$es, state transition tab$e, etc. (#t the aids p$a% on$% a sma$$ ro$e in

the process. o comp$ete a design, one ma% have to switch from one too$ to another,

raising the iss#es of too$ compatibi$it% and $earning new environments.

.& ">IC D>I7N F6OW:

As with an% other technica$ activit%, deve$opment of an ASI starts with an

idea and ta'es tangib$e shape thro#gh the stages of deve$opment. he first step in the

process is to e)pand the idea in terms of behavior of the target circ#it. hro#gh stages

of programming, the same is f#$$% deve$oped into a design description < in terms of

we$$&defined standard constr#cts and conventions.

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Idea

-esign description

S%nthesisSim#$ation

Ph%sica$ design

`

Fig .%: Design -/main an- le


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dedicated too$s. 1ith ever% sim#$ation r#n, the sim#$ation res#$ts are st#died to

identif% errors in the design description. he errors are corrected and another

sim#$ation r#n carried o#t. Sim#$ation and changes to design description together

form a c%c$ic iterative process, repeated #nti$ an error&free design is evo$ved.

-esign description is an activit% independent of the target techno$og% or

man#fact#rer. It res#$ts in a description of the digita$ circ#it. o trans$ate it into a

tangib$e circ#it, one goes thro#gh the ph%sica$ design process. he same constit#tes a

set of activities c$ose$% $in'ed to the man#fact#rer and the target techno$og%.

.&.1 Design Descripti/n:

he design is carried o#t in stages. he process of transforming the idea into a

detai$ed circ#it description in terms of the e$ementar% circ#it components constit#tes

design description. he fina$ circ#it of s#ch an I can have #p to a bi$$ion s#ch

components= it is arrived at in a step&b%&step manner. he first step in evo$ving the

design description is to describe the circ#it in terms of its behavior. he description

$oo's $i'e a program in a high $eve$ $ang#age $i'e . Once the behaviora$ $eve$ design

description is read%, it is tested e)tensive$% with the he$p of a sim#$ation too$= it

chec's and confirms that a$$ the e)pected f#nctions are carried o#t satisfactori$%. If necessar%, this behaviora$ $eve$ ro#tine is edited, modified, and rer#n < a$$ done

man#a$$%. +ina$$%, one has a design for the e)pected s%stem < described at the

behaviora$ $eve$. he behaviora$ design forms the inp#t to the s%nthesis too$s, for

circ#it s%nthesis. he behaviora$ constr#cts not s#pported b% the s%nthesis too$s are

rep$aced b% data f$ow and gate $eve$ constr#cts. o s#rmise, the designer has to

deve$op s%nthesizab$e codes for his design. he design at the behaviora$ $eve$ is to be

e$aborated in terms of 'nown and ac'now$edged f#nctiona$ b$oc's. It forms the ne)t

detai$ed $eve$ of design description

Once again the design is to be tested thro#gh sim#$ation and iterative$%

corrected for errors. he e$aboration can be contin#ed one or two steps f#rther. It

$eads to a detai$ed design description in terms of $ogic gates and transistor switches.

.&.2 Optimiati/n:

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he circ#it at the gate $eve$ < in terms of the gates and f$ip&f$ops < can be

red#ndant in nat#re. he same can be minimized with the he$p of minimization too$s.

he step is not shown separate$% in the fig#re. he minimized $ogica$ design is

converted to a circ#it in terms of the switch $eve$ ce$$s from standard $ibraries

provided b% the fo#ndries. he ce$$ based design generated b% the too$ is the $ast step

in the $ogica$ design process= it forms the inp#t to the first $eve$ of ph%sica$ design.

.&.% >imulati/n:

he design descriptions are tested for their f#nctiona$it% at ever% $eve$


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Fig .: ">IC Design an- De


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.&.& >#nthesis:

1ith the avai$abi$it% of design at the gate !switch" $eve$, the $ogica$ design is

comp$ete. he corresponding circ#it hardware rea$ization is carried o#t b% a s%nthesis

too$.

wo common approaches are as fo$$ows:

he circ#it is rea$ized thro#gh an +PA. he gate $eve$ design description is the

starting point for the s%nthesis here. he +PA vendors provide an interface to the

s%nthesis too$. hro#gh the interface the gate $eve$ design is rea$ized as a fina$

circ#it. 1ith man% s%nthesis too$s, one can direct$% #se the design description at

the data f$ow $eve$ itse$f to rea$ize the fina$ circ#it thro#gh an +PA. he +PA

ro#te is attractive for $imited vo$#me prod#ction or a fast deve$opment c%c$e.

he circ#it is rea$ized as an ASI. A t%pica$ ASI vendor wi$$ have his own

$ibrar% of basic components $i'e e$ementar% gates and f$ip&f$ops. >vent#a$$% the

circ#it is to be rea$ized b% se$ecting s#ch components and interconnecting them

conforming to the re#ired design. his constit#tes the ph%sica$ design. (eing an

e$aborate and cost$% process, a ph%sica$ design ma% ca$$ for an intermediate

f#nctiona$ verification thro#gh the +PA ro#te. he circ#it rea$ized thro#gh the

+PA is tested as a protot%pe. It provides another opport#nit% for testing the

design c$oser to the fina$ circ#it.

.&. Ph#sical Design:

A f#$$% tested and error&free design at the switch $eve$ can be the starting point

for a ph%sica$ design. It is to be rea$ized as the fina$ circ#it #sing !t%pica$$%" a mi$$ion

components in the fo#ndr%Rs $ibrar%. he step&b%&step activities in the process are

described brief$% as fo$$ows:

S%stem partitioning: he design is partitioned into convenient compartments or

f#nctiona$ b$oc's. Often it wo#$d have been done at an ear$ier stage itse$f and the

software design prepared in terms of s#ch b$oc's. Interconnection of the b$oc's is

part of the partition process.

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+$oor p$anning: he positions of the partitioned b$oc's are p$anned and the b$oc's

are arranged according$%. he proced#re is ana$ogo#s to the p$anning and

arrangement of domestic f#rnit#re in a residence. ($oc's with I*O pins are 'ept

c$ose to the peripher%= those which interact fre#ent$% or thro#gh a $arge n#mber of interconnections are 'ept c$ose together, and so on. Partitioning and f$oor

p$anning ma% have to be carried o#t and refined iterative$% to %ie$d best res#$ts.

P$acement: he se$ected components from the ASI $ibrar% are p$aced in position

on the MSi$icon f$oor.N It is done with each of the b$oc's above.

9o#ting: he components p$aced as described above are to be interconnected to

the rest of the b$oc': It is done with each of the b$oc's b% s#itab$% ro#ting the

interconnects. Once the ro#ting is comp$ete, the ph%sica$ design cam is ta'en as

comp$ete. he fina$ mas' for the design can be made at this stage and the ASI

man#fact#red in the fo#ndr%.

.&. P/st 6a#/ut >imulati/n:

Once the p$acement and ro#ting are comp$eted, the performance specifications

$i'e si$icon area, power cons#med, path de$a%s, etc., can be comp#ted. >#iva$ent

circ#it can be e)tracted at the component $eve$ and performance ana$%sis carried o#t.

his constit#tes the fina$ stage ca$$ed Mverification.N One ma% have to go thro#gh the

p$acement and ro#ting activit% once again to improve performance.

.&.3 Critical >us#stems:

he design ma% have critica$ s#bs%stems. heir performance ma% be cr#cia$ to

the overa$$ performance= in other words, to improve the s%stem performance

s#bstantia$$%, one ma% have to design s#ch s#bs%stems afresh. he design here ma%

imp$% redefinition of the basic feat#re size of the component, component design,

p$acement of components, or ro#ting done separate$% and specifica$$% for the

s#bs%stem. A set of mas's #sed in the fo#ndr% ma% have to be done afresh for the

p#rpose.

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C. FI6D PRO7R"$$"6 7"T "RR"E

C.1 INTRODUCTION:

+PA contains a two dimensiona$ arra%s of $ogic b$oc's and interconnections

between $ogic b$oc's. (oth the $ogic b$oc's and interconnects are programmab$e.

Logic b$oc's are programmed to imp$ement a desired f#nction and the interconnects

are programmed #sing the switch bo)es to connect the $ogic b$oc's.

o be more c$ear, if we want to imp$ement a comp$e) design !PK for instance", then

the design is divided into sma$$ s#b f#nctions and each s#b f#nction is imp$emented

#sing one $ogic b$oc'. 6ow, to get o#r desired design !PK", a$$ the s#b f#nctions

imp$emented in $ogic b$oc's m#st be connected and this is done b% programming the

interconnects. .

Interna$ str#ct#re of an +PA is depicted in the fo$$owing fig#re .2.

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Fig C.1: FP7" "rchitecture

+PAs, a$ternative to the c#stom Is, can be #sed to imp$ement an entire

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