MAPLD 2004 Jasinski/10051 Evaluating Logic Resources Utilization in an FPGA-Based TMR CPU Ricardo Jasinski, Volnei A. Pedroni. ([email protected], [email protected])

Jasinski/1005 1 MAPLD 2004

Evaluating Logic Resources Utilization in an FPGA-Based TMR CPU

Ricardo Jasinski, Volnei A. Pedroni.([email protected], [email protected])

Federal Center of Technological Education of Parana – CEFET/PR

Curitiba-PR, Brazil.

Jasinski 2 MAPLD 2004

1. Topics

1. Introduction2. Traditional TMR

• Combinational logic• Sequential logic• Memory circuits• Combinational logic with enable inputs

3. The original CPU4. Implementation

• CPU building blocks• Adaptation process

5. Resources Usage Estimation6. Experimental Results7. Conclusions


1. Introduction

• Triple modular redundancy (TMR) design techniques add reliability to a system at the expense of extra hardware resources;

• In a TMR system, all protected modules must be triplicated, in order to allow for automatic fault masking;

• An intuitive conclusion is that the resulting design would require approximately three times as many resources as the original design; however, practical results tend to present a much greater ratio.


2. Traditional TMR (1/6)

• Xilinx, Inc. design techniques for the implementation of fault- and radiation-tolerant designs;

• Basic concepts of TMR: • triplication of the module to be protected;• use of a majority voter:

• shortcoming: reliability cannot be grater than that of the voter.

V Output

Redundant Module 1

InputRedundant Module 2

Redundant Module 3

Majority voter

A B C Y

0 0 0 0

0 0 1 0

0 1 0 0

0 1 1 1

1 0 0 0

1 0 1 1

1 1 0 1

1 1 1 1

Truth table::



• In traditional systems, reliability of the voter can be greater than the reliability of redundant modules;

• In an FPGA, voters are usually implemented with the same logic resources than the rest of the circuit;

• Solution: triplication of voting circuits

Output 2

V Output 1

Output 3

Redundant Module 1

Redundant Module 2

Redundant Module 3

Input 1

Input 2

Input 3

V

V



• Combinational Logic• at any time, outputs depend on the inputs only;• also includes circuits in which the result take more than one clock

cycle to be computed;• protection method => simple triplication

• no voter needed right after module outputs • Conclusion: purely combinational logic requires no change in

original source files; simply create a new, TMR module and instantiate 3 times the original module.

(a) original circuit

(no TMR)(b) protected

circuit (with TMR)



• Sequential Logic• requires additional care to avoid error persistence

• correct TMR implementation:1. triplicate all circuits, including combinational logic and flip-flops;

2. insert one voter circuit in each feedback path.

• Conclusion: sequential modules require changes in original source code. In addition, voters must be added within the new TMR entity.

output

clk

D Q

(a) original circuit (no TMR)

output 2

V output 1

output 3

V

VD Q

D Q

D Q

clk 1

clk 2

clk 3

(b) protected circuit (with TMR)



• Memories• must have a means to avoid error build-up;

• application-independent protection techniques are preferable;

• FPGAs with dual-port RAMs: • 1 port for user application;

• 1 port for automatic refresh.

ADD1

DIN1

CLK

ADD1

DIN1

DOUT1

DOUT2

User logic signals

Unused signals

(a) original memory circuit (without TMR)

ADD1

DIN1

CLK1

ADD2

DIN2

DOUT1

DOUT2 V

V

V

TMR Counter

CLK2

ADD1

DIN1

CLK1

ADD2

DIN2

DOUT1

DOUT2

CLK2

ADD1

DIN1

CLK1

ADD2

DIN2

DOUT1

DOUT2

CLK2

User logic signals

Refresh signals

(b) protected memory circuit (with TMR and automatic refresh)



• Combinational Logic with Enable Input• registers may have to maintain stored data for

arbitrarily long time periods (application-dependent);

• flip-flop adapted for automatic refresh at each clock cycle:

D Q

EN

input

enable

clk

output

(a) original flip-flop

D Qinput

enable

clk

0

1 tmr_voteroutput

(b) protected flip-flop


3. The Original CPU (1/1)

• Xilinx PicoBlaze;

• 8-bit CPU, designed for implementation in CPLD and FPGA devices;

• Indicated for aplications requiring a complex, but non-time-critical state machine;

• 4 different configurations;

• 49 16-bit instructions; eight 8-bit registers.


3. The Original CPU (2/2)

• Chosen configuration: for CPLD devices;

• Device-independent VHDL code.

8-bit Registers

s7s6s5s4s3s2s1s0

Zero and Carry flags

Interrupt state preserve

Interrupt control

Program flow control

Program Counter

Program Counter Stack

Program memory

(RAM/ROM)

256 words

IN_PORT[7:0]

RESETCLK

Operational control &

Insctruction decoding

INTERRUPT

ADDRESS[7:0]

PORT_ID[7:0]READ_STROBEWRITE_STROBE

OUT_PORT[7:0]

Instruction (16-bit) Datapath (8-bits) Program address (8-bit) Constants (8-bit)

INSTRUCTION[15:0]

I/O Addressing Control

ALUAdd, subtract, shift and rotate

Legend:


4. Implementation (1/2)

• Each building block was protected by TMR;

• All protected modules were instantiated to create a TMR version of the CPU;

• Emphasis on source code reuse;

• Systematic changes;

• Not necessary to know details on how the adapted circuit works; only information necessary is the kind of logic implemented by each block.


4. Implementation (2/2)

• First step: identification of the CPU`s building blocks;

• Second step: applicationof traditional TMRdesign techniques;

• Third step: evaluation.

Pure Combinational Logic:

picoblaze.vhd, arithmetic.vhd, interrupt_capture.vhd, IO_strobe_logic.vhd, logical_bus_processing.vhd, register_and_flag_enable.vhd, shift_rotate.vhd, zero_flag_logic.vhd.

Combinational Logic with Enable Inputs:

carry_flag_logic.vhd, interrupt_logic.vhd, zero_flag_logic.vhd.

Sequential Logic:

program_counter.vhd, stack_counter.vhd, T_state_and_Reset.vhd.

Memories:

register_bank.vhd, stack_ram.vhd.


5. Resources Usage Estimation

Type of Logic Number of Registers Number of Logic Cells

Combinational NRTMR = NR 3 LCTMR = LC 3

Combinational with enable NRTMR = NR 3 LCTMR = (LC + NFF) 3 (mín.)

Sequential NRTMR = NR 3 LCTMR = (LC + NSE) 3

Memory NRTMR = (NR + log2M) 3 ---

Where NR = number of registers of the original moduleNRTMR = number of registers of the TMR module

M = number of memory positionsLC = number of logic cells of the original moduleLCTMR = number of logic cells of the TMR module

NFF = number of flip-flops with enable input

NSE = number of state storage elements

Estimated resources usage:


6. Results (1/2)

ModuleRegisters Logic Cells

Original Estimated With TMR Original Estimated With TMR

arithmatic 9 27 27 27 81 81

carry_flag_logic 1 3 3 4 15 15

interrupt_capture 2 6 6 3 9 9

interrupt_logic 3 9 9 5 24 30

IO_strobe_logic 2 6 6 2 6 6

logical_bus_processing 8 24 24 8 24 24

program_counter 8 24 24 52 180 180

register_and_flag_enable 3 9 9 5 15 15

register_bank 64 201 201 146 -- 813

T_state_and_Reset 3 9 9 3 12 12

shift_rotate 9 27 27 16 48 48

zero_flag_logic 1 3 3 5 18 18

stack_counter 2 6 6 5 21 21

stack_ram 40 126 126 52 -- 351

picoblaze (at entity level) 0 0 0 57 171 171

Total 155 480 480 390 -- 1794

Table 1 - Synthesis results × estimated values:


6. Results (2/2)

Type of Logic

Registers Logic Cells

Without TMR

With TMR Ratio Without TMR

With TMRRatio

Pure Combinational 33 99 3.0 118 354 3.0

Combinational w/ Enable

5 15 3.0 14 63 4.5

Sequential 13 39 3.0 60 213 3.5

Memory 104 327 3.1 198 1164 5.9

Total 155 480 3.1 390 1794 4.6

Table 2 - Increase in resources usage by type of logic:


7. Conclusions

• A methodology was proposed, employed and verified, for the adaptation of an existing CPU (or any other circuits) in order to create a TMR version; it is not necessary to know exactly how the adapted circuit works, only the kind of logic implemented in each block;

• Traditional TMR design techniques were applied, and the impact in the logic resources usage was recorded, considering the type of logic implemented;

• The practical results achieved were greater (more area-consuming) than the intuitively expected values (4.6 ~3.0);

• A method for the calculation of logic resources needed in the adaptation of an existing circuit to TMR has also been presented and verified.

Documents

MAPLD 2004 Jasinski/10051 Evaluating Logic Resources Utilization in an FPGA-Based TMR CPU Ricardo Jasinski, Volnei A. Pedroni. ([email protected], [email protected])