MCP4261_2OPCION

8/12/2019 MCP4261_2OPCION

1/84

2007 Microchip Technology Inc. DS22059A-page 1

MCP414X/416X/424X/426X

Features

Single or Dual Resistor Network options Potentiometer or Rheostat configuration options Resistor Network Resolution

- 7-bit: 128 Resistors (129 Steps)- 8-bit: 256 Resistors (257 Steps)

RABResistances options of:- 5 k- 10 k- 50 k

- 100 k Zero-Scale to Full-Scale Wiper operation Low Wiper Resistance: 75(typ.) Low Tempco:

- Absolute (Rheostat): 50 ppm typical(0C to 70C)

- Ratiometric (Potentiometer): 15 ppm typical Non-volatile Memory

- Automatic Recall of Saved Wiper Setting- WiperLock Technology

SPI serial interface (10 Mhz, modes 0,0 & 1,1)- High-Speed Read/Writes to wiper registers- Read/Write to Data EEPROM registers- Serially enabled EEPROM write protect

- SDI/SDO multiplexing (MCP41X1 only) Resistor Network Terminal Disconnect Feature

via:

- Shutdown pin (SHDN)- Terminal Control (TCON) Register

Write Protect Feature:- Hardware Write Protect (WP) Control pin- Software Write Protect (WP) Configuration bit

Brown-out reset protection (1.5V typical) Serial Interface Inactive current (2.5 uA typ.) High-Voltage Tolerant Digital Inputs: Up to 12.5V Supports Split Rail Applications Internal weak pull-up on all digital inputs Wide Operating Voltage:

- 2.7V to 5.5V - Device CharacteristicsSpecified

- 1.8V to 5.5V - Device Operation Wide Bandwidth (-3dB) Operation:

- 2 MHz (typ.) for 5.0 kdevice Extended temperature range (-40C to +125C)

Description

The MCP41XX and MCP42XX devices offer a widerange of product offerings using an SPI interface. Thisfamily of devices support 7-bit and 8-bit resistornetworks, Non-Volatile memory configurations, andPotentiometer and Rheostat pinouts.

WiperLock Technology allows application-specificcalibration settings to be secured in the EEPROM.

Package Types

1234 5

678

P0WP0B

P0AVSS

VDD

MCP41X1Single Potentiometer

PDIP, SOIC, MSOP,

CS

SDI/SDOSCK

1234 5

678

P0BSDO

P0W

VDD

MCP41X2Single Rheostat

PDIP, SOIC, MSOP,

1234 11

121314

SHDNSDO

WP

VDD

MCP42X1Dual Potentiometers

PDIP, SOIC, TSSOP

567 8

910 P0WP0B

P0AP1AP1WP1B

VSS

CS

SDISCK

VSS

CS

SDISCK

1

2

3

4

11

121314

SDO

SHDN

4x4 QFN

5 6 7 89

10 P0B

NC

P0W

P0A

P1A

P1

W

VSS

SCK

VSS

SDI

1516

P1B

VDD

CS

WP

1234 7

89

10SDOVDD

MCP42X2Dual Rheostat

MSOP, DFN

5 6

P0BP0WP1WP1B

VSS

CS

SDISCK

3x3 DFN 3x3 DFN

7/8-Bit Single/Dual SPI Digital POT with

Non-Volatile Memory

8/12/2019 MCP4261_2OPCION

2/84

MCP414X/416X/424X/426X

DS22059A-page 2 2007 Microchip Technology Inc.

Device Block Diagram

Device Features

Device

#ofPOTs

Wiper

ConfigurationControl

Interface

Memory

Type

WiperLock

Technology

PORWiper

Setting

Resistance (typical)

#ofSteps

VDD

Operating

Range (2)RABOptions (k)Wiper

- RW

()

MCP4131 (3) 1 Potentiometer (1) SPI RAM No Mid-Scale 5.0, 10.0, 50.0, 100.0 75 129 1.8V to 5.5V

MCP4132(3)

1 Rheostat SPI RAM No Mid-Scale 5.0, 10.0, 50.0, 100.0 75 129 1.8V to 5.5VMCP4141 1 Potentiometer (1) SPI EE Yes NV Wiper 5.0, 10.0, 50.0, 100.0 75 129 2.7V to 5.5V

MCP4142 1 Rheostat SPI EE Yes NV Wiper 5.0, 10.0, 50.0, 100.0 75 129 2.7V to 5.5V


MCP4152 (3) 1 Rheostat SPI RAM No Mid-Scale 5.0, 10.0, 50.0, 100.0 75 257 1.8V to 5.5V

MCP4161 1 Potentiometer (1) SPI EE Yes NV Wiper 5.0, 10.0, 50.0, 100.0 75 257 2.7V to 5.5V



MCP4232 (3) 2 Rheostat SPI RAM No Mid-Scale 5.0, 10.0, 50.0, 100.0 75 129 1.8V to 5.5V



MCP4251 (3) 2 Potentiometer (1) SPI RAM No Mid-Scale 5.0, 10.0, 50.0, 100.0 75 257 1.8V to 5.5VMCP4252 (3) 2 Rheostat SPI RAM No Mid-Scale 5.0, 10.0, 50.0, 100.0 75 257 1.8V to 5.5V



Note 1: Floating either terminal (A or B) allows the device to be used as a Rheostat (variable resistor).

2: Analog characteristics only tested from 2.7V to 5.5V unless otherwise noted.

3: Please check Microchip web site for device release and availability

Power-up/Brown-outControl

VDD

VSS

SPI SerialInterfaceModule &ControlLogic(WiperLockTechnology)

ResistorNetwork 0(Pot 0)

Wiper 0& TCONRegister

ResistorNetwork 1(Pot 1)

Wiper 1& TCONRegister

CS

SCK

SDI

SDO

WP

SHDN

Memory (16x9)

Wiper0 (V & NV)Wiper1 (V & NV)

TCON

STATUSData EEPROM(10 x 9-bits)

P0A

P0W

P0B

P1A

P1W

P1B

For Dual Resistor NetworkDevices Only

For Dual PotentiometerDevices Only

8/12/2019 MCP4261_2OPCION

3/84


MCP414X/416X/424X/426X

1.0 ELECTRICALCHARACTERISTICS

Absolute Maximum Ratings

Voltage on VDDwith respect to VSS ............... -0.6V to +7.0V

Voltage on CS, SCK, SDI, SDI/SDO, WP, and

SHDN with respect to VSS...................................... -0.6V to 12.5VVoltage on all other pins (PxA, PxW, PxB, and

SDO) with respect to VSS ............................ -0.3V to VDD+ 0.3VInput clamp current, IIK

(VI< 0, VI> VDD, VI> VPPONHV pins) ......................20 mA

Output clamp current, IOK(VO< 0 or VO> VDD) ..................................................20 mA

Maximum output current sunk by any Output pin

......................................................................................25 mAMaximum output current sourced by any Output pin

......................................................................................25 mA

Maximum current out of VSSpin .................................100 mA

Maximum current into VDDpin ....................................100 mAMaximum current into PXA, PXW & PXB pins ............2.5 mA

Storage temperature .. ............... ............... ....-65C to +150C

Ambient temperature with power applied-40C to +125C

Total power dissipation (Note 1) ................................400 mW

Soldering temperature of leads (10 seconds) ............. +300C

ESD protection on all pins .................................. 4 kV (HBM),.......................................................................... 300V (MM)Maximum Junction Temperature (TJ) .........................+150C

Notice: Stresses above those listed under Maximum

Ratings may cause permanent damage to the device. This is

a stress rating only and functional operation of the device atthose or any other conditions above those indicated in the

operational listings of this specification is not implied.

Exposure to maximum rating conditions for extended periodsmay affect device reliability.

Note 1: Power dissipation is calculated as follows:Pdis = VDDx {IDD- IOH} + {(VDD-VOH) x IOH} + (VOl x IOL)

8/12/2019 MCP4261_2OPCION

4/84

MCP414X/416X/424X/426X


AC/DC CHARACTERISTICS

DC Characteristics

Standard Operating Conditions (unless otherwise specified)

Operating Temperature 40C TA+125C (extended)

All parameters apply across the specified operating ranges unless noted.VDD= +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 kdevices.Typical specifications represent values for V

DD= 5.5V, T

A= +25C.

Parameters Sym Min Typ Max Units Conditions

Supply Voltage VDD 2.7 5.5 V

1.8 2.7 V Serial Interface only.

CS, SDI, SDO,SCK, WP, SHDNpin Voltage Range

VHV VSS 12.5V V VDD4.5V

The CS pin will be at oneof three input levels(VIL, VIHor VIHH). (Note 6)VSS VDD+

8.0VV VDD VBOR)

TBORD 10 20 S

Supply Current(Note 10)

IDD 450 A Serial Interface Active,VDD= 5.5V, CS = VIL, SCK @ 5 MHz,write all 0s to volatile Wiper 0 (address0h)

1 mA EE Write Current,VDD= 5.5V, CS = VIL, SCK @ 5 MHz,write all 0s to non-volatile Wiper 0

(address 2h)

2.5 5 A Serial Interface Inactive,CS = VIH, VDD= 5.5V

0.55 1 mA Serial Interface Active,VDD= 5.5V, CS = VIHH,SCK @ 5 MHz,decrement non-volatile Wiper 0(address 2h)

Note 1: Resistance is defined as the resistance between terminal A to terminal B.

2: INL and DNL are measured at VW with VA= VDDand VB= VSS.3: MCP4XX1only.

4: MCP4XX2only, includes VWZSEand VWFSE.

5: Resistor terminals A, W and Bs polarity with respect to each other is not restricted.6: This specification by design.

7: Non-linearity is affected by wiper resistance (RW), which changes significantly over voltage andtemperature.

8: The MCP4XX1is externally connected to match the configurations of the MCP41X2and MCP42X2, andthen tested.

9: POR/BOR is not rate dependent.

10: Supply current is independent of current through the resistor network

8/12/2019 MCP4261_2OPCION

5/84


MCP414X/416X/424X/426X

Resistance( 20%)

RAB 4.0 5 6.0 k -502 devices(Note 1)

8.0 10 12.0 k -103 devices(Note 1)

40.0 50 60.0 k -503 devices(Note 1)

80.0 100 120.0 k -104 devices(Note 1)

Resolution N 257 Taps 8-bit No Missing Codes

129 Taps 7-bit No Missing Codes

Step Resistance RS RAB/(256)

8-bit Note 6

RAB/(128)

7-bit Note 6

NominalResistance Match

|RAB0- RAB1|/ RAB

0.2 1.25 % MCP42X1devices only

|RBW0- RBW1|/ RBW

0.25 1.5 % MCP42X2devices only,Code = Full-Scale

Wiper Resistance(Note 3, Note 4)

RW 75 160 VDD= 5.5 V, IW= 2.0 mA, code = 00h

75 300 VDD= 2.7 V, IW= 2.0 mA, code = 00h

NominalResistanceTempco

RAB/T 50 ppm/C TA= -20C to +70C

100 ppm/C TA= -40C to +85C

150 ppm/C TA= -40C to +125C

RatiometericTempco

VWB/T 15 ppm/C Code = Midscale (80h or 40h)

Resistor TerminalInput VoltageRange (Terminals

A, B and W)

VA,VW,VB Vss VDD V Note 5, Note 6

Maximum currentthrough A, W or B

IW 2.5 mA Note 6, Worst case current throughwiper when wiper is either Full Scale orZero Scale.

Leakage currentinto A, W or B

IWL 100 nA MCP4XX1PxA = PxW = PxB = VSS

100 nA MCP4XX2PxB = PxW = VSS

AC/DC CHARACTERISTICS (CONTINUED)

DC Characteristics



All parameters apply across the specified operating ranges unless noted.VDD= +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 kdevices.Typical specifications represent values for VDD= 5.5V, TA= +25C.


No te 1: Resistance is defined as the resistance between terminal A to terminal B.


4: MCP4XX2only, includes VWZSEand VWFSE.5: Resistor terminals A, W and Bs polarity with respect to each other is not restricted.

6: This specification by design.





8/12/2019 MCP4261_2OPCION

6/84

MCP414X/416X/424X/426X


Full-Scale Error(MCP4XX1only)(8-bit code =100h,7-bit code = 80h)

VWFSE -6.0 -0.1 LSb 5 k 8-bit 3.0V VDD5.5V

-4.0 -0.1 LSb 7-bit 3.0V VDD5.5V

-3.5 -0.1 LSb 10 k 8-bit 3.0V VDD5.5V

-2.0 -0.1 LSb 7-bit 3.0V VDD5.5V

-0.8 -0.1 LSb 50 k 8-bit 3.0V VDD5.5V

-0.5 -0.1 LSb 7-bit 3.0V VDD5.5V

-0.5 -0.1 LSb 100 k 8-bit 3.0V VDD5.5V

-0.5 -0.1 LSb 7-bit 3.0V VDD5.5V

Zero-Scale Error

(MCP4XX1only)(8-bit code = 00h,7-bit code = 00h)

VWZSE +0.1 +6.0 LSb 5 k 8-bit 3.0V VDD5.5V

+0.1 +3.0 LSb 7-bit +0.1 +3.5 LSb 10 k 8-bit 3.0V VDD5.5V

+0.1 +2.0 LSb 7-bit

+0.1 +0.8 LSb 50 k 8-bit 3.0V VDD5.5V

+0.1 +0.5 LSb 7-bit

+0.1 +0.5 LSb 100 k 8-bit 3.0V VDD5.5V

+0.1 +0.5 LSb 7-bit

PotentiometerIntegralNon-linearity

INL -1 0.5 +1 LSb 8-bit 3.0V VDD5.5VMCP4XX1devices only(Note 2)

-0.5 0.25 +0.5 LSb 7-bit

PotentiometerDifferentialNon-linearity

DNL -0.5 0.25 +0.5 LSb 8-bit 3.0V VDD5.5VMCP4XX1devices only(Note 2)-0.25 0.125 +0.25 LSb 7-bit

Bandwidth -3 dB(See Figure 2-58,load = 30 pF)

BW 2 MHz 5 k 8-bit Code = 80h

2 MHz 7-bit Code = 40h

1 MHz 10 k 8-bit Code = 80h

1 MHz 7-bit Code = 40h

200 kHz 50 k 8-bit Code = 80h

200 kHz 7-bit Code = 40h

100 kHz 100 k 8-bit Code = 80h

100 kHz 7-bit Code = 40h


DC Characteristics






2: INL and DNL are measured at VW

with VA

= VDD

and VB= V

SS.3: MCP4XX1only.


5: Resistor terminals A, W and Bs polarity with respect to each other is not restricted.






8/12/2019 MCP4261_2OPCION

7/84


MCP414X/416X/424X/426X

Rheostat IntegralNon-linearityMCP41X1(Note 4, Note 8)MCP4XX2devices only(Note 4)

R-INL -1.5 0.5 +1.5 LSb 5 k 8-bit 5.5V, IW= 900 A

-8.25 +4.5 +8.25 LSb 3.0V, IW= 480 A(Note 7)

-1.125 0.5 +1.125 LSb 7-bit 5.5V, IW= 900 A

-6.0 +4.5 +6.0 LSb 3.0V, IW= 480 A(Note 7)

-1.5 0.5 +1.5 LSb 10 k 8-bit 5.5V, IW= 450 A

-5.5 +2.5 +5.5 LSb 3.0V, IW= 240 A(Note 7)

-1.125 0.5 +1.125 LSb 7-bit 5.5V, IW= 450 A

-4.0 +2.5 +4.0 LSb 3.0V, IW= 240 A(Note 7)

-1.5 0.5 +1.5 LSb 50 k 8-bit 5.5V, IW= 90 A

-2.0 +1 +2.0 LSb 3.0V, IW= 48 A(Note 7)

-1.125 0.5 +1.125 LSb 7-bit 5.5V, IW= 90 A

-1.5 +1 +1.5 LSb 3.0V, IW= 48 A(Note 7)

-1.0 0.5 +1.0 LSb 100 k 8-bit 5.5V, IW= 45 A

-1.5 +0.25 +1.5 LSb 3.0V, IW= 24 A(Note 7)

-0.8 0.5 +0.8 LSb 7-bit 5.5V, IW= 45 A-1.125 +0.25 +1.125 LSb 3.0V, IW= 24 A

(Note 7)


DC Characteristics











8: The MCP4XX1is externally connected to match the configurations of the MCP41X2and MCP42X2, and

then tested.9: POR/BOR is not rate dependent.


8/12/2019 MCP4261_2OPCION

8/84

MCP414X/416X/424X/426X


RheostatDifferentialNon-linearityMCP41X1(Note 4, Note 8)MCP4XX2devices only(Note 4)

R-DNL -0.5 0.25 +0.5 LSb 5 k 8-bit 5.5V, IW= 900 A

-1.0 +0.5 +1.0 LSb 3.0V (Note 7)

-0.375 0.25 +0.375 LSb 7-bit 5.5V, IW= 900 A

-0.75 +0.5 +0.75 LSb 3.0V (Note 7)

-0.5 0.25 +0.5 LSb 10 k 8-bit 5.5V, IW= 450 A

-1.0 +0.25 +1.0 LSb 3.0V (Note 7)

-0.375 0.25 +0.375 LSb 7-bit 5.5V, IW= 450 A

-0.75 +0.5 +0.75 LSb 3.0V (Note 7)

-0.5 0.25 +0.5 LSb 50 k 8-bit 5.5V, IW= 90 A

-0.5 0.25 +0.5 LSb 3.0V (Note 7)-0.375 0.25 +0.375 LSb 7-bit 5.5V, IW= 90 A

-0.375 0.25 +0.375 LSb 3.0V (Note 7)

-0.5 0.25 +0.5 LSb 100 k 8-bit 5.5V, IW= 45 A

-0.5 0.25 +0.5 LSb 3.0V (Note 7)

-0.375 0.25 +0.375 LSb 7-bit 5.5V, IW= 45 A

-0.375 0.25 +0.375 LSb 3.0V (Note 7)

Capacitance (PA) CAW 75 pF f =1 MHz, Code = Full-Scale

Capacitance (Pw) CW 120 pF f =1 MHz, Code = Full-Scale

Capacitance (PB) CBW 75 pF f =1 MHz, Code = Full-Scale


DC Characteristics














8/12/2019 MCP4261_2OPCION

9/84


MCP414X/416X/424X/426X

Digi tal Inputs/Outputs (CS, SDI, SDO, SCK, WP, SHDN)

Schmitt TriggerHigh InputThreshold

VIH 0.45 VDD V 2.7V VDD5.5V(Allows 2.7V Digital VDDwith5V Analog VDD)

0.5 VDD V 1.8V VDD2.7V

Schmitt TriggerLow InputThreshold

VIL 0.2VDD V

Hysteresis ofSchmitt TriggerInputs

VHYS 0.1VDD V

High Voltage InputEntry Voltage

VIHH 8.5 12.5(6) V Threshold for WiperLock Technology

High Voltage InputExit Voltage

VIHH VDD+0.8V (6)

V

High Voltage Limit VMAX 12.5(6) V Pin can tolerate VMAXor less.

Output LowVoltage (SDO)

VOL VSS 0.3VDD V IOL= 5 mA, VDD= 5.5V

VSS 0.3VDD V IOL= 1 mA, VDD= 1.8V

Output HighVoltage (SDO)

VOH 0.7VDD VDD V IOH= -2.5 mA, VDD= 5.5V

0.7VDD VDD V IOL= -1 mA, VDD= 1.8V

Weak Pull-up /Pull-down Current

IPU 375 uA Internal VDDpull-up, VIHHpull-down

170 A CS pin, VDD = 5.5V, VCS= 3V

CS Pull-up /Pull-downResistance

RCS 16 k VDD = 5.5V, VCS= 3V

Input LeakageCurrent

IIL -1 1 A VIN= VDDand VIN= VSS

Pin Capacitance CIN, COUT 10 pF fC = 20 MHz

RAM (Wiper) Value

Value Range N 0h 1FFh hex 8-bit device

0h 1FFh hex 7-bit device


DC Characteristics






2: INL and DNL are measured at VW with VA= VDDand VB= VSS.

3: MCP4XX1only.4: MCP4XX2only, includes VWZSEand VWFSE.







8/12/2019 MCP4261_2OPCION

10/84

MCP414X/416X/424X/426X


EEPROM

Endurance Endurance 1M Cycles

EEPROM Range N 0h 1FFh hex

Initial FactorySetting

N 80h hex 8-bit WiperLock Technology = Off

40h hex 7-bit WiperLock Technology = Off

EEPROM Pro-gramming WriteCycle Time

tWC 5 10 ms

Power Requirements

Power SupplySensitivity(MCP41X2andMCP42X2only)

PSS 0.0015 0.0035 %/% 8-bit VDD

= 2.7V to 5.5V,VA= 2.7V, Code = 80h

0.0015 0.0035 %/% 7-bit VDD= 2.7V to 5.5V,VA= 2.7V, Code = 40h


DC Characteristics














8/12/2019 MCP4261_2OPCION

11/84


MCP414X/416X/424X/426X

1.1 SPI Mode Timing Waveforms and Requirements

FIGURE 1-1: SPI Timing Waveform (Mode = 11).

TABLE 1-1: SPI REQUIREMENTS (MODE = 11)

# Characteristic Symbol Min Max Units Conditions

SCK Input Frequency FSCK 10 MHz VDD= 2.7V to 5.5V

1 MHz VDD= 1.8V to 2.7V

70 CS Active (VILor VIHH) to SCKinput TcsA2scH 60 ns

71 SCK input high time TscH 45 ns VDD= 2.7V to 5.5V

500 ns VDD= 1.8V to 2.7V

72 SCK input low time TscL 45 ns VDD= 2.7V to 5.5V

500 ns VDD= 1.8V to 2.7V

73 Setup time of SDI input to SCKedge TDIV2scH 10 ns

74 Hold time of SDI input from SCKedge TscH2DIL 20 ns

77 CS Inactive (VIH) to SDO output hi-impedance TcsH2DOZ 50 ns Note 1

80 SDO data output valid after SCKedge TscL2DOV 70 ns VDD= 2.7V to 5.5V

170 ns VDD= 1.8V to 2.7V

83 CS Inactive (VIH) after SCKedge TscH2csI 100 ns VDD= 2.7V to 5.5V

1 ms VDD= 1.8V to 2.7V

84 Hold time of CS Inactive (VIH) toCS Active (VILor VIHH)

TcsA2csI 50 ns

Note 1: This specification by design.

CS

SCK

SDO

SDI

70

71

72

7374

75, 76 77

787980

SDI

MSb LSbBIT6 - - - - - -1

MSb IN BIT6 - - - -1 LSb IN

83

84

VIH

VIL

VIHHVIH

8/12/2019 MCP4261_2OPCION

12/84

MCP414X/416X/424X/426X


FIGURE 1-2: SPI Timing Waveform (Mode = 00).

TABLE 1-2: SPI REQUIREMENTS (MODE = 00)

# Characteristic Symbol Min Max Units Conditions

SCK Input Frequency FSCK 10 MHz VDD= 2.7V to 5.5V

1 MHz VDD= 1.8V to 2.7V

70 CS Active (VILor VIHH) to SCKinput TcsA2scH 60 ns

71 SCK input high time TscH 45 ns VDD= 2.7V to 5.5V

500 ns VDD= 1.8V to 2.7V

72 SCK input low time TscL 45 ns VDD= 2.7V to 5.5V

500 ns VDD= 1.8V to 2.7V

73 Setup time of SDI input to SCKedge TDIV2scH 10 ns

74 Hold time of SDI input from SCKedge TscH2DIL 20 ns77 CS Inactive (VIH) to SDO output hi-impedance TcsH2DOZ 50 ns Note 1

80 SDO data output valid after SCKedge TscL2DOV 70 ns VDD= 2.7V to 5.5V

170 ns VDD= 1.8V to 2.7V

82 SDO data output valid afterCS Active (VILor VIHH)

TssL2doV 70 ns

83 CS Inactive (VIH) after SCKedge TscH2csI 100 ns VDD= 2.7V to 5.5V

1 ms VDD= 1.8V to 2.7V

84 Hold time of CS Inactive (VIH) toCS Active (VILor VIHH)

TcsA2csI 50 ns

Note 1: This specification by design.

CS

SCK

SDO

SDI

70

71 72

82

SDI

74

75, 76

MSb BIT6 - - - - - -1 LSb

77

MSb IN BIT6 - - - -1 LSb IN

80

83

84

73

VIH

VIL

VIHHVIH

8/12/2019 MCP4261_2OPCION

13/84

8/12/2019 MCP4261_2OPCION

14/84

MCP414X/416X/424X/426X


TEMPERATURE CHARACTERISTICS

Electrical Specifications:Unless otherwise indicated, VDD = +2.7V to +5.5V, VSS = GND.


Temperature Ranges

Specified Temperature Range TA -40 +125 C

Operating Temperature Range TA -40 +125 CStorage Temperature Range TA -65 +150 C

Thermal Package Resistances

Thermal Resistance, 8L-PDIP JA 84.6 C/W

Thermal Resistance, 8L-SOIC JA 145.5 C/W

Thermal Resistance, 8L-MSOP JA 211 C/W

Thermal Resistance, 8L-DFN (3x3) JA 68.5 C/W

Thermal Resistance, 10L-PDIP JA 82 C/W

Thermal Resistance, 10L-MSOP JA 202 C/W

Thermal Resistance, 14L-PDIP JA 70 C/W

Thermal Resistance, 14L-SOIC JA 85 C/W

Thermal Resistance, 14L-MSOP JA N/A C/WThermal Resistance, 16L-QFN JA 50 C/W

8/12/2019 MCP4261_2OPCION

15/84


MCP414X/416X/424X/426X

2.0 TYPICAL PERFORMANCE CURVES

Note:Unless otherwise indicated, TA= +25C, VDD= 5V, VSS= 0V.

FIGURE 2-1: Device Current (IDD) vs. SPI

Frequency (fSCK) and Ambient Temperature

(VDD = 2.7V and 5.5V).

FIGURE 2-2: Device Current (ISHDN) and

VDD. (CS = VDD) vs. Ambient Temperature.

FIGURE 2-3: Write Current (IWRITE) vs.

Ambient Temperature and VDD.

FIGURE 2-4: CS Pull-up/Pull-down

Resistance (RCS) and Current (ICS) vs. CS Input

Voltage (VCS) (VDD = 5.5V).

FIGURE 2-5: CS High Input Entry/Exit

Threshold vs. Ambient Temperature and VDD.

Note: The graphs and tables provided following this note are a statistical summary based on a limited number ofsamples and are provided for informational purposes only. The performance characteristics listed hereinare not tested or guaranteed. In some graphs or tables, the data presented may be outside the specifiedoperating range (e.g., outside specified power supply range) and therefore outside the warranted range.

050

100150200250300350400450500550600650

0.00 2.00 4.00 6.00 8.00 10.00 12.00

fSCK(MHz)

OperatingCurrent(IDD)(A) 2.7V -40C

2.7V 25C2.7V 85C2.7V 125C5.5V -40C5.5V 25C5.5V 85C5.5V 125C

0.0

0.5

1.0

1.5

2.0

2.5

3.0

-40 25 85 125

Ambien t Temperatu re (C)

Stan

dbyCurrent(Istby)(A)

5.5V

2.7V

300.0

400.0

500.0

600.0

700.0

800.0

900.0

-40 25 85 125

Ambien t Tem perature (C)

EEWriteCur

rent(Iwrite)(A)

5.5V

0

50

100

150

200

250

2 3 4 5 6 7 8 9 10VCS(V)

RCS(kOhms)

-1000

-800

-600

-400

-200

0

200

400

600

800

1000

ICS(A)ICS

RCS

0

2

4

6

8

10

12

-40 -20 0 20 40 60 80 100 120

Ambien t Temperature (C)

CSVPPThreshold(V)

2.7V Exit

5.5V Exit

2.7V Entry5.5V Entry

8/12/2019 MCP4261_2OPCION

16/84

8/12/2019 MCP4261_2OPCION

17/84


MCP414X/416X/424X/426X


FIGURE 2-12: 5 k Low-Voltage

Decrement Wiper Settling Time (VDD = 2.7V)

(1 s/Div).


Decrement Wiper Settling Time (VDD= 5.5V)

(1 s/Div).

FIGURE 2-14: 5 k Power-Up Wiper

Response Time (20 ms/Div).


Increment Wiper Settling Time (VDD= 2.7V)

(1 s/Div).



(1 s/Div).

8/12/2019 MCP4261_2OPCION

18/84

8/12/2019 MCP4261_2OPCION

19/84


MCP414X/416X/424X/426X




(1 s/Div).



(1 s/Div).



(1 s/Div).



(1 s/Div).

8/12/2019 MCP4261_2OPCION

20/84

8/12/2019 MCP4261_2OPCION

21/84


MCP414X/416X/424X/426X




(1 s/Div).



(1 s/Div).


Increment Wiper Settling Time (VDD = 2.7V)

(1 s/Div).



(1 s/Div).

8/12/2019 MCP4261_2OPCION

22/84

8/12/2019 MCP4261_2OPCION

23/84


MCP414X/416X/424X/426X




(1 s/Div).



(1 s/Div).

M

FIGURE 2-45: 100 k Power-Up Wiper

Response Time (1 s/Div).



(1 s/Div).

8/12/2019 MCP4261_2OPCION

24/84

MCP414X/416X/424X/426X



FIGURE 2-47: Resistor Network 0 to

Resistor Network 1 RAB(5 k) Mismatch vs. VDD

and Temperature.


Resistor Network 1 RAB(10 k) Mismatch vs.

VDDand Temperature.



VDDand Temperature.



VDDand Temperature.

0

0.01

0.02

0.03

0.04

0.05

0.06

0.07

0.08

0.09

0.1

-40 0 40 80 120

Temperature (C)

%

5.5V

3.0V

-0.04

-0.03

-0.02

-0.01

0

0.01

0.02

0.030.04

-40 0 40 80 120

Temperature (C)

%

5.5V

3.0V

0

0.02

0.04

0.06

0.08

0.1

0.12

-40 0 40 80 120Temperature (C)

%

5.5V

3.0V

-0.03

-0.02

-0.01

0

0.01

0.02

0.03

0.040.05

-40 10 60 110Temperature (C)

%

5.5V

3.0V

8/12/2019 MCP4261_2OPCION

25/84


MCP414X/416X/424X/426X


FIGURE 2-51: VIH(SDI, SCK, CS, WP, and

SHDN) vs. VDDand Temperature.

FIGURE 2-52: VIL(SDI, SCK, CS, WP, and

SHDN) vs. VDDand Temperature.

FIGURE 2-53: IOH(SDO) vs. VDDand

Temperature.

FIGURE 2-54: IOL(SDO) vs. VDDand

Temperature.

1

1.2

1.4

1.6

1.8

2

2.2

2.4

-40 0 40 80 120

Temperature (C)

VIH

(V)

5.5V

2.7V

0.6

0.7

0.8

0.9

1

1.1

1.2

1.3

1.4

-40 0 40 80 120

Temperature (C)

VIL(V)

5.5V

2.7V

-45

-40

-35

-30

-25

-20

-15

-10

-5

0

-40 0 40 80 120

Temperature (C)

IOH(mA)

5.5V

2.7V

0

5

10

15

20

25

30

3540

45

50

-40 0 40 80 120

Temperature (C)

IOL(mA)

5.5V

2.7V

8/12/2019 MCP4261_2OPCION

26/84

MCP414X/416X/424X/426X


Note:Unless otherwise indicated, TA= +25C, VDD=5V, VSS= 0V.

FIGURE 2-55: Nominal EEPROM Write

Cycle Time vs. VDDand Temperature.

FIGURE 2-56: POR/BOR Trip point vs. VDD

and Temperature.

FIGURE 2-57: SCK Input Frequency vs.

Voltage and Temperature.

2.1 Test Circuits

FIGURE 2-58: -3 db Gain vs. Frequency

Test.

3.0

3.2

3.4

3.6

3.8

4.0

4.2

-40 0 40 80 120

Temperature (C)

tWC

(ms)

0

0.2

0.4

0.6

0.8

1

1.2

-40 0 40 80 120

Temperature (C)

VDD(V)

2.7V

5.5V

12.0

12.5

13.0

13.5

14.0

14.5

15.0

-40 0 40 80 120

Temperature (C)

fsck(MHz)

2.7V

5.5V

+-

VOUT

2.5V DC

+5V

A

BW

OffsetGND

VIN

8/12/2019 MCP4261_2OPCION

27/84


MCP414X/416X/424X/426X

3.0 PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 3-1.Additional descriptions of the device pins follows.

TABLE 3-1: PINOUT DESCRIPTION FOR THE MCP414X/416X/424X/426X

Pin

Weak

Pull-up/

down (2)Standard Function

Single Dual

Symbol I/OBuffer

TypeRheo Pot (1) Rheo Pot

8L 8L 10L 14L 16L

1 1 1 1 16 CS I HV w/ST smart SPI Chip Select Input

2 2 2 2 1 SCK I HV w/ST smart SPI Clock Input

3 3 3 2 SDI I HV w/ST smart SPI Serial Data Input

3 SDI/SDO(1, 3) I/O HV w/ST smart SPI Serial Data Input/Output

4 4 4 4 3, 4 VSS P Ground

5 5 5 P1B A Analog No Potentiometer 1 Terminal B

6 6 6 P1W A Analog No Potentiometer 1 Wiper Terminal

7 7 P1A A Analog No Potentiometer 1 Terminal A

5 8 8 P0A A Analog No Potentiometer 0 Terminal A

5 6 7 9 9 P0W A Analog No Potentiometer 0 Wiper Terminal

6 7 8 10 10 P0B A Analog No Potentiometer 0 Terminal B

11 12 WP I I smart Hardware EEPROM WriteProtect

12 13 SHDN I HV w/ST smart Hardware Shutdown

7 9 13 14 SDO O O No SPI Serial Data Out

8 8 10 14 15 VDD P Positive Power Supply Input 11 NC No Connection

(4) (4) (4) (4) Exposed Pad Note 4

Legend: HV w/ST = High Voltage tolerant input (with Schmidtt trigger input)A = Analog pins (Potentiometer terminals) I = digital input (high Z)O = digital output I/O = Input / OutputP = Power

Note 1: The 8-lead Single Potentiometer devices are pin limited so the SDO pin is multiplexed with the SDI pin(SDI/SDO pin). After the Address/Command (first 6-bits) are received, If a valid Read command has beenrequested, the SDO pin starts driving the requested read data onto the SDI/SDO pin.

2: The pins smart pull-up shuts off while the pin is forced low. This is done to reduce the standby and shut-down current.

3: The SDO is an open drain output, which uses the internal smart pull-up. The SDI input data rate can beat the maximum SPI frequency. the SDO output data rate will be limited by the speed of the pull-up, cus-tomers can increase the rate with external pull-up resistors.

4: The DFN and QFN packages have a contact on the bottom of the package. This contact is conductivelyconnected to the die substrate, and therefore should be unconnected or connected to the same ground asthe devices VSSpin.

8/12/2019 MCP4261_2OPCION

28/84

MCP414X/416X/424X/426X


3.1 Chip Select (CS)

The CS pin is the serial interfaces chip select input.Forcing the CS pin to VILenables the serial commands.Forcing the CS pin to VIHHenables the high-voltageserial commands.

3.2 Ser ial Data In (SDI)The SDI pin is the serial interfaces Serial Data In pin.This pin is connected to the Host Controllers SDO pin.

3.3 Serial Data In / Serial Data Out

(SDI/SDO)

On the MCP41X1 devices, pin-out limitations do notallow for individual SDI and SDO pins. On thesedevices, the SDI and SDO pins are multiplexed.

The MCP41X1 serial interface knows when the pinneeds to change from being an input (SDI) to being anoutput (SDO). The Host Controllers SDO pin must be

properly protected from a drive conflict.

3.4 Ground (VSS)

The VSSpin is the device ground reference.

3.5 Potentiometer Terminal B

The terminal B pin is connected to the internal potenti-ometers terminal B.

The potentiometers terminal B is the fixed connectionto the Zero Scale wiper value of the digital potentiome-ter. This corresponds to a wiper value of 0x00 for both7-bit and 8-bit devices.

The terminal B pin does not have a polarity relative tothe terminal W or A pins. The terminal B pin cansupport both positive and negative current. The voltageon terminal B must be between VSSand VDD.

MCP42XX devices have two terminal B pins, one foreach resistor network.

3.6 Potentiometer Wiper (W) Terminal

The terminal W pin is connected to the internal potenti-ometers terminal W (the wiper). The wiper terminal isthe adjustable terminal of the digital potentiometer. Theterminal W pin does not have a polarity relative to

terminals A or B pins. The terminal W pin can supportboth positive and negative current. The voltage onterminal W must be between VSSand VDD.

MCP42XX devices have two terminal W pins, one foreach resistor network.

3.7 Potentiometer Terminal A

The terminal A pin is available on the MCP4XX1devices, and is connected to the internal potentiome-ters terminal A.

The potentiometers terminal A is the fixed connectionto the Full Scale wiper value of the digital potentiome-

ter. This corresponds to a wiper value of 0x100 for 8-bitdevices or 0x80 for 7-bit devices.

The terminal A pin does not have a polarity relative tothe terminal W or B pins. The terminal A pin cansupport both positive and negative current. The voltageon terminal A must be between VSSand VDD.

The terminal A pin is not available on the MCP4XX2devices, and the internally terminal A signal is floating.

MCP42X1 devices have two terminal A pins, one foreach resistor network.

3.8 Wr ite Pro tec t (WP)

The WP pin is used to force the non-volatile memory tobe write protected.

3.9 Shutdown (SHDN)

The SHDN pin is used to force the resistor networkterminals into the hardware shutdown state.

3.10 Serial Data Out (SDO)

The SDO pin is the serial interfaces Serial Data Out pin.This pin is connected to the Host Controllers SDI pin.

This pin allows the Host Controller to read the digitalpotentiometers registers, or monitor the state of the

command error bit.

3.11 Positive Power Supply Input (VDD)

The VDDpin is the devices positive power supply input.The input power supply is relative to VSS.

While the device VDD < Vmin (2.7V), the electricalperformance of the device may not meet the data sheetspecifications.

8/12/2019 MCP4261_2OPCION

29/84


MCP414X/416X/424X/426X

4.0 FUNCTIONAL OVERVIEW

This Data Sheet covers a family of thirty-two DigitalPotentiometer and Rheostat devices that will bereferred to as MCP4XXX. The MCP4XX1 devices arethe Potentiometer configuration, while the MCP4XX2devices are the Rheostat configuration.

As the Device Block Diagramshows, there are fourmain functional blocks. These are:

POR/BOR Operation

Memory Map

Resistor Network

Serial Interface (SPI)

The POR/BOR operation and the Memory Map arediscussed in this section and the Resistor Network andSPI operation are described in their own sections. TheDevice Commands commands are discussed inSection 7.0.

4.1 POR/BOR Operat ionThe Power-on Reset is the case where the device ishaving power applied to it from VSS. The Brown-outReset occurs when a device had power applied to it,and that power (voltage) drops below the specifiedrange.

The devices RAM retention voltage (VRAM) is lowerthan the POR/BOR voltage trip point (VPOR/VBOR). Themaximum VPOR/VBORvoltage is less then 1.8V.

When VPOR/VBOR < VDD < 2.7V, the electricalperformance may not meet the data sheetspecifications. In this region, the device is capable ofreading and writing to its EEPROM and incrementing,

decrementing, reading and writing to its volatilememory if the proper serial command is executed.

4.1.1 POWER-ON RESET

When the device powers up, the device VDDwill crossthe VPOR/VBORvoltage. Once the VDDvoltage crossesthe VPOR/VBORvoltage the following happens:

Volatile wiper register is loaded with value in thecorresponding non-volatile wiper register

The TCON register is loaded its default value

The device is capable of digital operation

4.1.2 BROWN-OUT RESET

When the device powers down, the device VDD willcross the VPOR/VBORvoltage.

Once the VDDvoltage decreases below the VPOR/VBORvoltage the following happens:

Serial Interface is disabled

EEPROM Writes are disabled

If the VDDvoltage decreases below the VRAMvoltagethe following happens:

Volatile wiper registers may become corrupted

TCON register may become corrupted

As the voltage recovers above the VPOR/VBORvoltagesee Section 4.1.1 Power-on Reset .

Serial commands not completed due to a brown-outcondition may cause the memory location (volatile andnon-volatile) to become corrupted.

4.2 Memory Map

The device memory is 16 locations that are 9-bits wide(16x9 bits). This memory space contains both volatileand non-volatile locations (see Table 4-1).

TABLE 4-1: MEMORY MAP

Address Funct ion Memory Type

00h Volatile Wiper 0 RAM

01h Volatile Wiper 1 RAM

02h Non-Volatile Wiper 0 EEPROM

03h Non-Volatile Wiper 1 EEPROM

04h Volatile TCON Register RAM

05h Status Register RAM06h Data EEPROM EEPROM

07h Data EEPROM EEPROM



0Ah Data EEPROM EEPROM

0Bh Data EEPROM EEPROM

0Ch Data EEPROM EEPROM

0Dh Data EEPROM EEPROM

0Eh Data EEPROM EEPROM

0Fh Data EEPROM EEPROM

8/12/2019 MCP4261_2OPCION

30/84

MCP414X/416X/424X/426X


4.2.1 NON-VOLATILE MEMORY(EEPROM)

This memory can be grouped into two uses of non-vol-atile memory. These are:

General Purpose Registers Non-Volatile Wiper Registers

The non-volatile wipers starts functioning below thedevices VPOR/VBORtrip point.

4.2.1.1 General Purpose Registers

These locations allow the user to store up to 10 (9-bit)locations worth of information.

4.2.1.2 Non-Volatile Wiper Registers

These locations contain the wiper values that areloaded into the corresponding volatile wiper registerwhenever the device has a POR/BOR event. There areup to two registers, one for each resistor network.

The non-volatile wiper register enables stand-alone

operation of the device (without Microcontroller control)after being programmed to the desired value.

4.2.1.3 Factory Initialization of Non-VolatileMemory (EEPROM)

The Non-Volatile Wiper values will be initialized tomid-scale value. This is shown in Table 4-2.

The General purpose EEPROM memory will beprogrammed to a default value of 0xFF.

It is good practice in the manufacturing flow toconfigure the device to your desired settings.

TABLE 4-2: DEFAULT FACTORYSETTINGS SELECTION

4.2.1.4 Special Features

There are 3 non-volatile bits that are not directlymapped into the address space. These bits control thefollowing functions:

EEPROM Write Protect

WiperLock Technology for Non-Volatile Wiper 0

WiperLock Technology for Non-Volatile Wiper 1

The operation of WiperLock Technology is discussed inSection 5.3. The state of the WL0, WL1, and WP bitsis reflected in the STATUS register (see Register 4-1).

EEPROM Write Protect

All internal EEPROM memory can be Write Protected.When EEPROM memory is Write Protected, Writecommands to the internal EEPROM are prevented.

Write Protect (WP) can be enabled/disabled by twomethods. These are:

External WP Hardware pin (MCP42X1 devices

only) Non-Volatile configuration bit

High Voltage commands are required to enable anddisable the nonvolatile WP bit. These commands areshown in Section 7.9 Modify Write Protect or Wip-erLock Technology (High Voltage) .

To write to EEPROM, both the external WP pin and theinternal WP EEPROM bit must be disabled. WriteProtect does not block commands to the volatileregisters.

4.2.2 VOLATILE MEMORY (RAM)

There are four Volatile Memory locations. These are:

Volatile Wiper 0

Volatile Wiper 1(Dual Resistor Network devices only)

Status Register

Terminal Control (TCON) Register

The volatile memory starts functioning at the RAMretention voltage (VRAM).R

esistance

Code

Typical

RABValue

DefaultPOR

WiperSetting

Wiper

Code

WiperLock

Technologyand

WriteProtectSetting

8-b it 7-b it

-502 5.0 k Mid-scale 80h 40h Disabled




8/12/2019 MCP4261_2OPCION

31/84


MCP414X/416X/424X/426X

4.2.2.1 Status (STATUS) Register

This register contains 5 status bits. These bits show thestate of the WiperLock bits, the Shutdown bit the WriteProtect bit, and if an EEPROM write cycle is active. The

STATUS register can be accessed via the READcommands. Register 4-1 describes each STATUSregister bit.

The STATUS register is placed at Address 05h.

REGISTER 4-1: STATUS REGISTER

R-1 R-1 R-1 R-1 R-0 R-x R-x R-x R-x

D8:D5 EEWA WL1 (1) WL0 (1) SHDN WP (1)

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as 0

-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown

bit 8-5 D8:D5: Reserved. Forced to 1

bit 4 EEWA: EEPROM Write Active Status bit

This bit indicates if the EEPROM Write Cycle is occurring.

1= An EEPROM Write cycle is currently occurring. Only serial commands to the Volatile memorylocations are allowed (addresses 00h, 01h, 04h, and 05h)

0= An EEPROM Write cycle is NOT currently occurring

bit 3 WL1: WiperLock Status bit for Resistor Network 1 (Refer to Section 5.3 WiperLock Technology for further information)

WiperLock (WL) prevents the Volatile and Non-Volatile Wiper 1 addresses and the TCON register bitsR1HW, R1A, R1W, and R1B from being written to. High Voltage commands are required to enable anddisable WiperLock Technology.1= Wiper and TCON register bits R1HW, R1A, R1W, and R1B of Resistor Network 1 (Pot 1) are

Locked (Write Protected)0= Wiper and TCON of Resistor Network 1 (Pot 1) can be modified

Note: The WL1 bit always reflects the result of the last programming cycle to the non-volatile WL1bit. After a POR or BOR event, the WL1 bit is loaded with the non-volatile WL1 bit value.

bit 2 WL0: WiperLock Status bit for Resistor Network 0 (Refer to Section 5.3 WiperLock Technology for further information)

The WiperLock Technology bits (WLx) prevents the Volatile and Non-Volatile Wiper 0 addresses and theTCON register bits R0HW, R0A, R0W, and R0B from being written to. High Voltage commands arerequired to enable and disable WiperLock Technology.1= Wiper and TCON register bits R0HW, R0A, R0W, and R0B of Resistor Network 0 (Pot 0) are

Locked (Write Protected)0= Wiper and TCON of Resistor Network 0 (Pot 0) can be modified

Note: The WL0 bit always reflects the result of the last programming cycle to the non-volatile WL0bit. After a POR or BOR event, the WL0 bit is loaded with the non-volatile WL0 bit value.

bit 1 SHDN: Hardware Shutdown pin Status bit (Refer to Section 5.4 Shutdown for further information)

This bit indicates if the Hardware shutdown pin (SHDN) is low. A hardware shutdown disconnects theTerminal A and forces the wiper (Terminal W) to Terminal B (see Figure 5-2). While the device is in Hard-ware Shutdown (the SHDN pin is low) the serial interface is operational so the STATUS register may beread.1= MCP4XXX is in the Hardware Shutdown state0= MCP4XXX is NOT in the Hardware Shutdown state

Note 1: Requires a High Voltage command to modify the state of this bit (for Non-Volatile devices only). This bit isNot directly written, but reflects the system state (for this feature).

8/12/2019 MCP4261_2OPCION

32/84

MCP414X/416X/424X/426X


bit 0 WP: EEPROM Write Protect Status bit (Refer to Section EEPROM Write Protect for further infor-mation)

This bit indicates the status of the write protection on the EEPROM memory. When Write Protect isenabled, writes to all non-volatile memory are prevented. This includes the General Purpose EEPROMmemory, and the non-volatile Wiper registers. Write Protect does not block modification of the volatile

wiper register values or the volatile TCON register value (via Increment, Decrement, or Writecommands).This status bit is an OR of the devices Write Protect pin (WP) and the internal non-volatile WP bit. HighVoltage commands are required to enable and disable the internal WP EEPROM bit.1= EEPROM memory is Write Protected0= EEPROM memory can be written

REGISTER 4-1: STATUS REGISTER (CONTINUED)

Note 1: Requires a High Voltage command to modify the state of this bit (for Non-Volatile devices only). This bit isNot directly written, but reflects the system state (for this feature).

8/12/2019 MCP4261_2OPCION

33/84


MCP414X/416X/424X/426X

4.2.2.2 Terminal Control (TCON) Register

This register contains 8 control bits. Four bits are forWiper 0, and four bits are for Wiper 1. Register 4-2describes each bit of the TCON register.

The state of each resistor network terminal connectionis individually controlled. That is, each terminal connec-

tion (A, B and W) can be individually connected/discon-nected from the resistor network. This allows thesystem to minimize the currents through the digitalpotentiometer.

The value that is written to this register will appear onthe resistor network terminals when the serial com-mand has completed.

When the WL1 bit is enabled, writes to the TCON reg-ister bits R1HW, R1A, R1W, and R1B are inhibited.

When the WL0 bit is enabled, writes to the TCON reg-

ister bits R0HW, R0A, R0W, and R0B are inhibited.On a POR/BOR this register is loaded with 1FFh(9-bits), for all terminals connected. The Host Control-ler needs to detect the POR/BOR event and thenupdate the Volatile TCON register value.

REGISTER 4-2: TCON BITS (1, 2)

R-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

D8 R1HW R1A R1W R1B R0HW R0A R0W R0B

bit 8 bit 0

Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as 0

-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown

bit 8 D8: Reserved. Forced to 1

bit 7 R1HW: Resistor 1 Hardware Configuration Control bit

This bit forces Resistor 1 into the shutdown configuration of the Hardware pin1= Resistor 1 is NOT forced to the hardware pin shutdown configuration0= Resistor 1 is forced to the hardware pin shutdown configuration

bit 6 R1A: Resistor 1 Terminal A (P1A pin) Connect Control bit

This bit connects/disconnects the Resistor 1 Terminal A to the Resistor 1 Network1= P1A pin is connected to the Resistor 1 Network

0= P1A pin is disconnected from the Resistor 1 Networkbit 5 R1W: Resistor 1 Wiper (P1W pin) Connect Control bit

This bit connects/disconnects the Resistor 1 Wiper to the Resistor 1 Network1= P1W pin is connected to the Resistor 1 Network0= P1W pin is disconnected from the Resistor 1 Network

bit 4 R1B: Resistor 1 Terminal B (P1B pin) Connect Control bit

This bit connects/disconnects the Resistor 1 Terminal B to the Resistor 1 Network1= P1B pin is connected to the Resistor 1 Network0= P1B pin is disconnected from the Resistor 1 Network

bit 3 R0HW: Resistor 0 Hardware Configuration Control bit

This bit forces Resistor 0 into the shutdown configuration of the Hardware pin1= Resistor 0 is NOT forced to the hardware pin shutdown configuration0= Resistor 0 is forced to the hardware pin shutdown configuration

bit 2 R0A: Resistor 0 Terminal A (P0A pin) Connect Control bit

This bit connects/disconnects the Resistor 0 Terminal A to the Resistor 0 Network1= P0A pin is connected to the Resistor 0 Network0= P0A pin is disconnected from the Resistor 0 Network

Note 1: The hardware SHDN pin (when active) overrides the state of these bits. When the SHDN pin returns to theinactive state, the TCON register will control the state of the terminals. The SHDN pin does not modify thestate of the TCON bits.

2: These bits do not affect the wiper register values.

8/12/2019 MCP4261_2OPCION

34/84

MCP414X/416X/424X/426X


bit 1 R0W: Resistor 0 Wiper (P0W pin) Connect Control bit

This bit connects/disconnects the Resistor 0 Wiper to the Resistor 0 Network1= P0W pin is connected to the Resistor 0 Network0= P0W pin is disconnected from the Resistor 0 Network

bit 0 R0B: Resistor 0 Terminal B (P0B pin) Connect Control bit

This bit connects/disconnects the Resistor 0 Terminal B to the Resistor 0 Network1= P0B pin is connected to the Resistor 0 Network0= P0B pin is disconnected from the Resistor 0 Network

REGISTER 4-2: TCON BITS (1, 2)(CONTINUED)

Note 1: The hardware SHDN pin (when active) overrides the state of these bits. When the SHDN pin returns to theinactive state, the TCON register will control the state of the terminals. The SHDN pin does not modify thestate of the TCON bits.

2: These bits do not affect the wiper register values.

8/12/2019 MCP4261_2OPCION

35/84


MCP414X/416X/424X/426X

5.0 RESISTOR NETWORK

The Resistor Network has either 7-bit or 8-bit resolu-tion. Each Resistor Network allows zero scale to fullscale connections. Figure 5-1shows a block diagramfor the resistive network of a device.

The Resistor Network is made up of several parts.

These include:

Resistor Ladder Wiper Shutdown (Terminal Connections)

Devices have either one or two resistor networks,These are referred to as Pot 0 and Pot 1.

FIGURE 5-1: Resistor Block Diagram.

5.1 Res is tor Ladder Modu le

The resistor ladder is a series of equal value resistors(RS) with a connection point (tap) between the tworesistors. The total number of resistors in the series(ladder) determines the RAB resistance (seeFigure 5-1). The end points of the resistor ladder are

connected to analog switches which are connected tothe device Terminal A and Terminal B pins. The RAB(and RS) resistance has small variations over voltageand temperature.

For an 8-bit device, there are 256 resistors in a stringbetween terminal A and terminal B. The wiper can beset to tap onto any of these 256 resistors thus providing257 possible settings (including terminal A and terminalB).

For a 7-bit device, there are 128 resistors in a stringbetween terminal A and terminal B. The wiper can beset to tap onto any of these 128 resistors thus providing129 possible settings (including terminal A and terminalB).

Equation 5-1 shows the calculation for the stepresistance.

EQUATION 5-1: RSCALCULATION

RS

A

RS

RS

RS

B

257

256

255

1

0

RW(1)

W

(01h)

Analog Mux

RW(1)

(00h)

RW(1)

(FEh)

RW(1)

(FFh)

RW(1)

(100h)

Note 1: The wiper resistance is dependent onseveral factors including, wiper code,device VDD, Terminal voltages (on A, B,and W), and temperature.

Also for the same conditions, each tapselection resistance has a small variation.This RWvariation has greater effects on

some specifications (such as INL) for thesmaller resistance devices (5.0 k)compared to larger resistance devices(100.0 k).

RAB

8-BitN =

128

127

126

1

0

(01h)

(00h)

(7Eh)

(7Fh)

(80h)

7-BitN =

RS

RAB

256( )-------------=

RS

RAB

128( )--------------=

8-bit Device

7-bit Device

8/12/2019 MCP4261_2OPCION

36/84

MCP414X/416X/424X/426X


5.2 Wiper

Each tap point (between the RS resistors) is aconnection point for an analog switch. The oppositeside of the analog switch is connected to a commonsignal which is connected to the Terminal W (Wiper)pin.

A value in the volatile wiper register selects whichanalog switch to close, connecting the W terminal tothe selected node of the resistor ladder.

The wiper can connect directly to Terminal B or toTerminal A. A zero-scale connections, connects theTerminal W (wiper) to Terminal B (wiper setting of000h). A full-scale connections, connects the TerminalW (wiper) to Terminal A (wiper setting of 100h or 80h).In these configurations the only resistance between theTerminal W and the other Terminal (A or B) is that of theanalog switches.

A wiper setting value greater than full scale (wipersetting of 100h for 8-bit device or 80h for 7-bit devices)

will also be a Full Scale setting (Terminal W (wiper)connected to Terminal A). Table 5-1illustrates the fullwiper setting map.

Equation 5-2illustrates the calculation used to deter-mine the resistance between the wiper and terminal B.

EQUATION 5-2: RWBCALCULATION

TABLE 5-1: VOLATILE WIPER VALUE VS.

WIPER POSITION MAP

5.3 WiperLock Techno logy

The MCP4XXX devices WiperLock technology allowsapplication-specific calibration settings to be secured inthe EEPROM without requiring the use of an additionalwrite-protect pin. There are two WiperLock Technologyconfiguration bits (WL0 and WL1). These bits prevent

the Non-Volatile and Volatile addresses and bits for thespecified resistor network from being written.

The WiperLock technology prevents the serialcommands from doing the following:

Changing a volatile wiper value Writing to a non-volatile wiper memory location Changing the volatile TCON register value

For either Resistor Network 0 or Resistor Network 1(Potx), the WLx bit controls the following:

Non-Volatile Wiper Register Volatile Wiper Register Volatile TCON register bits RxHW, RxA, RxW, and

RxB

High Voltage commands are required to enable anddisable WiperLock. Please refer to the Modify WriteProtect or WiperLock Technology (High Voltage)

command for operation.

5.3.1 POR/BOR OPERATION WHENWIPERLOCK TECHNOLOGYENABLED

The WiperLock Technology state is not affected by aPOR/BOR event. A POR/BOR event will load theVolatile Wiper register value with the Non-VolatileWiper register value, refer to Section 4.1.

Wiper SettingProperties

7-bit Pot 8-bit Pot

3FFh081h

3FFh101h

Reserved (Full Scale (W = A)),Increment and Decrementcommands ignored

080h 100h Full Scale (W = A),Increment commands ignored

07Fh041h

0FFh081

W = N

040h 080h W = N (Mid-Scale)

03Fh001h

07Fh001

W = N

000h 000h Zero Scale (W = B)Decrement command ignored

RWB

RAB

N

256( )-------------- R

W+=

N = 0 to 256 (decimal)

RWB

RAB

N

128( )-------------- R

W+=

N = 0 to 128 (decimal)

8-bit Device

7-bit Device

8/12/2019 MCP4261_2OPCION

37/84


MCP414X/416X/424X/426X

5.4 Shutdown

Shutdown is used to minimize the devices currentconsumption. The MCP4XXX has two methods toachieve this. These are:

Hardware Shutdown Pin (SHDN)

Terminal Control Register (TCON)

The Hardware Shutdown pin is backwards compatiblewith the MCP42XXX devices.

5.4.1 HARDWARE SHUTDOWN PIN(SHDN)

The SHDN pin is available on the dual potentiometerdevices. When the SHDN pin is forced active (VIL):

The P0A and P1A terminals are disconnected The P0W and P1W terminals are simultaneously

connect to the P0B and P1B terminals, respec-tively (see Figure 5-2)

The Serial Interface is NOT disabled, and allSerial Interface activity is executed

Any EEPROM write cycles are completed

The Hardware Shutdown pin mode does NOT corruptthe values in the Volatile Wiper Registers nor theTCON register. When the Shutdown mode is exited(SHDN pin is inactive (VIH)):

The device returns to the Wiper setting specifiedby the Volatile Wiper value

The TCON register bits return to controlling theterminal connection state

FIGURE 5-2: Hardware Shutdown

Resistor Network Configuration.

5.4.2 TERMINAL CONTROL REGISTER(TCON)

The Terminal Control (TCON) register is a volatileregister used to configure the connection of eachresistor network terminal pin (A, B, and W) to theResistor Network. This register is shown inRegister 4-2.

The RxHW bits forces the selected resistor networkinto the same state as the SHDN pin. Alternate lowpower configurations may be achieved with the RxA,RxW, and RxB bits.

5.4.3 INTERACTION OF SHDN PIN ANDTCON REGISTER

Figure 5-3 shows how the SHDN pin signal and theRxHW bit signal interact to control the hardwareshutdown of each resistor network (independently).Using the TCON bits allows each resistor network (Pot0 and Pot 1) to be individually shutdown while thehardware pin forces both resistor networks to be shut-down at the same time.

FIGURE 5-3: RxHW bit and SHDN pin

Interaction.

A

B

W

ResistorNetwork

Note: When the RxHW bit forces the resistornetwork into the hardware SHDN state,the state of the TCON register RxA, RxW,and RxB bits is overridden (ignored).When the state of the RxHW bit no longerforces the resistor network into the hard-ware SHDN state, the TCON register RxA,RxW, and RxB bits return to controlling theterminal connection state. In other words,the RxHW bit does not corrupt the state ofthe RxA, RxW, and RxB bits.

SHDN (from pin)

RxHW(from TCON register)

To Pot x HardwareShutdown Control

8/12/2019 MCP4261_2OPCION

38/84

MCP414X/416X/424X/426X


NOTES:

8/12/2019 MCP4261_2OPCION

39/84


MCP414X/416X/424X/426X

6.0 SERIAL INTERFACE (SPI)

The MCP4XXX devices support the SPI serial protocol.This SPI operates in the slave mode (does notgenerate the serial clock).

The SPI interface uses up to four pins. These are:

CS - Chip Select SCK - Serial Clock SDI - Serial Data In SDO - Serial Data Out

Typical SPI Interfaces are shown in Figure 6-1. In theSPI interface, The Masters Output pin is connected tothe Slaves Input pin and the Masters Input pin isconnected to the Slaves Output pin.

The MCP4XXX SPIs module supports two (of the four)standard SPI modes. These are Mode 0, 0and 1, 1.The SPI mode is determined by the state of the SCK

pin (VIHor VIL) on the when the CS pin transitions frominactive (VIH) to active (VILor VIHH).

All SPI interface signals are high-voltage tolerant.

FIGURE 6-1: Typical SPI Interface Block Diagram.

SDI/SDOSDI

SDO

SDO

SDI 200 k

MCP41X1

SCK SCK

SDISDO

MCP4XXX

SDOSDI

SCKSCK

( Master Out - Slave In (MOSI) )

( Master In - Slave Out (MISO) )

Host

Controller

Host

Controller

Typical SPI Interface Connections

Typical MCP41X1 SPI Interface Connections (Host Controller Hardware SPI)

SDI/SDOSDI

SDO

I/O

MCP41X1

I/O SCK

Host

Controller

Al ternate MCP41X1 SPI Inter face Connections (Host Controller Firmware SPI)

(SDO/SDI)

(SCK)

CSI/O (1)

CSI/O (1)

CSI/O (1)

Note 1: If High voltage commands are desired, some type of external circuitry needs to beimplemented.

8/12/2019 MCP4261_2OPCION

40/84

MCP414X/416X/424X/426X


6.1 SDI, SDO, SCK, and CS Operation

The operation of the four SPI interface pins arediscussed in this section. These pins are:

SDI (Serial Data In) SDO (Serial Data Out) SCK (Serial Clock)

CS (Chip Select)

The serial interface works on either 8-bit or 16-bitboundaries depending on the selected command. TheChip Select (CS) pin frames the SPI commands.

6.1.1 SERIAL DATA IN (SDI)

The Serial Data In (SDI) signal is the data signal intothe device. The value on this pin is latched on the risingedge of the SCK signal.

6.1.2 SERIAL DATA OUT (SDO)

The Serial Data Out (SDO) signal is the data signal outof the device. The value on this pin is driven on the

falling edge of the SCK signal.

Once the CS pin is forced to the active level (VIL orVIHH), the SDO pin will be driven. The state of the SDOpin is determined by the serial bits position in thecommand, the command selected, and if there is acommand error state (CMDERR).

6.1.3 SDI/SDO

For device packages that do not have enough pins forboth an SDI and SDO pin, the SDI and SDO function-ality is multiplexed onto a single I/O pin called SDI/SDO.

The SDO will only be driven for the command error bit(CMDERR) and during the data bits of a read command(after the memory address and command has beenreceived).

6.1.3.1 SDI/SDO Operation

Figure 6-2shows a block diagram of the SDI/SDO pin.The SDI signal has an internal smart pull-up. Thevalue of this pull-up determines the frequency that datacan be read from the device. An external pull-up can beadded to the SDI/SDO pin to improve the rise time andtherefore improve the frequency that data can be read.

Data written on the SDI/SDO pin can be at themaximum SPI frequency.

On the falling edge of the SCK pin during the C0 bit(see Figure 7-1), the SDI/SDO pin will start outputtingthe SDO value. The SDO signal overrides the control of

the smart pull-up, such that whenever the SDI/SDO pinis outputting data, the smart pull-up is enabled.

The SDI/SDO pin will change from an input (SDI) to anoutput (SDO) after the state machine has received the

Address and Command bits of the Command Byte. Ifthe command is a Read command, then the SDI/SDOpin will remain an output for the remainder of thecommand. For any other command, the SDI/SDO pinreturns to an input.

FIGURE 6-2: Serial I/O Mux Block

Diagram.

Note: MCP41X1 Devices Only .

Note: To support the High voltage requirement of

the SDI function, the SDO function is anopen drain output.

Note: Care must be take to ensure that a Driveconflict does not exist between the HostControllers SDO pin (or software SDI/SDOpin) and the MCP41x1 SDI/SDO pin (seeFigure 6-1).

SDI/SDOSDI

SDOControl

smart pull-up

Opendrain

Logic

8/12/2019 MCP4261_2OPCION

41/84


MCP414X/416X/424X/426X

6.1.4 SERIAL CLOCK (SCK)(SPI FREQUENCY OF OPERATION)

The SPI interface is specified to operate up to 10 MHz.The actual clock rate depends on the configuration ofthe system and the serial command used. Table 6-1shows the SCK frequency for different configurations.

TABLE 6-1: SCK FREQUENCY

6.1.5 THE CS SIGNAL

The Chip Select (CS) signal is used to select the deviceand frame a command sequence. To start a command,or sequence of commands, the CS signal musttransition from the inactive state (VIH) to an active state(VILor VIHH).

After the CS signal has gone active, the SDO pin isdriven and the clock bit counter is reset.

If an error condition occurs for an SPI command, thenthe Command bytes Command Error (CMDERR) bit(on the SDO pin) will be driven low (VIL). To exit theerror condition, the user must take the CS pin to the VIHlevel.

When the CS pin returns to the inactive state (VIH) theSPI module resets (including the address pointer).While the CS pin is in the inactive state (VIH), the serialinterface is ignored. This allows the Host Controller to

interface to other SPI devices using the same SDI,SDO, and SCK signals.

The CS pin has an internal pull-up resistor. The resistoris disabled when the voltage on the CS pin is at the VILlevel. This means that when the CS pin is not driven,the internal pull-up resistor will pull this signal to the VIHlevel. When the CS pin is driven low (VIL), the resis-tance becomes very large to reduce the device currentconsumption.

The high voltage capability of the CS pin allows HighVoltage commands. High Voltage commands allow thedevices WiperLock Technology and write protectfeatures to be enabled and disabled.

Memory Type Access

Command

Read

Write,

Increment,

Decrement

Non-VolatileMemory

SDI, SDO 10 MHz 10 MHz (2, 3)

SDI/SDO(1)

250 kHz (4) 10 MHz (2, 3)

VolatileMemory

SDI, SDO 10 MHz 10 MHz

SDI/SDO(1)

250 kHz (4) 10 MHz

Note 1: MCP41X1 devices only2: Non-Volatile memory does not support

the Increment or Decrement command.

3: After a Write command, the internal writecycle must complete before the next SPIcommand is received.

4: This is the maximum clock frequencywithout an external pull-up resistor.

Note: There is a required delay after the CS pingoes active to the 1st edge of the SCK pin.

8/12/2019 MCP4261_2OPCION

42/84

MCP414X/416X/424X/426X


6.2 The SPI Modes

The SPI module supports two (of the four) standard SPImodes. These are Mode 0,0 and 1,1. The mode isdetermined by the state of the SDI pin on the risingedge of the 1st clock bit (of the 8-bit byte).

6.2.1 MODE 0,0In Mode 0,0: SCK idle state = low (VIL), data is clockedin on the SDI pin on the rising edge of SCK and clockedout on the SDO pin on the falling edge of SCK.

6.2.2 MODE 1,1

In Mode 1,1: SCK idle state = high (VIH), data isclocked in on the SDI pin on the rising edge of SCK andclocked out on the SDO pin on the falling edge of SCK.

6.3 SPI Waveforms

Figure 6-3 through Figure 6-8show the different SPIcommand waveforms. Figure 6-3 and Figure 6-4 areread and write commands. Figure 6-5and Figure 6-6are read commands when the SDI and SDO pins aremultiplexed on the same pin (SDI/SDO). Figure 6-7

and Figure 6-8 are increment and decrementcommands. The high voltage increment and decrementcommands are used to enable and disable WiperLockTechnology and Write Protect.

FIGURE 6-3: 16-Bit Commands (Write, Read) - SPI Waveform (Mode 1,1).

FIGURE 6-4: 16-Bit Commands (Write, Read) - SPI Waveform (Mode 0,0).

CS

SCK

Write toSSPBUF

SDI

InputSample

SDO bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

bit15 bit14 bit13 bit12 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

AD3 AD2 AD1 AD0

C1 C0

X D8 D7 D6 D5 D4 D3 D2 D1 D0

VIH

VIL

CMDERR bit

VIHH

CS

SCK

Write toSSPBUF

SDI

InputSample

SDO bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

bit15 bit14 bit13 bit12 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

AD3 AD2 AD1 AD0

C1 C0

X D8 D7 D6 D5 D4 D3 D2 D1 D0

VIH

VIL

CMDERR bit

VIHH

8/12/2019 MCP4261_2OPCION

43/84


MCP414X/416X/424X/426X

FIGURE 6-5: 16-Bit Read Command for Devices with SDI/SDO multiplexed -

SPI Waveform (Mode 1,1).

FIGURE 6-6: 16-Bit Read Command for Devices with SDI/SDO multiplexed -

SPI Waveform (Mode 0,0).

CS

SCK

Write toSSPBUF

SDI

InputSample

SDO bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

bit15 bit14 bit13 bit12

AD3 AD2 AD1 AD0 C1 C0

D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

VIH

VIL

CMDERR bit

Note 1:The SDI pin will read the state of the SDI pin which will be the SDO signal, unless overdriven

(1) (1) (1) (1) (1) (1) (1) (1) (1) (1)1 1

VIHH

CS

SCK

Write toSSPBUF

SDI

InputSample

SDO bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

bit15 bit14 bit13 bit12

AD3 AD2 AD1 AD0 C1 C0

D8 D7 D6 D5 D4 D3 D2 D1 D0X

VIH

VIL

CMDERR bit

Note 1:The SDI pin will read the state of the SDI pin which will be the SDO signal, unless overdriven

(1) (1) (1) (1) (1) (1) (1) (1) (1) (1)1 1

VIHH

8/12/2019 MCP4261_2OPCION

44/84

MCP414X/416X/424X/426X


FIGURE 6-7: 8-Bit Commands (Increment, Decrement, Modify Write Protect or WiperLock

Technology) - SPI Waveform with PIC MCU (Mode 1,1).

FIGURE 6-8: 8-Bit Commands (Increment, Decrement, Modify Write Protect or WiperLock

Technology) - SPI Waveform with PIC MCU (Mode 0,0).

bit7 bit0

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

CS

SCK

Write toSSPBUF

SDI

InputSample

SDO

VIH

VIL

AD3 AD2 AD1 AD0 C0C1 X X

1 = Valid Command/Address0 = Invalid Command/Address

CMDERR bit

VIHH

SCK

InputSample

SDI

bit7 bit0

SDO bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

Write toSSPBUF

CS

VIH

VIL

AD3 AD2 AD1 AD0 C0C1 X X

1 = Valid Command/Address0 = Invalid Command/Address

CMDERR bit

VIHH

8/12/2019 MCP4261_2OPCION

45/84


MCP414X/416X/424X/426X

7.0 DEVICE COMMANDS

The MCP4XXXs SPI command format supports 16memory address locations and four commands. Eachcommand has two modes. These are:

Normal Serial Commands High-Voltage Serial Commands

Normal serial commands are those where the CS pin isdriven to VIL. With High-Voltage Serial Commands, theCS pin is driven to VIHH. In each mode, there are fourpossible commands. These commands are shown inTable 7-1.

The 8-bit commands (Increment Wiper and Decre-ment Wiper commands) contain a Command Byte,see Figure 7-1, while 16-bit commands (Read Dataand Write Datacommands) contain a Command Byteand a Data Byte. The Command Byte contains two databits, see Figure 7-1.

Table 7-2 shows the supported commands for eachmemory location and the corresponding values on the

SDI and SDO pins.

Table 7-3shows an overview of all the SPI commandsand their interaction with other device features.

7.1 Command Byte

The Command Byte has three fields, the Address, theCommand, and 2 Data bits, see Figure 7-1. Currentlyonly one of the data bits is defined (D8). This is for theWrite command.

The device memory is accessed when the master

sends a proper Command Byte to select the desiredoperation. The memory location getting accessed iscontained in the Command Bytes AD3:AD0 bits. Theaction desired is contained in the Command BytesC1:C0 bits, see Table 7-1. C1:C0 determines if thedesired memory location will be read, written,Incremented (wiper setting +1) or Decremented (wipersetting -1). The Increment and Decrement commandsare only valid on the volatile wiper registers, and inHigh Voltage commands to enable/disable WiperLockTechnology and Software Write Protect.

As the Command Byte is being loaded into the device(on the SDI pin), the devices SDO pin is driving. TheSDO pin will output high bits for the first six bits of thatcommand. On the 7th bit, the SDO pin will output theCMDERR bit state (see Section 7.3 Error Condi-tion ). The 8th bit state depends on the the commandselected.

TABLE 7-1: COMMAND BIT OVERVIEW

FIGURE 7-1: General SPI Command Formats.

C1:C0

Bit

States

Command# of

Bits

Operates on

Volatile/

Non-Volatile

memory

11 Read Data 16-Bits Both

00 Write Data 16-Bits Both

01 Increment (1) 8-Bits Volatile Only

10 Decrement(1) 8-Bits Volatile Only

Note 1: High Voltage Increment and Decrementcommands on select non-volatile memorylocations enable/disable WiperLockTechnology and the software WriteProtect feature.

AD3

AD2

AD1

AD0

C1

C0

D9

D8

Memory

Command Byte

DataAddress Bits

CommandBits

AD3

AD2

AD1

AD0

C1

C0

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Memory

16-bit Command

DataAddress Bits

CommandBits

0 0 = Write Data0 1 = INCR1 0 = DECR1 1 = Read Data

C C1 0

CommandBits

8-bit Command

Command Byte Data Byte

8/12/2019 MCP4261_2OPCION

46/84

8/12/2019 MCP4261_2OPCION

47/84


MCP414X/416X/424X/426X

7.2 Data Byte

Only the Read Command and the Write Command usethe Data Byte, see Figure 7-1. These commandsconcatenate the 8-bits of the Data Byte with the onedata bit (D8) contained in the Command Byte to form9-bits of data (D8:D0). The Command Byte format

supports up to 9-bits of data so that the 8-bit resistornetwork can be set to Full Scale (100h or greater). Thisallows wiper connections to Terminal A and toTerminal B.

The D9 bit is currently unused, and corresponds to theposition on the SDO data of the CMDERR bit.

7.3 Error Condition

The CMDERR bit indicates if the four address bitsreceived (AD3:AD0) and the two command bitsreceived (C1:C0) are a valid combination (seeTable 4-1). The CMDERR bit is high if the combinationis valid and low if the combination is invalid.

The command error bit will also be low if a write to aNon-Volatile Address has been specified and anotherSPI command occurs before the CS pin is driveninactive (VIH).

SPI commands that do not have a multiple of 8 clocksare ignored.

Once an error condition has occurred, any followingcommands are ignored. All following SDO bits will below until the CMDERR condition is cleared by forcingthe CS pin to the inactive state (VIH).

7.3.1 ABORTING A TRANSMISSION

All SPI transmissions must have the correct number ofSCK pulses to be executed. The command is notexecuted until the complete number of clocks havebeen received. Some commands also require the CSpin to be forced inactive (VIH). If the CS pin is forced tothe inactive state (V

IH

) the serial interface is reset.Partial commands are not executed.

SPI is more susceptible to noise than other busprotocols. The most likely case is that this noisecorrupts the value of the data being clocked into theMCP4XXX or the SCK pin is injected with extra clockpulses. This may cause data to be corrupted in thedevice, or a command error to occur, since the addressand command bits were not a valid combination. Theextra SCK pulse will also cause the SPI data (SDI) andclock (SCK) to be out of sync. Forcing the CS pin to theinactive state (VIH) resets the serial interface. The SPIinterface will ignore activity on the SDI and SCK pinsuntil the CS pin transition to the active state is detected

(VIHto VILor VIHto VIHH).

Note 1: When data is not being received by theMCP4XXX, It is recommended that theCS pin be forced to the inactive level (VIL)

2: It is also recommended that long continu-ous command strings should be brokendown into single commands or shortercontinuous command strings. Thisreduces the probability of noise on theSCK pin corrupting the desired SPIcommands.

8/12/2019 MCP4261_2OPCION

48/84

MCP414X/416X/424X/426X


7.4 Continuous Commands

The device supports the ability to execute commandscontinuously. While the CS pin is in the active state (V ILor VIHH). Any sequence of valid commands may bereceived.

The following example is a valid sequence of events:

1. CS pin driven active (VILor VIHH).

2. Read Command.

3. Increment Command (Wiper 0).

4. Increment Command (Wiper 0).

5. Decrement Command (Wiper 1).

6. Write Command (Volatile memory).

7. Write Command (Non-Volatile memory).

8. CS pin driven inactive (VIH).

TABLE 7-3: COMMANDS

Note 1: It is recommended that while the CS pin isactive, only one type of command shouldbe issued. When changing commands, itis recommended to take the CS pininactive then force it back to the activestate.

2: It is also recommended that longcommand strings should be broken downinto shorter command strings. Thisreduces the probability of noise on theSCK pin corrupting the desired SPIcommand string.

Command Name# of

Bits

Writes

Value in

EEPROM

Operates onVolatile/

Non-Volatile

memory

HighVoltage

(VIHH) on

CS pin?

Impact on

WiperLock or

Write Protect

Workswhen

Wiper is

locked?

Write Data 16-Bits Yes (1) Both unlocked (1) No

Read Data 16-Bits Both unlocked (1) No

Increment Wiper 8-Bits Volatile Only unlocked (1) No

Decrement Wiper 8-Bits Volatile Only unlocked (1) No

High Voltage Write Data 16-Bits Yes Both Yes unchanged No

High Voltage Read Data 16-Bits Both Yes unchanged Yes

High Voltage Increment Wiper 8-Bits Volatile Only Yes unchanged No

High Voltage Decrement Wiper 8-Bits Volatile Only Yes unchanged No

Modify Write Protect or Wiper-

Lock Technology (High Voltage)-Enable

8-Bits (2) Non-VolatileOnly (2)

Yes locked/protected (2)

Yes

Modify Write Protect or Wiper-

Lock Technology (High Voltage)-Disable

8-Bits (3) Non-VolatileOnly (3)

Yes unlocked/unprotected (3)

Yes

Note 1: This command will only complete if wiper is unlocked (WiperLock Technology is Disabled).

2: If the command is executed using address 02h or 03h, then that corresponding wiper is locked orif with address 0Fh, then Write Protect is enabled.

3: If the command is executed using with address 02h or 03h, then that corresponding wiper is unlocked orif with address 0Fh, then Write Protect is disabled.

8/12/2019 MCP4261_2OPCION

49/84


MCP414X/416X/424X/426X

7.5 Write Data

Normal and High Voltage

The Write command is a 16-bit command. The WriteCommand can be issued to both the Volatile andNon-Volatile memory locations. The format of thecommand is shown in Figure 7-2.

A Write command to a Volatile memory locationchanges that location after a properly formatted WriteCommand (16-clock) have been received.

A Write command to a Non-Volatile memory locationwill only start a write cycle after a properly formattedWrite Command (16-clock) have been received and theCS pin transitions to the inactive state (VIH).

7.5.1 SINGLE WRITE TO VOLATILEMEMORY

The write operation requires that the CS pin be in theactive state (VILor VIHH). Typically, the CS pin will be inthe inactive state (VIH) and is driven to the active state(VIL). The 16-bit Write Command (Command Byte andData Byte) is then clocked in on the SCK and SDI pins.Once all 16 bits have been received, the specifiedvolatile address is updated. A write will not occur if thewrite command isnt exactly 16 clocks pulses. Thisprotects against system issues from corrupting theNon-Volatile memory locations.

Figure 6-3 and Figure 6-4 show possible waveformsfor a single write.

7.5.2 SINGLE WRITE TO NON-VOLATILEMEMORY

The sequence to write to to a single non-volatilememory location is the same as a single write to volatilememory with the exception that after the CS pin isdriven inactive (VIH), the EEPROM write cycle (twc) isstarted. A write cycle will not start if the write commandisnt exactly 16 clocks pulses. This protects againstsystem issues from corrupting the Non-Volatilememory locations.

After the CS pin is driven inactive (VIH), the serialinterface may immediately be re-enabled by driving theCS pin to the active state (VILor VIHH).

During an EEPROM write cycle, only serial commandsto Volatile memory (addresses 00h, 01h, 04h, and 05h)are accepted. All other serial commands are ignoreduntil the EEPROM write cycle (twc) completes. Thisallows the Host Controller to operate on the VolatileWiper reg

Documents

MCP4261_2OPCION