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Measures of Successfor NanoManufacturing of Future ICs

Measures of Successfor NanoManufacturing of Future ICs

1st International Symposium on NanoManufacturing

Cambridge, Massachusetts

April 25, 2003

Robert Doering

Texas Instruments, Inc.

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IC Metrics that Should Guide Researchon NanoManufacturing of Electronics

IC Metrics that Should Guide Researchon NanoManufacturing of Electronics• Cost/Integ.-Function (e.g., $/gate or $/bit integrated into system)

• Operations/Second (computation speed, e.g. MIPS)

• Power Dissipation (both operating and standby power)

• Integration Density (e.g., integrated functions/cm2 or /cm3)

• Integration Diversity (SOC functions - e.g., analog, RF, e-RAM)

• Capital Cost/Capacity (e.g., capital investment $/chips/month)

• Mfg. Cycle Time (impacts time-to-market and ASIC delivery)

• R&D Cost (e.g., cost per new product or tech node)

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First-Order IC Figures-of-MeritFirst-Order IC Figures-of-MeritP = Performance) = Operations/Second (e.g., gate switches/s)

$ = Cost (to mfg. the IC)

D = Dissipation/Power Consumption

• FOM1 = P/$ = “Bang per Buck” (performance/cost)

• FOM2 = P/D = Efficiency (operations/energy) {“P -> 0 limit” is also important!}

• Sufficiently large improvements in FOM1 and/or FOM2 result in revolutionary new end equipment markets for ICs (PCs, Cell Phones, etc.).

“eqi-FOM cone” (approximate)CPU

Digital-Baseband Chip

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DAB Digital Radio

Digital Still Camera

IP Phone

Pro-Audio

Digital MotorControl

Digital Hearing

Video Server

Internet Audio

Digital SpeakersVOPGateway

2G Cellular Phones 3G Cellular

Phones

Bluetooth-Enabled

Products

3G Base-Stations

Cable Modem

PDAs

DSLModem

HomeNetworking

CentralOffice

NanoMfg. Must Enable Many More !NanoMfg. Must Enable Many More !

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A Historical View of theIC Mfg. Cost/Function Challenge

A Historical View of theIC Mfg. Cost/Function Challenge

Feature Size

~12-14%

~12-14%~4%

Wafer Size ~2%< 2%

Yield Improvement ~7-10% < 1%

Other Productivity -- Equipment, etc.

> 9-15%

Log

($/F

unct

ion)

Time 1995

25-30%/YrImprovement

Historical Trend Equipment Productivity

Source: SEMATECH, circa 1995

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500

350

250

180

130100

70

50

35

25

95 97 99 01 04 07 10 13 16500

350

250

180

130

90

65

45

32

22

95 97 99 01 04 07 10 13 16

Feature-Scaling: the Traditional Enabler*Feature-Scaling: the Traditional Enabler*Fe

atur

e Si

ze [n

m]

Year of Production

Lithography Half-Pitch(ITRS 2002)

Gate Length(ITRS 2002)

9

15

return to0.7x/3-yr

13

Source: 2000-2002 ITRS

* Of Speed, Low-Cost,Low-Power, etc.

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Approximate Dependence of Mfg. Coston Chip Size and Functional ComplexityApproximate Dependence of Mfg. Cost

on Chip Size and Functional Complexity

0

10

20

30

40

50

60

70

Rela

tive

Mfg

. Cos

t

0 5 10 15 20 25 30 35 40 45 500.0

0.51.0

1.52.0

Masks

Area [cm2]

60-7050-6040-5030-4020-3010-200-10

0.5

1.0

1.5

2.0

Can NanoMfg. reduce the “yield non-linearities” ?

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Historically, IC Mfg. Cost-Effectivenessat Low-Volume Has Been Poor

Historically, IC Mfg. Cost-Effectivenessat Low-Volume Has Been Poor

4

5

6

7

8

2 4 6 8 10 12 14 16 18 20

K-Wafers / Month

Cos

t / c

m2

2 4 6M-cm2 / Month

Can NanoMfg. “Flatten” the Economy-of-Scale Curve ?

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0

1

10

100

1,000

10,000

100,000

1960

1965

1970

1975

1980

1985

1990

1995

2000

2005

2010

2015

2020

2025

Area

Dem

and

per Y

ear (

Mill

ions

in2 )

100%

33%

10%

Pilot

75 mm+

100 mm

125 mm+

150 mm

200 mm

300 mm450 mm

Total Wafer Area Trend1976-2025: 10% CAGR

Of Course, High-Volume ProductionWill Be a Requirement for NanoMfg. !Of Course, High-Volume ProductionWill Be a Requirement for NanoMfg. !

Source: VLSI Research and International SEMATECH

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0.01

0.1

1

10

100

1970 1980 1990 2000 2010 2020

Waf

er-F

ab C

apita

l Cos

t [$B

]

What Cost for “Mass-NanoMfg.” Fabs?What Cost for “Mass-NanoMfg.” Fabs?

Risk Limited ?

Extrapolationof Prior History

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Capital Productivity [wafers/month/$B]

0

2

4

6

8

10

0 2 4 6 8

Equipment Capital [$B/25K waf/mo]

Unit

Cost

kilodollars/waferdollars/chip (@1-cm2)microcents/transistor

12.5 6.25 3.134.17

What Capital Productivity for NanoMfg. ?What Capital Productivity for NanoMfg. ?

“Best Case”10-Year

ProjectionsBased on ITRS

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0

5

10

15

20

25

0 6 12 18 24

Hot-Lot Size [wafers]

Cycl

e-Ti

me

[day

s]

Can NanoManufacturing Provide Breakthroughs in Cycle-Time ?

Can NanoManufacturing Provide Breakthroughs in Cycle-Time ?

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Analysis of a 1993 Demoof 71.4-Hour Single-Wafer Cycle-Time

Analysis of a 1993 Demoof 71.4-Hour Single-Wafer Cycle-Time

OVERHEAD12.6 hr

TRANSFER10.5 hr

QUEUE30.8 hr

THEORETICAL17.5 hr

Can NanoMfg. be more efficient ?

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17.5-Hour Theoretical Cycle-Time Components

17.5-Hour Theoretical Cycle-Time Components

0

2

4

6

8

10

Pump/Vent WaferMove

Metrology Auxiliary Process

Hour

s

Can NanoMfg. approach pure “process time” ?

At even better than “thin-film process” rates ?

(Load Lock)

Can NanoMfg. Enhance the Affordability of IC Technology R&D ?

Can NanoMfg. Enhance the Affordability of IC Technology R&D ?

0100200300400500600700800900

1000

-3 -2 -1 0 1 2

Technology Lead (Years)

Tech

nolo

gy In

vest

men

t (M

$)

19931995199719992001

Source: Yoshio Nishi and Bob HelmsRRD

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Suggested Targets to Guide Research on: NanoManufacturing of ICs in 10-20 Years

Suggested Targets to Guide Research on: NanoManufacturing of ICs in 10-20 Years

• < 0.5 µ¢/gate for high-performance logic• > 4x108 gates/cm2 for the above logic (or “equivalent 3D”)• > 5 THz of intrinsic switching speed for the above logic• < 6 µW/MOP/sec• > 1010 “minimum-size” switches/cm2 (e.g., SRAM transistors)• < 50 n¢/bit of memory (of at least “DRAM performance”) • > 30 Gbits/cm2 of the above memory• > 105 hours (~ 10 years) of operating lifetime• < 103 FITs/Mbit of SER in a terrestrial environment• > 2x1014 logic gates/day of “mass production” capacity (in ~106-107 ICs)• < $1B of capital cost for the above capacity• < 1.5 days of theoretical cycle time for a “pure logic process”• Ability to integrate logic, analog, RF, multiple memory types

(e.g., high-speed, nonvolatile), optics, sensors, “bio stuff,”...

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NanoMfg. Should Initially Support Integration of New IC Technologies with CMOS

NanoMfg. Should Initially Support Integration of New IC Technologies with CMOS

Source: 2001 ITRS

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“Quantum-Barrier Tunneling Analogy”“Quantum-Barrier Tunneling Analogy”

Chip Performance (for fixed A)

ChipCost

(for fixed A)

AUPProfit

Historical Trend Cost-Performance Envelope

“Fine-Structure” “NanoManufacturing”in Typical Breakthrough ?

Breakthroughs

e.g., DUV Litho