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Ultra-Deep submicron technologyEtienne SicardInsa
[email protected]://intrage.insa-tlse.fr/~etienne
E. Sicard - ultra deep submicron
Ultra-deep submicron technology Specific features Embedded Memory Magnetic RAM SOI conclusion Summary
E. Sicard - ultra deep submicron
83868992959801040.18028680386486pentiumpentium II1.00.20.32.00.05YearPentium IV0.031. Ultra-deep submicron technologyItanium07MicronSub-micronDeep-submicronUltraDeep-submicronNano
E. Sicard - ultra deep submicron
1. Ultra-deep submicron technologyMultiple technological options to optimize performanceFaster & bigger chipsAgreements to handle tremendous costs (ST,Philips,Motorola,TSMC)
E. Sicard - ultra deep submicron
2. Specific featuresImproved tretch isolationMultiple MOS optionsMultiple metal layersStacked viasLow K dielectric to reduce couplingsCopper to speed up signal transport High K dielectric to reduce leakage
E. Sicard - ultra deep submicron
2. Specific features3-6 MOS optionsHigh Speed: normal MOSVery high speed: critical pathLow leakage: for low powerHigh voltage: for I/OsDouble-gate: for embedded EEPROMRF : optimized for GHz amplifiers
E. Sicard - ultra deep submicron
High VoltageLow LeakageHigh SpeedUltra High SpeedEEPromApplication-oriented MOS deviceSame basic mechanism
New physical properties in EEPROM and MRam2. Specific features
E. Sicard - ultra deep submicron
2.5V1.2VHigh SpeedHigh Voltage1.2VLow leakage1.2V1.2V2.5V1.2V2. Specific features1.8V2.5VExample in 0.12m technology
E. Sicard - ultra deep submicron
2. Specific featuresOption layerOption layer propertiesSimple access to low leakage, high voltage and isolated Pwell
E. Sicard - ultra deep submicron
2. Specific features
Low leakage High speed High voltage Simulation of the 3 MOS options
E. Sicard - ultra deep submicron
2. Specific featuresHigh speedLow leakageSmall Ion reductionLow leakage MOS has higher Vt, slight Ion reductionLow leakage MOS has 1/100 Ioff of high speed MOSIoff ~10nAIoff ~100pA
E. Sicard - ultra deep submicron
2. Specific features0.1m process (TSMC+ST+IBM+)Each MOS is optimized for a target customer applicationTowards a world-wide standard process which will ease design
E. Sicard - ultra deep submicron
Type of MOS
Effective channel length (m)
Oxide thickness
Ioff
Ion
Ultra-high speed
0.07
16
Very high
Very high
High speed
0.09
16
High
High
Low leakage
0.09
24
Low
Medium
High voltage
0.2
50
Low
Low
Cmos Embedded memories80% of a system-on-chipBottleneck for bandwidth3. Embedded Memory
E. Sicard - ultra deep submicron
Parasitic capacitance: 2fFSpecific capacitance: 3-30fF3. Embedded Memory
E. Sicard - ultra deep submicron
3. Embedded Memory2nd PolyFloating PolyUsed in EPROM, EEPROM and Flash memoriesDouble-Gate MOS
E. Sicard - ultra deep submicron
3. Embedded MemoryDouble-Gate MOS
E. Sicard - ultra deep submicron
12V3. Embedded MemoryDouble-Gate MOS: write/erase by tunneling0V
0VddAccelerateHot electron Tunneling12VColdelectron TunnelingwriteeraseDense but slow
E. Sicard - ultra deep submicron
4. Magnetic RAMDense, fast, non-volatile: universal memory2 stage magnetic statesSilicium, Cobalt et NikelA high magnetic field changes the state of the material equal toI=5mA
E. Sicard - ultra deep submicron
Principles: Write: i/2 on the line, i/2 on the column gives a current high enough to change the stateRead: i/4 on the line, i/4 on the column and monitor the attenuation of current due to magnetic stateLineColumni/2i/2i/4WriteReadi/2i/2Erasei/44. Magnetic RAM
E. Sicard - ultra deep submicron
The next major evolution?Less capacitanceLess distance between nMOS and pMOSLess leakageCMOS compatible>50% faster circuits5. Silicon-On-insulator
E. Sicard - ultra deep submicron
6. ConclusionThe ultra-deep submicron technologies introduce new featuresLow leakage MOS targeted for low powerHigh voltage MOS introduced for I/O interfacingDouble-poly MOS for EPROM/Flash memoriesEmbedded memory are key components for System-on-chipMagnetic RAM to become the universal memorySOI has many promising features, some design issues pending
E. Sicard - ultra deep submicron