Microsoft Word - Overview of VLSI

DEPARTMENT OF E & C - 1 - DK

OVERVIEW OF VLSI DESIGN

� The monolithic integration of a large number of functions on a single chip usually

provides:

� Less area/volume and therefore, compactness

� Less power consumption

� Less testing requirements at system level

� Higher reliability, mainly due to improved on-chip interconnects

� Higher speed, due to significantly reduced interconnection length

� Significant cost savings

• Incredible growth in the field of ICs has come from steady miniaturization of

transistors and improvements in manufacturing processes.

• As transistor become smaller, they also become faster, dissipate less power, and

are cheaper to manufacture.

• Vacuum tubes (first half of 20th century), transistors (1948), ICs (1958 by Jack

Kilby)

• BJTs are more reliable, less noisy, more power efficient. They are viewed as

electrically controlled switches with a control terminal (base) and 2 other

terminals (emitter and collector) that are connected or disconnected depending

on the voltage applied to the control.

• BJT require small current into the base to switch much larger currents between

other 2 terminals.

• Quiescent power dissipated by these base currents limits the maximum number

of transistors that can be integrated onto a single die.

• MOSFETs offer the advantage that they draw almost zero current while idle and

thus the power consumption is very less.

• Moore’s law: Gordan Moore observed that transistor count doubles every 18

months. Plotting the number of transistors that can be most economically

fabricated on a chip gives a straight line on semi logarithmic scale.

Year

Transistors

40048008

8080

8086

80286Intel386

Intel486PentiumPentium Pro

Pentium IIPentium III

Pentium 4

1,000

10,000

100,000

1,000,000

10,000,000

100,000,000

1,000,000,000

1970 1975 1980 1985 1990 1995 2000


• Level of integration of chips has been classified as small scale (up to 10 gates

e.g. IC7404, half dozen transistors per gate), medium scale (up to1000gates e.g.

IC74161 counter), large scale (up to 10000 gates e.g. 8 bit microprocessor) and

very large scale.

• Transistor size is made smaller by scaling.

� SEMICONDUCTORS

• Silicon forms the basic starting material for ICs.

• Pure silicon has 3 dimensional lattice of atoms. It is a group 4 element, forming

covalent bond with 4 adjacent atoms and as all its valence electrons are involved

in chemical bonds, it is a poor conductor. (intrinsic semiconductor)

• Conductivity is raised by introducing small amounts of impurities into Si lattice.

(Extrinsic semiconductor). These impurities are called dopants.

• Group 5 dopants such as Arsenic (AS) having 5 valence electrons, form n type

semiconductor. (free electron and positively charged ion are left, free electrons

carrying current are negatively charged electrons)

• Group 3 dopants such as Boron (B) having 3 valence electrons, form p type

semiconductor. (a hole and negatively charged ion are left, hole propagates

about the lattice and acts as positive carrier)

• A junction between p type and n type semiconductor is called a diode. When p

type semiconductor (anode) voltage is raised above the n type semiconductor

(cathode), the diode is forward biased. When the anode voltage is less than or

equal to cathode voltage the diode is reverse biased and almost zero current

flows.

� MOS TRANSISTORS

• A MOS transistor is termed as a majority carrier device, in which the current in a

conducting channel between the source and the drain is modulated by a voltage

applied to the gate.

• A MOS structure is created by superimposing several layers of conducting and

insulating materials to form a sandwich like structure.

• These structures are manufactured using a series of chemical processing steps

involving oxidation of the Si, diffusion of impurities into Si to give it certain

conduction characteristics and the deposition and etching of Al or other metals to

provide interconnection.


• CMOS technology provides 2 types of transistors or devices; n type transistor

(nMOS) and p type transistor (pMOS).

• Transistor operation is based on electric field and thus the name MOSFET.

• Each transistor consists of a stack of conducting gate, an insulating layer of

silicon dioxide and the silicon wafer, also called the substrate, body, or bulk.

• An nMOS transistor is built with a p type body and has regions of n type

semiconductor adjacent to the gate called the source and the drain. The gate is a

control input. It affects the flow of electric current between the source and the

drain.

� The body is typically grounded. The p-n junctions of the source and drain to body

are reverse biased.

� If the gate is also grounded, no current flows through the reverse biased

junctions. Thus the transistor is OFF.

� If the gate voltage is raised, it creates an electric field that starts to attract free

electrons to the underside of the Si-SiO2 interface. If the voltage is raised

enough, the electrons outnumber the holes and a thin region under the gate

called channel is inverted to act as an n type semiconductor. Hence a conducting

path of electron carriers is formed from source to drain and the current can flow.

Thus the transistor is ON.

� Thus, in an nMOS transistor, the majority carriers are electrons. A positive

voltage applied on the gate with respect to the substrate enhances the number of

electrons in the channel and hence increases the conductivity of the channel. For

gate voltages less than threshold value denoted by VT (the voltage at which a

MOS device begins to conduct, i.e. turns ON), the channel is cut off, thus causing

a very low drain to source current.

• A pMOS transistor consists of p type source and drain regions with an n type

body.

� The operation of a p-type transistor is analogous to the nMOS transistor, with the

exception that the majority carriers are holes and the voltages are negative with

respect to the substrate.

� The body is held at a high potential, the source and drain junctions are reverse

biased.

� If the gate is at high potential, no current flows, so the transistor is OFF.


� When the gate voltage is lowered, positive charges are attracted to the underside

of the Si-SiO2 interface. A sufficiently low gate voltage inverts the channel and a

conducting path of positive carriers is formed from source to drain, so the

transistor is ON.

• Thus the gate of a MOS transistor controls the flow of current between the source

and drain. When the gate of an nMOS transistor is ‘1’, the transistor is ON and

there is a conducting path from source to drain. When the gate is low, the nMOS

transistor is OFF, and almost zero current flows from source to drain. A pMOS

transistor is ON when gate is low and OFF when gate is high.

� Those devices that are normally cut off (i.e. non conducting) with zero gate bias

(gate to source voltage) are classed as Enhancement mode devices. The

devices that conduct with zero gate bias are called Depletion mode devices.

• The structure for an n channel enhancement type transistor consists of a

moderately doped p type silicon substrate into which two heavily doped n+

regions, the source and the drain, are diffused. Between these two regions, there

is a narrow region of p type substrate called the channel, which is covered by a

thin insulating layer of SiO2 called the gate oxide, Over this oxide layer, is a

polycrystalline silicon (polysilicon) electrode referred to as the gate.

� A positive voltage applied on the gate with respect to the substrate increases the

conductivity of the channel.

• A second type of the MOS device, Depletion mode MOSFET, can be made if to the

basic structure, a channel is diffused between the source and the drain, with the

same type of impurity as used for the source and the drain diffusion. Thus an

appreciable drain current flows for zero gate to source voltage VGS = 0.

� If the gate voltage is made negative, positive charges are induced in the channel,

thus causing depletion of majority carriers i.e. electrons, which makes the

channel less conductive and the drain current drops as VGS is made more

negative.


This views the process as one where we provide the basic necessities such as money, an

idea, and marketing information and dump them all into a “magic technology funnel”.

Adding a pile of sand as raw material produces the super chip at the bottom that will sell

millions of units. Engineers and scientists are needed some where in the process, but

they just put the things together. The complexity and capability of present-day VLSI

technology is extraordinary. To achieve the full potential of VLSI technology, it is

necessary to develop and use computer aids that provide significant assistance in the

design and analysis of complex VLSI systems. CAD techniques support the reduction of

design time and the optimization of the circuit quality.


� VLSI DESIGN FLOW




• Design specifications: The specifications to be mentioned in VLSI design are as

follows.

� The algorithm to be implemented in detail with mathematical representation: The

algorithm specification determines the complexity of the design and gives an idea

of number of gates required for the design.

� Number of inputs and outputs in the design and number of bits in each of them:

This takes into account the type of interface to be used with the chip (e.g. for

interfacing A/D converter, all the data lines and control lines i/ps and o/ps are

provided in the chip). It also determines the number of pins to be used in the

chip.

� Number of bits used in the internal arithmetic operation: This is kept higher than

the i/p bus size in order to avoid chances of overflow and underflow and also

reduce the effect of accumulation of round off errors to maintain the required

accuracy. In the hardware implementation of an arithmetic intensive algorithm,

the word lengths of resources such as adders multipliers and registers has an

algorithmic level optimization to meet the desired accuracy and minimization of

design cost to meet a given performance constraint.


� Number of clock signals to be used in the design: This is required because clock

routing requires dedicated channels, which must be considered during fabrication

of the chip. For a programmable type of prefabricated ICs, maximum number of

clock signals that can be used is predefined.

� Maximum clock frequency to be used: It defines speed of operation of the chip.

Maximization of operating speed is one of the main objectives in VLSI design

since faster operation needs lesser computation time. (If the chip interfaces with

very high speed devices, or if it has to perform real time computation of huge

complex and mathematically intensive algorithm, then the speed of operation of

the chip becomes very critical).

� Area of the chip: For portable type and miniature type of systems, chip size

should be as small as possible. Since million or more number of gates are

incorporated on a single chip, main optimization goal is area of the chip in IC

design.

� Power dissipation in the chip: The demand for portable semiconductor devices

has raised the demand for more power efficient devices. Thus VLSI design has

also an objective of circuit level power saving by modifying circuit design such as

reduction of switching activity.

• Design Entry:

� First the architectural design decision like number of sub-blocks to e used with

their functionality and interconnects such as adders, multipliers, dividers type of

processing, serial or parallel, in each sub-blocks and whether the design will be

pipelined, number of stages in the pipeline and operation in each stage are taken.

� Design entry is of two types: (a) Schematic Entry (b) Hardware description

language (HDL) entry.

� In Schematic entry circuit schematics are drawn on schematic sheets using

Graphical User Interface (GUI). Schematic library is available which consists of

symbols of basic gates and flip flops that are termed as primitive cells. The cells

required to make a design are invoked on the sheet and interconnections

between components is done using nets for single bit line and buses for multiple

bit line. User created macros can be stored in the library. In Schematic entry,

hierarchical design is approached. Large designs are divided into sub-designs,

which are further subdivided.


� The 2 dominant HDLs are VHDL and Verilog HDL. The digital hardware is

described using the language in structural, dataflow or sequential behavioral

style.

• Functional Simulation:

� For schematic and HDL designs, functional simulation is performed before design

implementation to verify that the logic created is correct or wrong. For schematic

flow projects, functional simulation is performed directly after completing design

within design entry tools. For HDL flow projects, functional simulation is

performed after the design has been entered and synthesized. To find the errors

encountered in the design, stimulus or input vectors are given at the input and

output response is observed. If the output response complies with desired

output, then it can be said that the design is functionally correct. If there is a

deviation, then the location of errors is found out by checking intermediate

outputs and the design is corrected and re-verified.

• Planning placement and Routing (PPR):

� This part is referred to as VLSI physical design or layout phase. This is the

process to determine the physical location of devices and make interconnection

between them inside the boundary of VLSI chip. As the cost of circuit fabrication

increases in proportion with circuit area, one of the main aims in layout phase is

to minimize the circuit area so that cost of chip is reduced. If the chip area is

smaller, it will have fewer defects, which in turn increases the yield. The other

criteria to be fulfilled are wire length minimization, delay minimization, power

minimization, via minimization. The various phases in layout process are as

follows:

o Partitioning is the task of dividing a circuit in such a way so that area of each sub

circuit is well within prescribed range and number of interconnection between the

sub circuits is also minimized. In VLSI physical design, partitioning is the first

step of solving a large problem by converting it to smaller sub problems of

manageable size.

o Floor planning is the step to determine the shape of each sub circuit module and

pin locations at their boundary and find out the approximate location of each

module in a rectangular chip. A good Floor planning aims to reduce the chip area,


make the subsequent routing phase simpler and improve performance like signal

delay reduction.

o Placement is the problem of determination f best position of each module, when

each module has a fixed shape, area and terminals. Floorplanning and

placements are very closely related and sometimes combined in a computer

aided design automation process.

o Routing is the method of interconnection of different circuit components, with an

aim to minimize the chip area and also reduction of total wire length. Routing

consists of a two step approach: global routing is done first and then followed by

channel routing. The main aim of global routing is to develop a routing plan so

that each net is assigned a particular region. It partitions routing region to

disjoint rectilinear sub regions and also gives an estimation of total wire length.

Then detailed routing is done to effectively realize the interconnections. In

detailed routing there are 2 kinds of rectilinear sub regions, channels and switch

boxes. Channels are routing regions having 2 parallel rows of fixed terminals.

Switch boxes are generalized channels having fixed terminals on all 4 sides of the

region. The objective of a channel router is to connect all the nets with minimum

possible area. After PPR if all the components do not fit into a given chip size, or

if the design may not be routed, then few iterations of PPR is done to achieve

successful routing. If it still fails, then the design entry is revisited by changing

some parallel processors to serial processors.

• Timing Simulation:

� After a successful PPR timing simulation is performed.

� After the design is fitted into the chip, net delays and gate delays come into

account. Net delays are delays encountered by a signal for traversing from output

of one gate to input of another ate. Gate delays are delays from input of one gate

to output of same gate due to propagation time of the gate.

� The timing simulation is done with the clock speed as per mentioned in design

specification. Input stimuli are given and output is verified.

� Timing analysis is done to see the timing performance of a circuit such as set up

and hold times of the flip-flops are met. It gives detailed report of all gate delays

and net delays of all the paths in the circuit to check whether they meet the

timing constraints of the design.


• Fusing/Fabrication into the chip:

� The last step in VLSI design is chip fabrication. There are 2 different VLSI design

styles used (i) full custom, (ii) semi custom.

� In a full custom design the semiconductor chips are Application Specific

Integrated Circuits (ASICs) which are designed specifically for a given application

or application domain. Full custom designs involve the complete design to be

hand-crafted in transistor level so as to optimize the circuit for performance and

area for a given application.

� Semi custom designs can be divided into 2 major classes: cell based design and

array based design.

� Cell based designs use libraries of predesigned cells which are then placed and

wired to complete the design.

� Array based designs use a prefabricated matrix of non connected components.

� FPGA uses programmable logic modules and also programmable interconnections

in which configuration data is loaded during each application. FPGAs are

prefabricated. The programming data is fused into the programmable IC chips in

order to make it functioning as per design. Programming data is written in PROM

and the FPGA load configuration data from PROM during power on or again when

reprogramming is required.

� In ASIC design the final step is the mask generation phase. The masks are the

geometrical patterns which are used for etching in lithography in subsequent

VLSI fabrication. The mask is generated using technology files of targeted

foundry. The output data of the design process is sent to the foundry which

manufactures the chip using masks.


� VLSI DESIGN STYLES OR METHODOLOGIES

� In a full custom design the semiconductor chips are Application Specific Integrated

Circuits (ASICs) which are designed specifically for a given application or application

domain.

In a full custom design, the functional and physical designs are handcrafted, in

transistor level so as to optimize the circuit for performance and area for a given

application. The entire mask design is done anew without use of any library.

However, the development cost of such a design style is prohibitively high. Thus, the

concept of design reuse is followed in order to reduce design cycle time and

development cost.

The most rigorous full custom design can be the design of a memory cell, be it static

or dynamic.

Since the same layout design is replicated, there would not be any alternative to

high density memory chip design.

For logic chip design, a good compromise can be achieved by using a combination of

different design styles on the same chip, such as standard cells, data-path cells and

PLAs. In real full-custom layout in which the geometry, orientation and placement of

every transistor is done individually by the designer, design productivity is usually

very low - typically 10 to 20 transistors per day, per designer.

In digital CMOS VLSI, full-custom design is rarely used due to the high labor cost.

Exceptions to this include the design of high-volume products such as memory chips,

high- performance microprocessors and FPGA masters.

� Semicustom design is based on the concept of restricting the circuit primitives to a

limited number, and reducing the possibility of fine tuning all parts of a circuit

design. CAD tools are used for design and optimization and to reduce the design

time.

To enable automated placement of the cells and routing of inter-cell connections,

each cell layout is designed with a fixed height, so that a number of cells can be

abutted side-by-side to form rows. The power and ground rails typically run parallel

to the upper and lower boundaries of the cell, thus, neighboring cells share a

common power and ground bus. The input and output pins are located on the upper

and lower boundaries of the cell.

Semi custom designs can be divided into 2 major classes: cell based design and

array based design. These classes further subdivide into subclasses as shown in the

FIG.

• Cell based designs use libraries of predesigned cells which are then placed and

wired to complete the design. It also uses cell-generators that synthesize macro-

cell layout from their functional specifications. Here the manufacturing process is


not simplified at all with respect to custom design. Instead, the design process is

simplified, because of the use of ready-made building blocks.

Cell-based designs are further classified into standard-cell design and macro

cells.

� In standard-cell design style, all of the commonly used logic cells are

developed, characterized, and stored in a standard cell library.

A typical library may contain a few hundred cells including inverters,

NAND gates, NOR gates, complex AOI, OAI gates, D-latches, and flip-

flops.

Each gate type can have multiple implementations to provide adequate

driving capability for different fan outs. For instance, the inverter gate

can have standard size transistors, double size transistors, and

quadruple size transistors so that the chip designer can choose the

proper size to achieve high circuit speed and layout density.

Library has to be maintained as each cell needs to be parameterized in

terms of area and delay over ranges of temperatures and operating

voltages.

The user’s design has to be confirmed to the available library

primitives, a step called library binding or technology mapping.

The cells are placed and wired.

An extension is the hierarchical standard-cell style, where larger cells

can be derived by combining smaller ones.

� Macro-cell based design consists of combining building blocks that can

be synthesized by computer programs, called cell or module

generators.

The sophisticated generators have been able to synthesize the

memory arrays and PLAs, and the layouts of various circuits with a

device density and performance superior to that achieved by human

designers.

The user of macro-cell generator provides the functional description.

Macro-cells are then placed and wired. Even though these steps have

been automated, these are less efficient compared to that of standard-

cell placement and wiring due to the irregularities in size of the macro-

cells.

A major advantage of cell-based design is the compatibility with custom design.

Custom components can be added to semicustom layout and vice versa.

The combination of custom design and cell based design is referred to as

structured custom design.

• Array based designs use a prefabricated matrix of non connected components

often called sites. Such components are then personalized and interconnected.


Array based circuits can further be classified as prediffused and prewired, also

called mask programmable and field programmable gate arrays respectively

(MPGA, FPGA).

� In prediffused gate arrays, batches of wafers, with arrays of sites, are

manufactured. The chip fabrication process entails programming the sites, by

connecting them to wires i.e. by manufacturing the routing layers. As a result,

only the metal and contact layers are used to program the chip, hence the name

“mask programmable”. Fewer manufacturing steps correlate to lower fabrication

time and cost. In addition, the cost of the prediffused batches of wafers can be

amortized over several chip designs.

� Prewired gate arrays are often called field programmable gate arrays because

these can be programmed in the ‘field”, i.e. outside the semiconductor foundry.

They consist of arrays of programmable modules, each having the capability of

implementing a generic logic function.

Programming is achieved in two ways. Wires already present in the form of

segments, can be connected by programming antifuses. (An antifuse is an open

circuit device that becomes a short circuit when traversed by an appropriate

current pulse.)

Alternately, memory elements inside the array can be programmed to store

information that relates to the module configuration and interconnection.

In prewired circuit, manufacturing is completely carried out independently of he

application. The design and customization can be done on field, with negligible

cost and time. But the drawback of this design style is the low capacity of these

arrays and inferior performance as compared to other design styles.

As the technology improves, the capacity and speed of prewired circuits will

improve substantially.

Comparison of different design styles is shown in the table.


Custom Cell-based Prediffused Prewired

Density

Performance

Flexibility

Design time

Manufacturing time

Cost-low volume

Cost-high volume

Very High

Very High

Very High

Very long

Medium

Very High

Low

High

High

High

Short

Medium

High

Low

High

High

Medium

Short

Short

High

Low

Medium-Low

Medium-Low

Low

Very short

Very short

Low

High

� CIRCUIT MODELS

� VIEWS OF A MODEL

� LEVELS OF ABSTRACTION


� DESIGN HIERARCHY

The use of hierarchy or “divide and conquer” technique involves dividing a module

into sub- modules and then repeating this operation on the sub-modules until the

complexity of the smaller parts becomes manageable. This approach is very similar

to the software case where large programs are split into smaller and smaller sections

until simple subroutines, with well-defined functions and interfaces can be written.

The concept of Design Hierarchy allows us to build up complex networks by starting

at primitive levels and adding cells as deemed useful. In this manner, various

libraries can be built and maintained for use in many different projects. Complex

systems are broken down into manageable sections, and the concept of building

chips with millions of transistors becomes a reality.

The key to creating hierarchy lies in the concept of cells. A cell is a collection of

objects that is treated as a single entity.

The simplest cells consist of only polygons. The logic gates such as NOT, NAND2 and

NOR2, fall in this category. A cell with this property is said to be flat; this means that

every object is independent and not related to any other object. In a flat cell, the

polygons can be altered without affecting anything else. To initiate the design

process, large number of flat cells are created and stored in a library. Transistors and

logic gates, stored in the library, are used as building blocks in more complex

designs.

Once the initial library is established, the cell entries can be used by instancing them

in the layout to be designed. An instance is a copy of the cell in the library. The

internal structure of the instanced object cannot be altered at a higher level, as it is

the exact replica of the library entry. The only way to change the characteristics of

an instance is to change the library entry. The new layout will be a more complex

object that can itself be stored as a cell in the library. New cells are designed using

the instances of primitive library and polygons of their own. This can be saved in the

library, for use in more complex designs.

This process is repeated as needed, and new cells become a part of the library, and

are used to build other cells. The final cell collection chosen from the library contains

the great majority of the cells needed for the design project.


At the most primitive level, the cells consist of only polygons representing the

material layers. This is designated as level-1 in the hierarchy. Level-2 cells consist of

polygons and instances of level-1 cells. The next group, level-3, consists of polygons

and may contain the instances of level-1 and level-2 entries. This process is repeated

as needed.

To alter an instance, for example, if a level-1 cell is instanced into a level-3 cell, the

level-3 design treats it as being invariant. To alter the level-1 cell, one must return

to the original level-1 design. Any changes in the cell will propagate to all higher

levels where the cell was instanced. (FIG)


Although the contents of an instance can be changed, it is possible to decompose it

into polygons by the Flatten command. After a cell is flattened, all references to the

original cell are lost and individual features of the circuit can be modified. A flattened

cell cannot be restored to its original instanced form.

System design can be from the top down, starting with the design goals in terms of

inputs/outputs, states and functional subsystems, with the designer then iterating until

the design is completed.

The design can also proceed from the bottom top, starting with basic building blocks,

such as PLAs, ROMs, multiplexers, decoders, registers, buses, and input/output pads.

From these the designer can construct larger subsystems such as arithmetic logic units,

again iterating until satisfactory design is reached.


� CONCEPTS OF REGULARITY, MODULARITY AND LOCALITY

� The hierarchical design approach reduces the design complexity by dividing the

large system into several sub-modules. Usually, other design concepts and

design approaches are also needed to simplify the process.

� Regularity means that the hierarchical decomposition of a large system should

result in not only simple, but also similar blocks, as much as possible.

� Modularity in design means that the various functional blocks which make up

the larger system must have well-defined functions and interfaces. Modularity

allows that each block or module can be designed relatively independently from

each other, since there is no ambiguity about the function and the signal

interface of these blocks.

� By defining well-characterized interfaces for each module in the system, it is

effectively ensured that the internals of each module become unimportant to the

exterior modules. Internal details remain at the local level. The concept of

locality also ensures that connections are mostly between neighboring modules,

avoiding long-distance connections as much as possible.


� SCALING

� Scaling means reducing or decreasing the feature size i.e. length and width of the

transistor. Proper scaling enables to shrink a design to new, smaller line-width

capabilities. Scaling down of feature size leads to improved performance. The

figures of merit such as minimum feature size, number of gates on one chip,

power dissipation, maximum operational frequency, die size and production cost

can be improved by shrinking the dimensions of the transistors, interconnections

and the separation between the features, and by adjusting the doping levels and

supply voltages.

� Advantages of scaling are

(i) A design, if shrunk, produces more die / wafer because the die is

reduced in size.

(ii) For a standard chip size, larger logic or memory circuits can be

achieved.

(iii) Faster switching speeds are possible with smaller devices.

� Limitations of scaling are

(i) After scaling, current density increases and if it exceeds the maximum

allowable limit, it may lead to ‘metal migration’ and subsequent

blowing of the conducting paths.

(ii) Due to scaling of supply voltage, VDD, we lose a healthy difference

between logic 1 and logic 0.

(iii) As the channel length L decreases, depletion regions around source

and drain come closer. If L is decreased too much, depletion regions

may meet and transistor action ceases to exist.

(iv) As substrate doping increases, L and VDD can be decreased.

g

s

d

g = 0

s

d

g = 1

s

d

g

s

d

s

d

s

d

nMOS

pMOS

OFFON

ONOFF


n+ n+

p-type body

W

L

tox

SiO2 gate oxide

(good insulator, εox = 3.9)

polysilicon

gate

n+ n+

p-type body

+

Vgd

gate

+ +

source

-

Vgs

-drain

Vds

channel-

Vg

Vs

Vd

Cg

• A MOS transistor is termed as a majority carrier device, in which the current in a

conducting channel between the source and the drain is modulated by a voltage

applied to the gate.

• In an nMOS transistor, the majority carriers are electrons. A positive voltage

applied on the gate with respect to the substrate enhances the number of electrons

in the channel and hence increases the conductivity of the channel. For gate voltages

less than threshold value denoted by VT (the voltage at which a MOS device begins

to conduct, i.e. turns ON), the channel is cut off, thus causing a very low drain to

source current.

• The operation of a p-type transistor is analogous to the nMOS transistor, with the

exception that the majority carriers are holes and the voltages are negative with

respect to the substrate.

• Threshold voltage denoted by VT is the voltage at which a MOS device begins to

conduct, i.e. turns ON.

• Those devices that are normally cut off (i.e. non-conducting) with zero gate bias

(gate to source voltage) are classed as Enhancement mode devices. The devices

that conduct with zero gate bias are called Depletion mode devices.

The n channel and p channel transistors are dual of each other i.e. the voltage

polarities required for correct operation are the opposite. The threshold voltages for

the n channel and p channel devices are denoted by VTn and VTp respectively.

nMOS devices are formed in a p type substrate of moderate doping level. The source

and the drain regions are formed by diffusing n type impurities through suitable masks

into these areas to give the desired n impurity concentration and give rise to depletion

regions which extend mainly in the more lightly doped p regions. Thus source and drain

are isolated from one another by two diodes. Connections to source and drain are made

by a deposited metal layer. In order to make a useful device , there must be the

capability for establishing and controlling a current between source and drain and this is

commonly achieved in one of the two ways, giving rise to Enhancement mode and

Depletion mode transistors.


nMOS Enhancement mode transistor

The structure for an n-channel enhancement mode transistor, shown in the FIG,

consists of a moderately doped p type silicon substrate into which two heavily doped n+

regions, the source and the drain are diffused. Between these two regions, there is a

narrow region of p type substrate called the channel, which is covered by a thin

insulating layer of SiO2 called the gate oxide. Over this oxide layer is a polycrystalline

silicon (polysilicon) electrode referred to as the gate. Polycrystalline silicon is silicon that

isn’t composed of a single crystal. Since the oxide layer is an insulator, the DC current

from the gate to the channel is essentially zero. Because of the inherent symmetry of

the structure, there is no physical distinction between the drain and the source regions.

n+

p

GateSource Drain

bulk Si

SiO2

Polysilicon

n+

n+

p

GateSource Drain

bulk Si

SiO2

Polysilicon

n+

D

1

S

n+

p

GateSource Drain

bulk Si

SiO2

Polysilicon

n+

D

0

S


Since SiO2 has relatively low loss and high dielectric strength, the application of high

gate fields is feasible.

Operation: A positive voltage is applied between the source and the drain (Vds). With

zero gate bias (Vgs=0), no current flows from source to drain. Therefore they are

effectively insulated from each other by the two reverse biased pn junctions, shown in

the FIG (indicated by the diode symbols).

However, a voltage applied to the gate, which is positive with respect to the source and

the substrate, produces an electric field E across the substrate, which attracts electrons

towards the gate and repels holes. If the gate voltage is sufficiently large, the region

under the gate changes from p type to n type (due to accumulation of attracted

electrons) and provides a conduction path between source and drain. Under such a

condition, the surface of the underlying p type silicon is said to be inverted. The term n-

channel is applied to the structure. The number of carriers and conductivity increases

with the gate voltage. The potential difference between the drain and source is Vds=Vgs-

Vgd. If Vds =0, (i.e. Vgs = Vgd), there is no electric field tending to push current from drain

to source.

polysilicon gate

(a)

silicon dioxide insulator

p-type body+-

Vg < 0

(b)

+-

0 < Vg < V

t

depletion region

(c)

+-

Vg > V

t

depletion region

inversion region


+-

Vgs > V

t

n+ n+

+-

Vgd = V

gs

+-

Vgs > V

t

n+ n+

+-

Vgs > V

gd > V

t

Vds = 0

0 < Vds < V

gs-V

t

p-type body

p-type body

b

g

s d

b

g

s dIds

The FIG (a) shows the initial distribution of mobile positive holes in a p type silicon

substrate of a MOS structure for a voltage Vgs, much less than a voltage VT, which is the

threshold voltage. This is termed the accumulation mode.

As Vgs is raised above VT in potential, the holes are repelled causing a depletion region

under the gate. Now the structure is in depletion mode (FIG b).

Raising Vgs further above VT results in electrons being attracted to the region of

substrate under the gate. A conductive layer of electrons in the p substrate gives rise to

the name inversion mode (FIG c).

The difference between a pn junction that exists in a BJT or diode and the inversion

layer substrate junction is that in pn junction, the n type conductivity is brought about

by a metallurgical process; i.e. the electrons are introduced into the semiconductor by

the introduction of donor ions. In an inversion layer substrate junction, the n type layer

is induced by electric field E applied to the gate. Thus this junction is a field induced

junction.

Electrically, a MOS device therefore acts as a voltage controlled switch that conducts

initially when the gate to source voltage, Vgs, is equal to the threshold voltage, VT.

+-

Vgs = 0

n+ n+

+-

Vgd

p-type body

b

g

s d


+-

Vgs > V

t

n+ n+

+-

Vgd < V

t

Vds > V

gs-Vt

p-type body

b

g

s d Ids

When a voltage Vds is applied between source and drain, with Vgs = VT, the horizontal

and vertical components of electric field due to source-drain voltage and gate to

substrate voltage, interact, causing conduction to occur along the channel. The

horizontal components of electric field associated with drain to source voltage (Vds >0) is

responsible for sweeping the electrons in the channel from the source towards the drain.

As Vds is increased, the resistive drop along the channel begins to change the shape of

the channel characteristics. This behaviour is shown in the FIGs below.

At the source end of the channel, the full gate voltage is effective in inverting the

channel. However at the drain end of the channel, only the difference between the gate

and the drain voltage is effective. When the effective gate voltage (Vgs - VT) is greater

than the drain voltage, the channel becomes deeper as Vgs is increased. This is termed

the linear, resistive or non saturated region, where the channel current Ids is a function

of both gate and drain voltages.

If Vds > (Vgs - VT), then Vgd< VT and the channel becomes pinched off. The channel no

longer reaches the drain. Pinch off occurs because there is insufficient electric field

available to give rise to an inversion layer to create the channel. However, in this case,

conduction is brought about by a drift mechanism of electrons under the influence of

positive drain voltage. As the electrons leave the channel, they are injected into the

drain depletion region and are subsequently accelerated towards the drain.

The voltage across the pinched off channel tends to remain fixed at (Vgs - VT). This

condition is the saturated state in which channel current is controlled by the gate voltage

and is almost independent of drain voltage.

For fixed Vds and fixed Vgs, the factors that influence the level of drain current Ids, flowing

between source and drain are


• Distance between source and drain

• The channel width

• The threshold voltage VT

• The thickness of gate insulating oxide layer

• The dielectric constant of gate insulator, the carrier mobility µ

The normal conduction characteristics of a MOS transistor can be categorized as follows:

• Cut off region: where the current flow is essentially zero (accumulation layer)

• Non saturated region: Weak inversion region where drain current is dependent on

gate and drain voltage with respect to the substrate

• Saturated region: the channel is strongly inverted and the drain current flow is

ideally independent of drain source voltage (strong inversion region)

An abnormal conduction condition called avalanche breakdown or punch through can

occur if very high voltage are applied to the drain. Under these circumstances, the gate

has no control over drain current.

pMOS Enhancement mode transistor

A reversal of p type and n type regions in nMOS yields pMOS. Application of negative

gate voltage with respect to source draws holes into the region below the gate, resulting

in channel changing from n type to p type. Thus a conduction path is created between

source and drain. The conduction results from the movement of holes in the channel. A

negative drain voltage sweeps holes from the source through the channel to the drain.

SiO2

n

GateSource Drain

bulk Si

Polysilicon

p+ p+

0 1 2 3 4 50

0.5

1

1.5

2

2.5

Vds

I ds (mA)

Vgs = 5

Vgs = 4

Vgs = 3

Vgs = 2

Vgs = 1


n+

p

Gate Source Drain

bulk Si

SiO 2

Polysilicon

n+

n channel

Depletion mode transistor action

A second type of MOS device can be made if, to the basic structure, a channel is diffused

between the source and the drain, with the same type of impurity as used for source

and the drain diffusion. With this device an appreciable drain current IDSS flows for zero

gate to source voltage Vgs =0.

If the gate voltage is made negative, positive charges are induced in the channel

through SiO2 of gate capacitor. Since the current is due to majority carriers (electrons),

the induced positive charges make the channel less conductive and the drain current

drops as Vgs is made more negative. The redistribution of charge in the channel causes

an effective depletion of majority carriers, which accounts for the designation depletion

MOS transistor. Because of the voltage drop due to drain current, the channel region

nearest the drain is more depleted than is the volume near the source. This

phenomenon is called pinch off.

The depletion mode MOS transistor can also operate in enhancement mode by applying

positive voltage at the gate, so that negative charges are induced into the n type

channel. Thus conductivity of the channel increases and the current rises above IDSS.


QUESTION BANK

1. What is Moore’s law? Explain this law in the context of evolution of microelectronics.

2. Explain the operation of basic Enhancement type MOSFET with characteristics.

3. Explain the operation of basic Depletion type MOSFET with characteristics.

4. Explain the different VLSI design styles.

5. Explain the complexity of VLSI chip using the idea of the VLSI design Funnel.

6. Explain the general overview of VLSI design hierarchy.

7. Explain the VLSI design flow.

8. With the help of transfer and output characteristics, explain the working of

(i) pMOS depletion type

(ii) nMOS enhancement type transistors

9. Using flow chart, Explain “top-down” and bottom-up” approach in VLSI design.

Documents

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