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Midterm PresentationMidterm Presentation
Project Name: Serial Communication Analyzer
Company Name: Digital laboratory
Presenter Name: Igal Kogan
Alexander Rekhelis
Instructor: Hen Broodney
Semester:Winter 2001/2
Project GoalsProject Goals
Implementation of testing and debugging device for serial communication protocol RS-232 and DSP protocol McBSP.
Both protocols are encoded and/or decoded by Altera FPGA. Also PCI Interface protocol, that implemented in PCI MegaCore, is managed by Altera FPGA.
The design will base on Altera Flex PCI Development Kit and the external devices will connect through bridges that are specially designed as RS-232 and McBSP protocols buffers.
AbstractAbstract
The device will manage the data in several ways:
1) As data buffer it will transfer the data from the input device to the output device.
2) As communication analyzer it will read the data from input, send it to PC through PCI Bus for
processing, and according to user commands will send the updated data to output.
Note: Since the communication is bi-directional, input and output devices can be switched constantly.
Highlights of RS232 protocolHighlights of RS232 protocol
RS-232 is an electrical interface standard between Data Terminal Equipment (DTE) and Data Circuit-Terminating Equipment (DCE) such as modems, PALM, mouse and so.
RS-232 is used for asynchronous data transfer as well as synchronous links.
It appears under different incarnations such as RS-232C, RS-232D, V.24, V.28 or V.10 but essentially all these interfaces are interoperable.
Highlights of McBSP protocolHighlights of McBSP protocol
– Full-duplex communication– Double-buffered data registers, which allow a continuous
data stream– Independent framing and clocking for receive and transmit– Direct interface to industry-standard analog interface chips
(AICs), and other serially connected analog-to-digital (A/D) and digital-to-analog (D/A) devices
– External shift clock or an internal, programmable frequency shift clock for data transfer
– Autobuffering capability through the 5-channel DMA
controller.
Abstract (cont.)Abstract (cont.)
RS-232 RS-232
McBSP McBSP
Serial Communication
Analyzer
System Block DiagramSystem Block Diagram
Altera Flex PCI
Development Kit
PCI
RS-232 Communication
Device
McBSP Communication
Device
RS-232 Communication
Device
McBSP Communication
Device
WinDriver
GUI
Altera PCI Development Board
HardwareHardware
All hardware will be implemented on Altera FLEX PCI Development Kit.
One channel for RS-232 communication is already placed on the kit. The implementation of the second RS-232 communication channel that connects to the Altera on the kit and also the implementation of the connections between two McBSP channels on DSP board to the Altera on the kit board are currently in progress.
We already purchased all needed elements and we will finish the rest of the pin connections shortly.
RS-232 pin out (addition)RS-232 pin out (addition)
TX
U2
MAX208
642217
73
2316
101213141115
5181921
212420
R1OUTR2OUTR3OUTR4OUT
R1INR2INR3INR4IN
C1+C1-C2+C2-V+V-
T1INT2INT3INT4IN
T1OUTT2OUTT3OUTT4OUT
RTSSignals to Altera
C10.1uF
C40.1uF
C50.1uF
RS232_TX_1
C60.1uF
DTR
C30.1uF
RS232_CTS_2
RX
U1
MAX208
642217
73
2316
101213141115
5181921
212420
R1OUTR2OUTR3OUTR4OUT
R1INR2INR3INR4IN
C1+C1-C2+C2-V+V-
T1INT2INT3INT4IN
T1OUTT2OUTT3OUTT4OUT
9-VCC
RS232_CTS_1
Signals to Altera
RS232_DTR_2
CTS
C70.1uF
RS232_RTS_2
RS232_TX_2
RS232_RX_1
P1CON DB9 MALE
5 9 4 8 3 7 2 6 1
RX
8-GND
RI
RTS
DTR
RS232_CD_2
RS232_CD_1
9-VCC
RS232_RTS_1
Signals to Altera
CTS
8-GND
CD
C80.1uF
C20.1uF
RS232_DTR_1
P2CON DB9 MALE
5 9 4 8 3 7 2 6 1
CD
RS232_RX_2
RI
RS232_RI_1Signals to Altera
RS232_RI_2
TX
PC Com Port - EIA-574 RS-232 pin out DB-9 pin used for Asynchronous Data
McBSP pin out (addition)McBSP pin out (addition)J4
CONNECTOR EDGE 80
1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980
FSR1
DX0
CLKX1
DR0
CLKR1McBSP 1
(to Altera)
FSX0
(to Altera)
FSR0
DX1
J3
CONNECTOR EDGE 80
123456789
1011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980
DSP BOARD
McBSP 0
ALTERA side DSP side
CLKR0
CLKX0
DR1
FSX1
McBSP Interface SignalsMcBSP Interface Signals
Pin I/O/Z† DescriptionCLKR I/O/Z Receive clock
CLKX I/O/Z Transmit clock
CLKS I External clock
DR I Received serial data
DX O/Z Transmitted serial data
FSR I/O/Z Receive frame synchronization
FSX I/O/Z Transmit frame synchronization
SoftwareSoftware
We are currently focused on RS232 protocol implementation.
The communication can be handled at: 1200, 2400, 4800, 9600,
19200 baud rate.
In the future the rates can be increased if needed.
The communication rate and condition (with or without
handshake) will be determined by the GUI through the
WinDriver. Control Logic block will provide the proper interactions
between PCI Core and RS232 or McBSP communication blocks (by local bus).
System modules diagram (FPGA)System modules diagram (FPGA)
RS-232
Protocol
RS-232
Protocol
McBSP
Protocol
McBSP
Protocol
Control
Logic
PCI
MegaCore
PCI CorePCI Core
PC
I B
us
Local B
us
.Altera ליחידות לוגיות, כפי שמומש ע”י חברת PCI Coreחלוקת ה-
.Control Logic Block לבין PCI Busתפקידו למנשק בין ה-
FPGA block diagramFPGA block diagram
ScheduleSchedule
Phase1 – Hardware Design
Phase2 – Software Design
Phase3 – Debug
Oct Nov Dec Jan Feb Mar Apr May Jun Jul
Phase 1Phase 2
Phase 3
Schedule milestones are:
Schedule (cont.)Schedule (cont.):לוח זמנים
12/2001 – 01/2002 – הרכבת הפרוייקט , בדיקת התכנון : RS-232 23/12/2001.הצגת דו"ח אמצע לצוות מעבדה - 30/12/2001.הרכבת החומרה - 01/01/2002.יציאה למילואים של אחד מאנשי הצוות - 14/01/2002 סיום מימוש פרוטוקול - RS-232 . 21/01/2002 בדיקות עבודת הפרוטוקול - RS-232 . 30/01/2002 בדיקות עבודת הפרוטוקול - RS-232 +
איתור תקלות. 04/02/2002 .הכנות לבחינות סוף סמסטר - 02/2002 – 03/2002 .בחינות סוף סמסטר : 03/2002 הצגת חלק א' - הצגת כרטיס כולל בדיקות :
ראשוניות, עבודה .RS-232בפרוטוקול
תודה
רבה
Serial Communication Analyzer