Miles Murdocca and Vincent Heuringiiusatech.com/murdocca/POCA/slides/Ch08POCA.pdf · 2006. 12. 4. · 8-1 Chapter 8: Input and Output Principles of Computer Architecture by M. Murdocca

Chapter 8: Input and Output8-1

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring

Principles of Computer ArchitectureMiles Murdocca and Vincent Heuring

Chapter 8: Input and Output



Chapter Contents8.1 Simple Bus Architectures8.2 Bridge-Based Bus Architectures8.3 Communication Methodologies8.4 Case Study: Communication on the Intel Pentium Architecture8.5 Mass Storage8.6 Input Devices8.7 Output Devices



Simple Bus Architecture• A simplified motherboard of a personal computer (top view):

Motherboard

I/O Bus

Board traces (wires)

Connectors for plug-in cards

Integrated Circuits

Plug-in card

I/O bus connector

Memory

CPU



Simplified Illustration of a Bus

CPU DiskMemory

Control (C0 – C9)Address (A0 – A31)Data (D0 – D31)Power (GND, +5V, –15V)



100 MHz Bus Clock

CrystalOscillator

1 0 1 0 1 0 1 0

Logical 0 (0V)

Logical 1 (+5V)

10 ns



The Synchronous Bus• Timing diagram for a synchronous memory read (adapted from

[Tanenbaum, 1999]).

Φ

Address

Data

MREQ

RD

T1 T2 T3Leading edge

Trailing edge

Data valid

Time

Address valid



The Asynchronous Bus• Timing diagram for asynchronous memory read (adapted from

[Tanenbaum, 1999]).

Address

MSYN

RD

Data

Time

Memory address to be read

MREQ

SSYN

Data valid



Bus Arbitration

• (a)Simplecentralized busarbitration; (b)centralizedarbitration withpriority levels; (c)decentralized busarbitration.(Adapted from[Tanenbaum,1999]).

Arbiter Bus grant

Bus request

0 1 2 n. . .

(a)

Arbiter

Bus grant level 0

Bus request level 0

0 1 2 n. . .

(b)

Bus grant

Bus request

0 1 2 n. . .

(c)Busy+5V

Bus grant level k

Bus request level k...



BridgeBased

Bus Ar-chitecture

• Bridging withdual Pentium IIXeon proces-sors on Slot 2.

(Source: http://www.intel.com.)

3200 MB/sec 3200 MB/sec

800 MB/sec

100-MHz System Bus

533 MB/sec 800 MB/sec

AGP 100 MHz

133 MB/sec 33-MHz PCI Bus

40 M

B/s

ec

16.7 MB/sec

ISA Bus

USB #2IDE Bus #2

USB #1

SC

SI B

us

1.5 MB/sec

33 MB/sec

IDE Bus #133 MB/sec

Intel 440GX AGPset

(Host Bridge)

400-MHz Core

512KB-2MB Cache

400-MHz Core

512KB-2MB Cache

2GB 100-MHz SDRAM

AGP 2X Graphics

PCI to ISA Bridge

Keyboard Audio

CD-ROMMouseSnapshot Camera

Hard Disk

Hard Disk

SCSI Interface

Ethernet Interface



Programmed I/OFlowchart for aDisk Transfer

Check status of disk

Disk ready?No

Yes

Send data from memory to disk (when writing) or from disk

to memory (when reading).

Done?No

Yes

Continue

Enter



Interrupt DrivenI/O Flowchart

for a DiskTransfer

Transfer data between disk and memory.

Done?No

Yes

Continue

Return from interrupt. Normal processing

resumes.

Do other processing, until disk issues an

interrupt.

Interrupt causes current processing to stop.

Issue read or write request to disk.

Enter



DMA Transfer from Disk to MemoryBypasses the CPU

CPU DiskMemory

Without DMA With DMA

Bus



DMA Flowchart for a Disk Transfer

CPU executes another process

Continue

DMA device begins transfer independent of

CPU

DMA device interrupts CPU when finished

CPU sets up disk for DMA transfer

Enter



Intel Memory and I/O Address Spaces

AddressFFFFFFFF

00000000

AddressFFFF

0000

MemorySpace

I/OSpace



Standard Intel Pentium Read andWrite Bus Cycles

T1 T2 Ti T1 T2 Ti T1

Read Write

TO CPU FROM CPU

READ CYCLE IDLE IDLEWRITE CYCLE

ADDR

ADS#

Valid ValidInvalid Invalid

W/R#

BRDY#

CACHE#

DATA

CLK



Intel Pentium Burst Read Bus CycleT1 T2 T2 T2 T2 Ti

Read

TO CPU TO CPU TO CPU TO CPU

READ READ READ READ

ADDR

ADS#

Valid Invalid

W/R#

BRDY#

CACHE#

DATA

CLK



Intel PentiumHold-Hold

AcknowledgeBus Cycle

T1 T2 Ti Ti Ti Ti T1

Read

TO CPU

READ CYCLE

BUS REQ.

NEW BUSMASTER

ADDR

ADS#

Valid

W/R#

BRDY#

CACHE#

DATA

HOLD

HLDA

CLK



A Magnetic Disk with Three Platters

Direction ofarm (comb)

motion

Surface 3Surface 2

Surface 1Surface 0

Top surface not used

Bottom surface not used

Spindle

Platter

Head

SurfaceAir cushion

5 µm

Comb

Read/write head(1 per surface)



Manchester Encoding• (a) Straight amplitude (NRZ) encoding of ASCII ‘F’; (b) Manchester

encoding of ASCII ‘F’.

(a)

Time

Vol

tage

1 0 0 0 1 1 0 = ‘F’

(b)

Time

Vol

tage

1 0 0 0 1 1 0 = ‘F’



Organization of a Disk Platter with a1:2 Interleave Factor

Sector

.

.

.

Inter-sector gap

Inter-track gap

Interleave factor 1:2

Track

Track 0

.

.

.

0

8

1

9

2

10

3114

12

5

13

6

14

715



MasterControlBlock

No. surfaces on disk = 4No. tracks/surface = 814No. sectors/track = 32No. bytes/sector = 512Interleave factor = 1:3

Filename

xyz.p

Surface Track Sector

Starting sector, or sector list

Prea

mbl

eFi

les

Free

blo

cks

Bad

blo

cks

1 10 51 12 72 23 4

ab.c 1 10 83 95 22 12 0

1 1 01 1 11 2 5

...

...

1 1 32 5 7

...

CreationDate

LastModified

Owner Protec-tions

11/14/93 11/14/93 16 RWX by10:30:57 19:30:57 Owner

8/18/93 1/21/94 20 RX - All16:03:12 14:45:03 W-Owner

R = ReadW = WriteX = Execute



Magnetic Tape• A portion of a magnetic tape (adapted from [Hamacher, 1990]).

File mark

Record

Inter-record gap

Record Record

File

Frames



Magnetic Drum

Fixed read/writeheads (1 per track)Tracks

Sector



Spiral Format for Compact Disk



ECMA-23 Keyboard Layout• Keyboard layout for the ECMA-23 Standard (2nd ed.). Shift keys

are frequently placed in the B row.

99 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18

F

E

D

C

B

A

Z

Q W E R T Y U I O P

A S D F G H J K L

Z X C V B N M

7 8 9

4 5 6

1 2 3

00 . SP

–

0

1!

2"

3#

4 5%

6&

7'

8(

9)

0 .= ¬̂

¬

@'

[{

;+

:*

/?

,<

.>

]}

\|



The Dvorak Keyboard Layout

P Y F G C R L

A O E U I D H T N S

Q J K X B M W V Z

?/

}{

–-

"'

,,

.

.

:;



Bit Pad with Puck

Puck

Cable to host computer

Coil

Buttons



Mouse and Trackball• A three-button mouse (left) and a three-button trackball (right).

To host

Mousepad (improves traction) Trackball

Mouse

Buttons

To host

Buttons



Lightpen• A user selects an object with a lightpen.



Touchscreen• A user selects an object on a touchscreen.

LEDs (sources)

Detector

User breaks beams



Joystick• A joystick with a selection button and a rotatable rod:



Laser Printer• Schematic of a laser printer (adapted from [Tanenbaum, 1999]).

Paper input

Paper output

The quick brown fox jumps

Heated rollers

Toner cartridge

Cleaner and discharger

Stationary laser source

Page composing

circuitry

Page description from host computer

Charged pattern

Rotating mirror



Cathode Ray Tube• A CRT with a single electron gun:

Horizontal control

Vertical control

Intensity control

Electron gun

Vertical deflection plate

Vacuum

GridHorizontal deflection plate

Phosphor coated screen



Display Controller• Display con-

troller for a640×480 colormonitor(adapted from[Hamacher etal., 1990]).

To horizontal deflection plate control

To vertical deflection plate control

10 9

To

elec

tron

gun

(g

rid)

con

trol Red

Green

Blue8

LUT loaded from computer

Screen image

loaded by computer

Clock Column counter(mod 640)

Row counter

(mod 480)

Address

Out

put

Inpu

t

Out

put

Add

ress

8Input

RAM frame buffer

RAM LUT

8

8

One output pulse per 640 columns

Documents

Miles Murdocca and Vincent Heuringiiusatech.com/murdocca/POCA/slides/Ch08POCA.pdf · 2006. 12. 4. · 8-1 Chapter 8: Input and Output Principles of Computer Architecture by M. Murdocca