MIPI Alliance Overview - pudn.comread.pudn.com/downloads423/sourcecode/book/1790499/MIPI_D-PHY_Tutorial… · • Data are launched and sampled with a DDR clock supplied on the Clock

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Copyright © 2004 MIPI Alliance. All rights reserved. MIPI Alliance Confidential1

Copyright © 2005 MIPI Alliance. All rights reserved. MIPI Alliance Confidential

D-PHY Tutorial

PHY Working Grouprepresented by

Gerrit den Besten (Philips)

David Meltzer (Epson)

MIPI Alliance Confidential

Legal Disclaimer

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The material contained herein is not a license, either expressly or impliedly, to any IPR owned or controlled by any of the authors or developers of this material or MIPI. The material contained herein is provided on an “AS IS” basis and to the maximum extent permitted by applicable law, this material is provided AS IS AND WITH ALL FAULTS, and the authors and developers of this material and MIPI hereby disclaim all other warranties and conditions, either express, implied or statutory, including, but not limited to, any (if any) implied warranties, duties or conditions of merchantability, of fitness for a particular purpose, of accuracy or completeness of responses, of results, of workmanlike effort, of lack of viruses, and of lack of negligence. ALSO, THERE IS NO WARRANTY OR CONDITION OF TITLE, QUIET ENJOYMENT, QUIET POSSESSION, CORRESPONDENCE TO DESCRIPTION OR NON-INFRINGEMENT WITH REGARD TO THIS MATERIAL.

IN NO EVENT WILL ANY AUTHOR OR DEVELOPER OF THIS MATERIAL OR MIPI BE LIABLE TO ANY OTHER PARTY FOR THE COST OF PROCURING SUBSTITUTE GOODS OR SERVICES, LOST PROFITS, LOSS OF USE, LOSS OF DATA, OR ANY INCIDENTAL, CONSEQUENTIAL, DIRECT, INDIRECT, OR SPECIAL DAMAGES WHETHER UNDER CONTRACT, TORT, WARRANTY, OR OTHERWISE, ARISING INANY WAY OUT OF THIS OR ANY OTHER AGREEMENT RELATING TO THIS MATERIAL, WHETHER OR NOT SUCH PARTY HAD ADVANCE NOTICE OF THE POSSIBILITY OF SUCH DAMAGES.

MIPI Alliance Confidential

Overview

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• Introduction• Architecture• Electrical• Timing • Global Operation• Interconnect• PHY-Protocol Interface• Summary• Q & A

Objectives

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• Specify an unified PHY which supports: • Display protocol• Camera protocol• Future MIPI protocols,

including UniPRO

• Features• High bandwidth• Minimal power• Supports technology scaling • Low implementation complexity

Physical Layer

protocolinterface

lineinterface

CSI-2CSI-2 DSIDSIOther

protocolse.g.

UniPRO

Otherprotocols

e.g. UniPRO

Pro

toco

lP

HY

Application Requirement Summary

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• Bit rate 80-1000 Mb/s• Across ‘bad’ channels including flex-foils• Distance 0-20cm• Low operational power (mW-range)• Very low stand-by power (µW-range)• Low EMI• Low wire count• Robustness in a noisy environment

• noise magnitude: ~10mVdif ~100mVcom

• Support for bi-directionality• Ease of integration• Lane scalability

Overview

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Conceptual choices

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• Serial High-speed: Fully terminated differential signaling• Low-Power: Unterminated 1.2V CMOS-like signaling• Transmission line interconnect needed• First generation: Source synchronous & no encoding• Bi-directionality and contention detection

HSRX

HSTX/RX

HSRX

HS TX

HSTX/RX Tri-state

full-swing TX/RX

Tri-statefull-swing

TX/RX

HSTX

PHY Configuration

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Reference Clock

D-PHY Master Clock Lane Module

D-PHYMaster Data Lane Module

ClockMultiplier

Unit

• One Clock Lane for one or more Data Lanes• Source Sync: Clock direction from Master to Slave

Master Side

Controls

D-PHYSlave Clock Lane Module

D-PHYSlave Data Lane Module

PPI

Slave Side

D-PHYSlave Data Lane Module

D-PHYMaster Data Lane Module

Data1

Clk

Data2

PPI

PPI

PPI

PPI

PPI

transmitclocks

Universal Lane Architecture

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LaneControl

andInterface

Logic

PPI(appendix)

Line Side

HS-TX

RT

LP-RX

Dp

DnHS-RX

LP-TX

LP-CD

TX

RX

CD

Data-in

Data-out

Clocks-in

Clocks-out

Control-in

Control-out

Protocol Side

Universal Lane ArchitecturePPI

(appendix)

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Lane Control & Interface Logic

Sequences

HS-Serialize

State Machine(incl Enables, Selects

and System Ctrl)

Error detect

DataSampler

Esc Encoder

HS-Deserialize

Ctrl Decoder

DataIF

logic

Data-in

Data-out

Clocks-in

Clocks-out

Control-in

Control-out

TX Ctrl Logic

Esc Decoder

CtrlIF

logic

HS-TX

RT

LP-RX

Dp

DnHS-RX

LP-TX

LP-CD

TX

RX

CD

Line Side

Protocol Side

Mandatory versus Optional

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Mandatory• High-Speed Forward signaling• Basic Forward Low-Power Control Capabilities

Optional features• Escape Mode signaling in Forward direction • Bi-directionality

• High-Speed Reverse Signaling• Escape Mode signaling in Reverse direction

Overview

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Low Power & Low EMI on 2 Wires

13



HS-TX

R

LP-RX

Dp

DnHS-RX

LP-TX

LP-CD

T

Line Side

TX

RX

CD

V

• LP signaling• Single-ended unterminated 1.2V CMOS like signaling• Rout and Trise/fall specified for low EMI • No static power

• HS signaling• 200mV differential• 200mV common-mode• Double terminated

Reference ground

Min LP-RX threshold

VDD (1.2V-3.3V+)

Large Signal Margins

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HS VOUTRange

HS VCMRange

360

LP ThresholdRegion

LP VIH

GND

1.1V

LP VOL

Min VOD

250

150

LP VIL

1.3V

880mV

550mV

+50mV-50mV

LP VOH

Tran Rec

460

330

70-40

140 mV < |Differential Signal| < 270mV70mV

Rec

TX

Rec

TX

HS Driver & Receiver

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Pre-

drive

rV REG

Dp

Dn

terminationenable

C CM

ZID/2

ZID/2

ZOD

ZOD

• Differential Receiver• 100Ω Differential Termination• Common-mode decap to ground• Switchable termination• Common mode AC rejection

(200mV at >450MHz)

• Voltage or Current Mode Driver• ZOD = 50 Ω nominal• Switchable to “Tristate”• Minimum rise time = 150ps• Maximum rise time = .3UINOM

LP Driver & ReceiverDP and DN are two independent single-ended links in LP-mode!

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Pre-

drive

r

1.2V

Low Pass Filter

High/Low Threshold

Comparator with HysteresisZOLP

• Driver specified as Thevenin Equivalent V & Z• ZOLP for low EMI• Trise/fall <25ns for 70pF load

• Receiver specified for noise rejection, not speed• LPF input rejects up to 400mV of RF at f > 450 MHz• Glitches rejection of <300V-psec • Hysteresis >25mV

I

VV 2 = 850 mV

VDD110 O

VDD – V 2110 O

~ 110 O

-I

V350 mV

~ 110 O

-3 .2 mA

Drive LP 1

PMOS

NMOS

Drive LP 0

Line Contention Detection• If LP bidirectional functions present in lane, LP contention detection

must also exist• LP receiver must always be enabled and observed (sampled)• LP-CD circuit must be provided

• Two contention situations must be detected by D-PHY hardware• 2 LP TX driving opposite levels on same line• LP TX drives LP1 while HS TX drives HS0

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LP TXOutput High

LP ThresholdRegion

VIL,MAX

VOL,MAX

GNDVOL,MIN

V IH,MIN

VOH,MIN

VOH,MAX

Low Power-Transmitter

LP RXInput High

LP RXInput Low

LP TXOutput LOW

Low Power-Receiver

LP ContentionFault Threshold

VILF,MIN

V ILF,MAX

Low Power-Fault Detector

actual

actual

expects

expects LP TX drives hiRec Vin<VIHMIN

LP TX drives lowLP-CD Vin>VILFMIN

Electrical Summary

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• Electrical specification enables robust sharing of signal pair between High Speed and Low Power mode communication within 1.2V

• Doubly terminated 50Ω single-ended/100Ω differential in HS• High Input noise rejection for LP mode

• Minimizes radiated EMI and EMI susceptibility• High data transmission rate at low BER, low power in

hostile environment• Low speed channel without DC power

• Provision made to minimize standby power if 1.2V regulator required (ULPM)

• Optional half-duplex, bidirectional operation

Overview

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• Introduction• Architecture• Electrical• Timing• Global Operation• Interconnect• PHY-Protocol Interface• Summary• Q & A

High Speed Clock Timing

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• Data are launched and sampled with a DDR clock supplied on the Clock Lane from Master side

• DDR clock generation not part of D-PHY• PLL characteristics determine how to meet timing specs

• All D-PHY HS Clock timing specs normalized to UI• D-PHY operates in range of 80Mbps to <1Gbps /Data Lane

• Forward data transfers are source synchronous• Optional reverse data transfers are Master synchronous• Clock is always in quadrature to data

• Simplifies slave design

Forward Data Transfer Timing

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TSETUP

CLKp

CLKn

1 UI INST

Reference time

0.5 UI INST+TSKEW

Tclkp

T HOLD

Total .3UI SU+Hld window for receiver

Large Clock and Data Jitter + duty cycle distortion allowed[referred to 1us average]

All timings referenced toCrossing of clock signal pair

Optional Reverse Data Transfer Timing• Clock is supplied by master (not Source Synchronous)• Data rate = ¼ of possible forward rate

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• Slave uses any edge of DDR clock to launch data

• Master determines which edge to use to sample received data

• Data to clock skew and round trip delay not specified

• Same UI variation in clock as forward transfer

NRZ DATA

2UI2UI

CLKp

CLKn

Clock to data Skew TTD

Overview

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Data Lane Flow Diagram

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TX

HST

HS-RqstLP-01

LP-RqstLP-10

EoTSoT

StopLP-11

Trigger

LPDTULP

EscapeMode

TurnaroundLP-00>10>00>10

RX Trigger

LPDT

ULPEscapeMode

Wait

InitMaster

InitSlave

HS-PrprLP-00

HST

HS-RqstLP-01

LP-RqstLP-10

EoTSoT

StopLP-11

TurnaroundLP-00>10>00>10

HS-PrprLP-00

Source Sync: Data Burst

CLKTSOT

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capture 1st data bit

• Clock keeps running and samples data lanes (except for lanes in LPS)• Unambiguous leader and trailer sequences required to distill real data bits• Trailer is removed inside PHY (a few bytes)• Time-out to ignore line-values during line-state transition

TEOT

THS-SETTLE

THS-SYNC

THS-LEAD

THS-TRAIL THS-EXIT

disconnectterminator

THS-SKIP

THS-ZEROTLPX THS-PREPARE

LP-01 LP-00Dp/Dn

LP-11SYNCLP-11

Link turnaround

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• All during Low-Power mode• Request sequence (LP11)-LP10-LP00-LP10-LP00…..• Actual switching of direction during double LP-00 drive: no glitch• Line levels remain always well-defined

TTA-GOTLPX TLPXTLPX

driveoverlap

TTA-GET TLPXTTA-SURE TLPX

LP-10 LP-10LP-11 LP-00 LP-00 LP-00 LP-10 LP-11LP-00

LP Escape Mode

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• A special mode of operation for Data Lanes using the low power line states

• Asynchronous communication using two wires• Does not depend on clock lane• Maximum data rate 10 Mbit/s

• Escape mode commands add extra 8 functions• Low power data transfer• Ultra low power mode• 4 remote triggers• 2 reserved functions

• Function selected by Entry codes• 8-out-of-256 codes selected for maximum robustness• In case of code mismatch everything is ignored till next Stop state

Escape Mode signalingTrigger Reset Example

LP-11>10>00>01>00>01>00>10>00>……..

0 1 1 0 0 0 1 0

Escape Mode Entry

Dp

Dn

LP Clk=EXOR(Dp,Dn)

Entry Command Mark & Stop:Exit Escape

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Escape Mode signalingTwo Byte LPDT Example

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Escape Mode Entry

Dp

Dn

LP Clk = EXOR(Dp,Dn)

First Data Byte01110101

Exit Escape

LPDTCommand

Second Data Byte11010000

Pause:Asynchronousno transition

Clock Lane Flow Diagram

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• Electrically identical to Unidirectional data lane

• No Escape Mode• Unidirectional,

no Turnaround• Special short

ULP entry(“Sleep mode”)

TX

HST

HS-RqstLP-01

ULP-RqstLP-10

EoTSoT

StopLP-11

RX

InitMaster

HS-PrprLP-00

ULP-exitLP-10

ULPLP-00

HST

HS-RqstLP-01

ULP-RqstLP-10

EoTSoT

StopLP-11

InitSlave

HS-PrprLP-00

ULP-exitLP-10

ULPLP-00

Clock Lane Low-Power

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• Clock must be reliable during HS transmission and mode-switching• Clock can go to LP only if Data lanes are in LP (and nothing relies on it)• In Low-Power Data lanes are conceptually asynchronous

(independent of the High-Speed Clock)

TLPX

THS-SETTLE

THS-SKIP

Dp/Dn

TEOT

TCLK-POST


TCLK-SETTLE

TCLK-ZERO

TCLK-PRE

THS-EXIT

TCLK-MISS

TCLK-TRAIL THS-PREPARE


TLPX

CLK

THS-PREPARE

Overview

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Configuration & Characterization

TLISTX/RX RX/TX

Transmission Line Interconnect Structure

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• Split at PHY Modules pins• Interconnect structure considered as one black box

characterized by S-parameters over Frequency

• S-parameters• Differential Transfer• Differential Reflection• Common-mode reflection• Mode conversion

• Frequencies• Low-frequency• Fundamental signaling

frequency• Interference frequencies

Characterization & S-Parameters

RX/TX

Vc1+ Vd1/2

Vc1-Vd1/2

Z0=50

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measurement equipment

port 1 Vc1+ Vd1/2

Vc1-Vd1/2

Z0=50

port 2

TLIS

Vc1+ Vd1/2

Vc1-Vd1/2

Z0=50

measurement equipment measurement equipment

Example: Sdd21 & Sdd12 Interconnect

-2 dB-0.5 dB

f/fh0 1

-5 dB

3

0

Sddij[dB]

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Overview

36




PHY-Protocol Interface (PPI)

37



• Hides line states and Encodings from Protocol layer

• Byte wide interface

• On-chip interface• No sharing of signals• No voltage specifications• Synchronous interface

• Informative exampleprovided in Appendix A • Not covered e.g. error behaviour, simultaneous event behaviour• Many optional signals regarding optional parts of PHY

PPI(appendix)


Sequences

HS-Serialize


and System Ctrl)

Error detect

DataSampler

Esc Encoder

HS-Deserialize

Ctrl Decoder

DataIF

logic

Data-in

Data-out

Clocks-in

Clocks-out

Control-in

Control-out

Protocol Side

TX Ctrl Logic

Esc Decoder

CtrlIF

logic

LineSide

HS-TX

RT

LP-RX

Dp

DnHS-RX

LP-TX

LP-CD

TX

RX

CD

PPI(appendix)


Sequences

HS-Serialize


and System Ctrl)

Error detect

DataSampler

Esc Encoder

HS-Deserialize

Ctrl Decoder

DataIF

logic

Data-in

Data-out

Clocks-in

Clocks-out

Control-in

Control-out

Protocol Side

TX Ctrl Logic

Esc Decoder

CtrlIF

logic

LineSide

HS-TX

RT

LP-RX

Dp

DnHS-RX

LP-TX

LP-CD

TX

RX

CD

HS-TX

RT

LP-RX

Dp

DnHS-RX

LP-TX

LP-CD

TX

RX

CD

PPI Signals and Clocks

• Almost all signals are synchronous to a clock• HS TX Byte Clock• HS Receive Byte Clock• Esc TX Byte Clock• Esc Rec Byte Clock

• No externally supplied clock is assumed on the Slave side for HS transmission in either direction

• High Speed Byte clocks are PHY outputs• Transmit Escape function requires input clock

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Data Handshaking at Transmit Side

• Ready and Valid (or Request)• High-speed request also serves as valid• Escape mode uses separate request and valid signal• Transfer when both signals are active at a rising clock edge

39



Clock

Valid

Data[7:0]

Data TransferWaiting for Ready

Ready

Data Handshaking at Receive Side• No “Ready” signal

• Receive side must always immediately accept the data

40



Clock

Valid

Data[7:0]

Data Transfer

Overview

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Summary

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• D- PHY supports: • DSI Display Serial Interface• CSI2 Camera Serial Interface• UniPRO MIPI Universal Protocol

• Meets all of the objectives• Scalable bit rate 80-1000 Mb/s• Robustness support of ‘bad’ 0-20cm channels• Minimal power mW-range for operation, µW-range for standby• Easy technology scaling 1.2 Volt signal range• Low complexity source-synchronous signalling• Low pin count 2 differential pairs• Bi-directionality for HS (1/4 forward bit rate) and LP• Lane scalability multiple data lanes with a single clock lane

Physical Layer

CSI-2CSI-2 DSIDSIOther

protocolse.g.

UniPRO

Otherprotocols

e.g. UniPRO

43



44



QUESTIONS ?

Documents

MIPI Alliance Overview - pudn.comread.pudn.com/downloads423/sourcecode/book/1790499/MIPI_D-PHY_Tutorial… · • Data are launched and sampled with a DDR clock supplied on the Clock