MIPI CSI-2 Receiver - ザイリンクス - All Programmable CSI‐2 RX サブシステム v2.1 6 PG232 2016 年 11 月 30 日 japan.xilinx.com 第 1 章: 概要 • マルチレーンの相互運用性

MIPI CSI-2 Receiver v2.1

Vivado Design Suite

PG232 2016 11 30

MIPICSI2RXv2.1 2PG23220161130 japan.xilinx.com

IP

1: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

4: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

A: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

B: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

C: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

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MIPICSI2RXSubsystemv2.1 3PG23220161130 japan.xilinx.com Production

MIPI (Mobile Industry Processor Interface) Camera Serial Interface (CSI-2) RX MIPI Alliance Standard for Camera Serial Interface CSI-2 v1.1 [ 1] CSI-2 MIPI CSI-2 AXI4-Stream AXI4-Stream AXI4-Stream

1 4 D-PHY

80 1500Mb/s

(RAW RGB YUV)

AXI IIC Camera Control Interface (CCI)

ID (VC)

AXI4-Stream Video IP (UG934) [ 2] 1 1 2 4

AXI4-Lite

D-PHY

IP

IP

(1)

UltraScale+Zynq UltraScale+ MPSoC

Zynq-7000 7

AXI4-Lite AXI4-Stream

Performance and Resource Utilization

( )

RTL

XDC

(2)

(3)

Vivado Design Suite

Vivado Design Suite :

Vivado

:1. Vivado IP

2. SDK (/SDK//data/embeddedsw/doc/xilinx_drivers.htm) Linux OS Xilinx Wiki

3. Vivado Design Suite :

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1

MIPI CSI-2 RX MIPI MIPI (D-PHY) 1-1

MIPI D-PHY

MIPI CSI-2 RX Controller

AXI Crossbar

Video Format Bridge

AXI IIC

X-Ref Target - Figure 1-1

11:

AXI Crossbar

AXI IIC

VideoFormatBridge

MIPI CSI-2 RXControllerMIPI D-PHY

Video Interface(AXI4-Stream)

Embedded Non-ImageInterface (AXI4-Stream)

csirxss_csi_irq

csirxss_iic_irq

Serial Interface

AXI4-Lite Interface

IIC Interface

PPI

dphy_clk_200M

lite_aclklite_aresetnvideo_aclk

video_aresetn



1:

MIPIDPHY

MIPI D-PHY IP D-PHY RX CSI-2 RX PHY MIPI D-PHY LogiCORE IP (PG202) [ 3] UltraScale+ 7 MIPI D-PHY I/O

UltraScale+ Vivado IDE [Pin Assignment] I/O 7 I/O (CCIO) 7 MIPI IOB MIPI IP HP I/O MIPI IOB D-PHY (XAPP894) [ 15]

MIPICSI2RXController

MIPI CSI-2 RX Controller MIPI CSI-2 RX 1.1 ( /)

MIPI CSI-2 RX Controller MIPI D-PHY PPI 1 8 ( 4 ) 1-1 PPI AXI4-Stream / PPI 32

1 4 ()

(DT)

ID (VC)

DT VC


12: MIPICSI2RXController

PHY Protocol Interface

(PPI)Lane

ManagementControl

FSM

PHECCProcessing

DataProcessing

CRCChecker

Buffer AXI4-Stream

RegisterInterface

AXI4-StreamPPI

AXI4-Lite

Interrupt

X16317-031116



1:

(ECC) 1 2

CRC

1.5Gb/s

AXI4-Lite

(D-PHY )

32/64 TDATA AXI4-Stream

/

1-1 ( 0x12) AXI4-Stream

EOL TLAST TUSER[1]

AXICrossbar

AXI4-Lite AXI Crossbar AXI Interconnect LogiCORE IP (PG059) [ 4]

VideoFormatBridge

Video Format Bridge VC AXI4-Stream AXI4-Stream 1 AXI4-Stream Video IP (UG934) [ 2]

Video Format Bridge CSI-2 RX Controller Vivado (IDE) RAW8 (0x30 0x37) Vivado IDE

11: AXI4StreamTDATA

(DT) AXI4StreamTDATA

RAW6 32

RAW7 32

RAW8 32

RAW10 64

RAW12 64

RAW14 64

RGB 64

YUV 422 8bit 64



1:

Vivado IDE RAW10 AXI4-Stream Video IP (UG934) [ 2]

(TKEEP)

video_out

video_out 1 RAW8 Vivado IDE 1 AXI4-Stream

1:VivadoIDERAW10 1 2

RAW10 1 = 10

RAW8 1 = 8

[Pixels Per Clock] 2 RAW10 20 RAW8 16 video_out 2 video_out 24

2:VivadoIDERAW7 1 4

RAW7 1 = 7

RAW8 1 = 8

[Pixels Per Clock] 4 RAW7 28 RAW8 32 video_out 2 video_out 32

LSB

1

RAW12 RAW8 1 2 video_out 24 RAW8 24 LSB

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RAW12 q11 q10 q9 q8 q7 q6 q5 q4 q3 q2 q1 q0 p11 p10 p9 p8 p7 p6 p5 p4 p3 p2 p1 p0

RAW8 q7 q6 q5 q4 q3 q2 q1 q0 p7 p6 p5 p4 p3 p2 p1 p0

:1. p0 p11 RAW12 1 q0 q11 RAW12 2 2. p0 p7 RAW8 1 q0 q7 RAW8 2



1:

2

Vivado IDE RAW6 1 2 video_out 16 RAW6 RAW8 16 LSB

AXI4-Stream TDATA Vivado IDE [Pixel Format] emb_nonimg_tdata

1 : emb_nonimg_tdata[7:0] 2 : emb_nonimg_tdata[15:8] ()

VideoFormatBridge

video_out Vivado IDE [CSI-2 Options] [TDATA Width] Video Format Bridge MIPI CSI-2 RX MIPI CSI-2 Recommended Memory Storage

MIPI Alliance Standard for Camera Serial Interface CSI-2 Specification [ 1]

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RAW8 q7 q6 q5 q4 q3 q2 q1 q0 p7 p6 p5 p4 p3 p2 p1 p0

RAW6 q5 q4 q3 q2 q1 q0 p5 p4 p3 p2 p1 p0

:1. p0 p7 RAW8 1 q0 q7 RAW8 2 2. p0 p5 RAW6 1 q0 q5 RAW6 2

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RAW8 s7 s6 s5 s4 s3 s2 s1 s0 r7 r6 r5 r4 r3 r2 r1 r0 q7 q6 q5 q4 q3 q2 q1 q0 p7 p6 p5 p4 p3 p2 p1 p0

:1. p0 p7 RAW8 1 q0 q7 RAW8 2

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RAW10 s9 s8 s7 s6 s5 s4 s3 s2 r9 r8 r7 r6 r5 r4 r3 r2 q9 q8 q7 q6 q5 q4 q3 q2 p9 p8 p7 p6 p5 p4 p3 p2

RAW10 v9 v8 v7 v6 v5 v4 v3 v2 u9 u8 u7 u6 u5 u4 u3 u2 t9 t8 t7 t6 t5 t4 t3 t2 s1 s0 r1 r0 q1 q0 p1 p0

RAW10 y9 y8 y7 y6 y5 y4 y3 y2 x9 x8 x7 x6 x5 x4 x3 x2 w1 w0 v1 v0 u1 u0 t1 t0 w9 w8 w7 w6 w5 w4 w3 w2

:1. RAW10 4 8 2



1:

AXIIIC

MIPI CSI-2 CCI (Camera Control Interface) I2C (400kHz 7 )

AXI IIC AXI IIC Bus Interface v2.0 LogiCORE IP (PG090) [ 5]

MIPI CSI-2 RX Controller () CSI (Camera Serial Interface) MIPI CSI MIPI MIPI MIPI VR () AR ()

Video Format Bridge YUV 420 (8 10 ) YUV 422 10 YUV

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RGB888 d7 d6 d5 d4 d3 d2 d1 d0 c7 c6 c5 c4 c3 c2 c1 c0 b7 b6 b5 b4 b3 b2 b1 b0 a7 a6 a5 a4 a3 a2 a1 a0

RGB888 h7 h6 h5 h4 h3 h2 h1 h0 g7 g6 g5 g4 g3 g2 g1 g0 f7 f6 f5 f4 f3 f2 f1 f0 e7 e6 e5 e4 e3 e2 e1 e0

:1. RGB888 a0 a7 B b0 b7 G c0 c7 R



1:

IP Vivado IP IP IP

Vivado

Vivado

write_bitstream (Tcl )

: IP IP

IP Vivado Design Suite

MIPI CSI-2 RX

LogiCORE IP IP LogiCORE IP

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2

MIPI Alliance Standard for Camera Serial Interface CSI-2 v1.1 [ 1]

MIPI Alliance Physical Layer Specifications, D-PHY Specification v1.1 [ 6]

: AXI4-Lite Vivado Design Suite AXI: (UG1037) [ 7]

: AXI4-Stream Video IP (UG934) [ 2]

Performance and Resource Utilization ( )

2-1 MIPI CSI-2 RX I/O

21:

lite_aclk AXI

lite_aresetn AXI Low

S00_AXI* AXI4-Lite Vivado Design Suite AXI: (UG1037) [ 7]

dphy_clk_200M D-PHY 200MHz

video_aclk

video_aresetn(1) Low

VideoFormatBridgeAXI4Stream

video_out_valid Valid

video_out_ready Ready ()

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2:

video_out_tuser

(SOF): ID (VC) VC emb_nonimg_tuser[0] 0

video_out_tlast

video_out_tdata[n-1:0]

n Vivado IDE ( video_out )

video_out_tdest[7:0] 1-0 ID (VC)

7-2

[EmbeddednonimageInterface]AXI4Stream

emb_nonimg_tdata[n-1:0]

n Vivado IDE ( 1-1 )

emb_nonimg_tdest[1:0] ID (VC)

emb_nonimg_tkeep[n/8-1:0]

emb_nonimg_tlast

emb_nonimg_tready Ready ()

emb_nonimg_tuser[95:0]

95-70

69-64

63-48

47-32

31-16

15-2

1

0 (SOF): ID (VC) VC emb_nonimg_tuser[0] 0

emb_nonimg_tvalid Valid

VideoFormatBridgeAXI4Stream

video_out_tdata[n-1:0]

n Vivado IDE TDATA

video_out_tdest[n-1:0]

n Vivado IDE TDEST

7-2

1-0 ID

video_out_tkeep[n/8-1:0]

video_out_tlast

video_out_tready Ready ()

21:()



2:

video_out_tuser[n-1:0]

n Vivado IDE TUSER

95-70

69-64

63-48

47-32

31-16

15-2

1

0

(SOF): ID (VC) VC emb_nonimg_tuser[0] 0

video_out_tvalid Valid

csirxss_csi_irq CSI-2 RX Controller ( High)

csirxss_iic_irq AXI IIC ( High)

7

clk_hs_rxp D-PHY RX clk_hs_rxn

data_hs_rxp[n:0] D-PHY RX

n data_hs_rxn[n:0]

clk_lp_rxp D-PHY RX clk_lp_rxn

data_lp_rxp[n:0] D-PHY RX

n data_lp_rxn[n:0]

rxbyteclkhs PPI

system_rst_out MMCM/PLL ( High)

dlyctrl_rdy_out VTC IDEALYCTRL Ready

clk_300m IDELAYCTRL 300MHz

UltraScale+

clk_rxp D-PHY RX

clk_rxn

data_rxp[n:0] D-PHY RX n data_rxn[n:0]

21:()



2:

MIPI CSI-2 RX


AXI IIC

MIPI D-PHY

rxbyteclkhs PPI

clkoutphy_out PHY

system_rst_out MMCM/PLL ( High)

pll_lock_out PLL ( High)

UltraScale+

clk_rxp D-PHY RX

clk_rxn

data_rxp[n:0] D-PHY RX n data_rxn[n:0]

bg_pin_nc

bitslice0 (0 1 2 3) bitslice0 ( 0 6)

clkoutphy_in PHY

pll_lock_in PLL

system_rst_in MMCM/PLL ( High)

rxbyteclkhs PPI

:1. MIPI D-PHY High Low (video_aresetn) 0

21:()



2:

IP 64K 2-2 AXI IIC MIPI D-PHY

MIPICSI2RXController 2-3 MIPI CSI-2 RX Controller

22:

IP

MIPI CSI-2 RX Controller 0x0_0000

AXI IIC 0x1_0000

MIPI D-PHY 0x2_0000(1)

:1. AXI IIC MIPI D-PHY 0x1_0000

23: MIPICSI2RXController

0x00

0x04

0x08 (1)

0x0C

0x10

0x14

0x18

0x1C

0x20

0x24

0x28

0x2C

0x30

0x34

0x38

0x3C

0x40 Lane0 0

0x44 Lane1 1

0x48 Lane2 2

0x4C Lane3 3

0x50

0x54

0x58



2:

( 2-4) MIPI CSI-2 RX Controller /

0x5C

0x60 VC0 1 VC = 0 1

0x64 VC0 2 VC = 0 2

0x68 VC1 1 VC = 1 1

0x6C VC1 2 VC = 1 2

0x70 VC2 1 VC = 2 1

0x74 VC2 2 VC = 2 2

0x78 VC3 1 VC = 3 1

0x7C VC3 2 VC = 3 2

:1. 0 2. WSTRB

3. AXI4-Lite 7 (6:0) 0x00 0x80 0x00

4. /

24:

31-2 N/A N/A

1 Soft Reset 0x0 R/W

1: 0: ( Core Enable Active Lanes ) 1

PPI

FIFO (PPI )

FSM ( ) AXI4-Stream TUSER[1]

23: MIPICSI2RXController ()



2:

( 2-5)

0 Core Enable 0x1 R/W

1: 0:

PPI FIFO (PPI

) FSM

AXI4-Stream TUSER[1]

:1. FIFO CDC (

)

25:

31-5 N/A N/A

4-3 Maximum Lanes(1) R

0x0 1 0x1 2 0x2 3 0x3 4

2 N/A

1-0 Active Lanes R(2)/W

(3)

0x0 1 0x1 2 0x2 3 0x3 4

:1. Maximum Lanes [Serial Data Lanes] 2.

3

3. Active Lanes [4:3] Maximum Lanes

24: ()



2:

2-6

2-7

26:

31-16 Packet Count 0x0 R

15-4 N/A N/A N/A

3 Short packet FIFO Full 0x0 R FIFO

2 Short packet FIFO not empty 0x0 RFIFO FIFO

1 Stream Line buffer Full 0x0 R

0 Soft reset/Core disablein progress 0x0 R / 1

27:

31-1 N/A N/A

0 Global Interrupt enable 0x0 R/W

1: (IER)

0: IER



2:

(ISR) ( 2-8)

28:

(1)

31 Frame Received 0x0 R/W1C Frame End (FE)

30-22 N/A N/A N/A

21 Incorrect lane configuration 0x0 R/W1C Active Lanes Maximum Lanes

20 Short packet FIFO full 0x0 R/W1C FIFO High

19 Short packet FIFO not empty 0x0 R/W1C FIFO High

18 Stream line buffer full 0x0 R/W1C (2)

17 Stop state 0x0 R/W1C High (3)

16 N/A N/A N/A

15 N/A N/A N/A

14 N/A N/A N/A

13 SoT error(ErrSoTHS) 0x0 R/W1C SoT () (3)

12 SoT sync error(ErrSotSyncHS) 0x0 R/W1C SoT (3)

11 ECC 2-bit error(ErrEccDouble) 0x0 R/W1CECC 2

10ECC 1-bit error()(ErrEccCorrected)

0x0 R/W1CECC 1

9 CRC error(ErrCrc) 0x0 R/W1C CRC CRC

8 Unsupported Data Type(ErrID) 0x0 R/W1C ID /

7Frame synchronizationerror for VC3(ErrFrameSync)

0x0 R/W1C FE FS (Frame Start) (4)

6 Frame level error for VC3(ErrFrameData) 0x0 R/W1CFS FE FE CRC


0x0 R/W1C FE FS (4)



2:

VC

ErrEccDouble VC VC

ErrSotSyncHS VC VC

(IER) (ISR) / ( 2-9) IER 0 / ISR



0x0 R/W1C FE FS (4)



0x0 R/W1C FE FS (4)


:1. W1C = Write 1 to Clear (1 ) 2. video_aresetn 3. PPI 4. ErrSotSyncHS 5. FIFO CDC (

) 6. PPI PPI CDC ISR

7. ErrSotSyncHS ECC VC 8. ISR 9. MIPI Alliance Standard for Camera Serial Interface CSI-2 [ 1]

28: ()

(1)



2:

2-10 31 FIFO FIFO

video_aresetn

29:

31 Frame Received 0x0 R/W

1 0 /ISR ( 2-8)

30-22 N/A N/A

21 Incorrect lane configuration 0x0 R/W

20 Short packet FIFO full 0x0 R/W

19 Short packet FIFO empty 0x0 R/W

18 Stream line buffer full 0x0 R/W

17 Stop state 0x0 R/W

16 N/A N/A

15 N/A N/A

14 N/A N/A

13 SoT error 0x0 R/W

12 SoT sync error 0x0 R/W

11 ECC 2-bit error 0x0 R/W

10 ECC 1-bit error () 0x0 R/W

9 CRC error 0x0 R/W

8 Unsupported Data Type 0x0 R/W

7 Frame synchronization error for VC3 0x0 R/W

6 Frame level error for VC3 0x0 R/W







210:

31-24 N/A N/A

23-8 Data 0x0 R 16

7-6 Virtual Channel 0x0 R

5-0 Data Type 0x0 R



2:

2-11

(n = 0 1 2 3) ( 2-12)

1 (VC0VC3)

1 VC ( 2-13) ( 0x18 ) FSM

211:

31-2 N/A N/A

1 Stop state 0x0 R

0 N/A N/A

212: 0/1/2/3

(2)

31-6 N/A N/A

5 Stop state 0x0 R High

4 N/A N/A

3 N/A N/A

2 N/A N/A

1 SoT error 0x0 R SoT (ErrSotHS) SoT

0 SoT sync error 0x0 R SoT (ErrSotSyncHS) SoT

:1. 0x0

2. PPI

213: 1

31-16 Line count 0x0 R

15-0 Byte count 0x0 R FSM



2:

2 (VC0VC3)

2 ( 2-14) ( 0x18 ) FSM

AXIIICVivado IDE [Enable AXI IIC (CCI)] AXI IIC AXI IIC AXI IIC Bus Interface v2.0 LogiCORE IP (PG090) [ 5]

MIPIDPHYVivado IDE [D-PHY Register Interface] MIPI D-PHY MIPI D-PHY MIPI D-PHY LogiCORE IP (PG202) [ 3]

214: 2

31-6 N/A N/A

5-0 0x0 R FSM


MIPICSI2RXSubsystemv2.1 24PG23220161130 japan.xilinx.com

3

MIPI AXI4-Stream

MIPI

[1:0]

1. Active Lanes (Vivado IDE [Enable Active Lanes] )

2. PPI RxByteClkHS

3.

4.



3:

1 HDL

CSI-2 RX I/O CSI-2 RX MMCM PLL

_support 3-1 3-2 2 2 MIPI CSI-2 RX Vivado IDE [Shared Logic] MMCM PLL 4 BUFG


31:


32:

_exdes

_core

_core



3:

[Include Shared Logic in core] MMCM PLL PHY MMCM PLL

[Include Shared Logic in core]

MMCM PLL

MIPI CSI-2 RX

MMCM PLL

[Include Shared logic in example design]

2 MIPI CSI-2 RX

MIPI CSI-2 RX 1

MMCM PLL 1 MIPI CSI-2 RX 1 1 MIPI CSI-2 RX MMCM/PLL 2

[Include Shared Logic in example design]

3-3 MIPI CSI-2 RX (MIPI_CSI_SS_Master) MIPI CSI-2 RX (MIPI_CSI_SS_Slave00 MIPI_CSI_SS_Slave01) (UltraScale+ )



3:

: MMCM/PLL


33:



3:

3-1 IP

CSI-2 RX Controller 32 PPI 4

1 1000Mb/s 1 MIPI 125MHz 32 (4 ) 125MHz/4

1 800Mb/s 2 MIPI 100MHz*2 32 (4 ) (125MHz*2)/4

1 700Mb/s 3 MIPI 87.5MHz*3 32 (4 ) (87.5MHz*3)/4

1 1200Mb/s 4 MIPI 150MHz*4 32 (4 ) (150MHz*4)/4

video_aclk (MHz) = (Mbps) * / 8 / 4

31:

lite_aclk(1) IP AXI4-Lite

video_aclk(2) IP

dphy_clk_200M MIPI D-PHY LogiCORE IP (PG202) [ 3]

:1. lite_aclk video_aclk 2. UltraScale+ 250MHz 7 175MHz [Pixels Per

Clock] 1 2 4



3:

2

lite_aresetn: AXI4-Lite ( Low) video_aresetn: ( Low)

video_aresetn 40 dphy_clk_200M ( 3-4 )

3-2 MIPI CSI-2 RX

: (lite_resetn video_aresetn)


34: MIPICSI2RX

32:

lite_aresetn video_aresetn

MIPI CSI-2 RX Controller s_axi_aresetn m_axis_aresetn

MIPI D-PHY s_axi_aresetn core_rst

Video Format Bridge N/A s_axis_aresetn

AXI IIC s_axi_aresetn N/A

AXI Crossbar aresetn N/A



3:

1. AXI IIC ()

2. MIPI CSI-2 RX Controller

3. MIPI D-PHY ( )

3-3 0x44A0_0000 (32 ) AXI IIC MIPI D-PHY

AXIIICIP AXI IIC IP AXI IIC Bus Interface v2.0 LogiCORE IP (PG090) [ 5]

MIPICSI2RXController MIPI CSI-2 RX Controller 3-5

1. (video_aresetn) Core Enable 1 PPI Active Lanes Maximum Lanes (Vivado IDE [Serial Data Lanes] )

2.

Core Enable 0 Soft Reset 1

Soft reset/Core disable in progress

( )

(Core Enable 1 Soft Reset 0 )

33:

MIPI CSI-2 RX Controller 0x44A0_0000

AXI IIC 0x44A1_0000

MIPI D-PHY 0x44A2_0000(1)

:1. AXI IIC IP MIPI D-PHY MIPI D-PHY

0x44A1_0000



3:

[1:0]

1. Active Lanes (Vivado IDE [Enable Active Lanes] )

2. PPI RxByteClkHS

3.

4.

: RxByteClkHS Active Lanes MIPI D-PHY Rx Active Lanes MIPI D-PHY Rx Active Lanes MIPI D-PHY Rx Active Lanes

MIPIDPHYIP

MIPI D-PHY IP MIPI D-PHY LogiCORE IP (PG202) [ 3]


35:



4

// Vivado IP Vivado Design Suite

Vivado Design Suite : IP IP (UG994) [ 8]

Vivado Design Suite : IP (UG896) [ 9]

Vivado Design Suite : (UG910) [ 10]


Vivado Design Suite

Vivado IP Vivado Design Suite : IP IP (UG994) [ 8] IP Tcl validate_bd_design

IP

1. Vivado IP IP

2. IP [Customize IP]

Vivado Design Suite : IP (UG896) [ 9] Vivado Design Suite : (UG910) [ 10]

: Vivado (IDE)



4:

4-1 7

[Component Name]: 1 2 a z 0 9 (_) mipi_csi2_rx_subsystem_0

[Configuration][Configuration]

[Pixel Format]: CSI-2 ( ) [RAW6] [RAW7] [RAW8][RAW10] [RAW12] [RAW14] [RGB888] [RGB666] [RGB565] [RGB555] [RGB444] [YUV422_8bit]

[Serial Data Lanes]: D-PHY 1 2 3 4

[Enable AXI IIC (CCI)]: AXI IIC CCI

[Include Video Format Bridge (VFB)]: Video Format Bridge

[Line Rate (Mbps)]: MIPI D-PHY 80 1500Mbps Vivado IDE


41:[Configuration]



4:

[D-PHY Register Interface]: MIPI D-PHY

[Calibration Mode]: 7 MIPI D-PHY RX [NONE][FIXED] [AUTO] [NONE] IDELAY2 [FIXED] [IDELAY Tap Value] IDELAYE2 [AUTO] IDELAYE2 D-PHY RX IP

[IDELAY Tap Value]: [Calibration Mode] [FIXED] IDELAY 1 31

[Include IDELAYCTRL in core]: IDELAYCTRL [FIXED] [AUTO]

[Enable 300 MHz clock for IDELAYCTRL]: 300MHz [Calibration Mode] [AUTO]

[Embedded non-image Interface]: CSI-2 ( 0x12) AXI4-Stream CSI-2 RX Controller

[Line Buffer Depth]: RAM 128 256 512 1024 2048 4096 8192 16384

: PPI

[Pixels Per Clock]: 1 1 ( ) 2 ( ) 4 ( )

[Allowed VC]: VC All 0 1 2 3

[Enable CRC]: CRC

[Enable Active Lanes]: [Serial Data Lanes] [Serial Data Lanes] 3 Active Lanes 1 2 3 [Serial Data Lanes] Active Lanes 21



4:

[SharedLogic][Shared Logic] 4-2

[Shared Logic]: MMCM PLL

[Include Shared Logic in core]

[Include Shared Logic in example design]


42:[SharedLogic]



4:

[PinAssignment][Pin Assignment] 4-3

: 7

[HP IO Bank Selection]: HP I/O

[Clock Lane]: LOC HP I/O I/O

[Data Lane 0/1/2/3]: [Clock Lane] 0 1 2 3 LOC


43:[PinAssignment]



4:

4-1 Vivado IDE Tcl


41: VivadoIDE

VivadoIDE

[Pixel Format] CMN_PXL_FORMAT RAW8

[Serial Data Lanes] CMN_NUM_LANES 1

[Allowed VC] CMN_VC All

[Pixels Per Clock] CMN_NUM_PIXELS 1

[Enable AXI IIC (CCI)] CMN_INC_IIC True

[Include Video Format Bridge (VFB)] CMN_INC_VFB True

[Line Rate (Mbps)] DPY_LINE_RATE 1000

[D-PHY Register Interface] DPY_EN_REG_IF False

[Calibration Mode] C_CAL_MODE None

[IDELAY Tap Value] C_IDLY_TAP 1

[Include IDELAYCTRL in core] C_SHARE_IDLYCTRL False

[Enable 300 MHz clock for IDELAYCTRL] C_EN_CLK300M False

[Embedded non-image Interface] CSI_EMB_NON_IMG False

[Line Buffer Depth] CSI_BUF_DEPTH 2048

[Enable CRC] C_CSI_EN_CRC True

[Enable Active Lanes] C_CSI_EN_ACTIVELANES False

[Shared Logic] SupportLevel 0

[HP IO Bank Selection] HP_IO_BANK_SELECTION

[Clock Lane] CLK_LANE_IO_LOC

[Data Lane0] DATA_LANE0_IO_LOC






4:

Vivado Design Suite

XDC

MIPI CSI-2 RX (OOC) _fixed_ooc.xdc

MIPI CSI-2 RX MIPI D-PHY Vivado IDE [Pin Assignment] HP I/O I/O BITSLICE

: [Pin Assignment] 7

I/OUltraScale+ MIPI I/O XDC I/O MIPI_DPHY_DCI XDC LOC I/O MIPI CSI-2 RX MIPI D-PHY IP I/O LOC 7 I/O LOC

7 RX I/O I/O I/O

UltraScale+ MIPI CSI-2 RX VRP I/O VRP I/O I/O DCI_CASCADE XDC I/O 65 VPR D-PHY TX IP I/O 66

set_property DCI_CASCADE {66} [get_iobanks 65]



4:

Vivado Vivado Design Suite : (UG900) [ 11]




A

MIPI CSI-2 RX

/ HS (High Speed)

( )

/

MIPI CSI-2 RX MIPI CSI-2 RX

MIPI CSI-2 RX A-1 / MIPI CSI-2 RX

7 MIPI IOB MIPI IP HP I/O MIPI IOB D-PHY (XAPP894) [ 15]

A1:

Zynq UltraScale+ MPSoC ZCU102 N/A



B

: IP 1

MIPI CSI-2 Receiver

MIPI CSI-2 Receiver (http://japan.xilinx.com/support) Xilinx Documentation Navigator

Xilinx Documentation Navigator

MIPICSI2Receiver

AR: 65242

https://japan.xilinx.comhttps://japan.xilinx.com/supporthttps://japan.xilinx.com/supporthttps://japan.xilinx.com/supporthttps://japan.xilinx.com/support/download.htmlhttps://japan.xilinx.com/supporthttps://japan.xilinx.com/support/answers/65242.htmlhttp://japan.xilinx.com/about/feedback.html?docType=Product_Guide&docId=PG232&Title=MIPI%20CSI-2%20Receiver%20%26%2312469%3B%26%2312502%3B%26%2312471%3B%26%2312473%3B%26%2312486%3B%26%2312512%3B%20v2.1%20%26%2335069%3B%26%2321697%3B%26%2312460%3B%26%2312452%3B%26%2312489%3B&releaseVersion=2.1&docPage=41


B:

LogiCORE IP

DO NOT MODIFY

MIPI CSI-2 Receiver

VivadoDesignSuiteVivado Design Suite Logic Analyzer Virtual I/O Vivado IDE

Vivado IP

ILA 2.0 ( )

VIO 2.0 ( )


https://japan.xilinx.comhttps://japan.xilinx.com/supporthttps://japan.xilinx.com/supporthttps://japan.xilinx.com/supporthttp://japan.xilinx.com/about/feedback.html?docType=Product_Guide&docId=PG232&Title=MIPI%20CSI-2%20Receiver%20%26%2312469%3B%26%2312502%3B%26%2312471%3B%26%2312473%3B%26%2312486%3B%26%2312512%3B%20v2.1%20%26%2335069%3B%26%2321697%3B%26%2312460%3B%26%2312452%3B%26%2312489%3B&releaseVersion=2.1&docPage=42


B:

Vivado Vivado

MIPI DPHY MIPI CSI-2 RX Controller

MIPI CSI-2 RX Controller Incorrect Lane Configuration

MIPI CSI-2 RX Controller Stream line buffer full ([DPHY Options] [Line Rate (Mbps)]) ([Pixels Per Clock]) 2 () 4 ( )

AXI IIC AXI IIC PULLUP XDC ( AXI IIC Bus Interface v2.0 LogiCORE IP (PG090) [ 5] )


Packet Count

Data Type Byte count

Frame Received

AXI4Lite 0 B-1 s_axi_arready / s_axi_rvalid

lite_aclk (lite_aresetn Low

)

AXI4-Lite



B:

AXI4Stream

_tvalid _tready Low

_tvalid Low video_aclk dphy_clk_200M

Stream line buffer full

X-Ref Target - Figure B-1

B1: AXI4Lite



C

:

1. MIPI Alliance Standard for Camera Serial Interface CSI-2 : mipi.org/specifications/camera-interface#CSI2

2. AXI4-Stream Video IP (UG934)

3. MIPI D-PHY LogiCORE IP (PG202: )

4. AXI Interconnect LogiCORE IP (PG059)

5. AXI IIC Bus Interface v2.0 LogiCORE IP (PG090)

6. MIPI Alliance Physical Layer Specifications, D-PHY Specification: http://mipi.org/specifications/physical-layer#D-PHY Specification

7. Vivado Design Suite: AXI (UG1037: )

8. Vivado Design Suite : IP IP (UG994: )

9. Vivado Design Suite : IP (UG896: )

10. Vivado Design Suite : (UG910: )


12. ISE Vivado Design Suite (UG911: )



15. D-PHY (XAPP894: )

https://japan.xilinx.comhttps://japan.xilinx.com/supporthttp://mipi.org/specifications/camera-interface#CSI2https://japan.xilinx.com/cgi-bin/docs/ipdoc?c=axi_videoip;v=latest;d=ug934_axi_videoIP.pdfhttps://japan.xilinx.com/cgi-bin/docs/ipdoc?c=mipi_dphy;v=latest;d=pg202-mipi-dphy.pdfhttps://japan.xilinx.com/cgi-bin/docs/ipdoc?c=axi_interconnect;v=latest;d=pg059-axi-interconnect.pdfhttps://japan.xilinx.com/cgi-bin/docs/ipdoc?c=axi_iic;v=latest;d=pg090-axi-iic.pdfhttp://mipi.org/specifications/physical-layer#D-PHY Specificationhttp://mipi.org/specifications/physical-layer#D-PHY Specificationhttps://japan.xilinx.com/cgi-bin/docs/ipdoc?c=axi_ref_guide;v=latest;d=ug1037-vivado-axi-reference-guide.pdfhttps://japan.xilinx.com/cgi-bin/docs/ipdoc?c=axi_ref_guide;v=latest;d=j_ug1037-vivado-axi-reference-guide.pdfhttps://www.xilinx.com/cgi-bin/docs/rdoc?v=latest;d=ug994-vivado-ip-subsystems.pdfhttps://japan.xilinx.com/cgi-bin/docs/rdoc?v=latest;d=ug994-vivado-ip-subsystems.pdfhttps://www.xilinx.com/cgi-bin/docs/rdoc?v=latest;d=ug896-vivado-ip.pdfhttps://japan.xilinx.com/cgi-bin/docs/rdoc?v=latest;d=ug896-vivado-ip.pdfhttps://www.xilinx.com/cgi-bin/docs/rdoc?v=latest;d=ug910-vivado-getting-started.pdfhttps://japan.xilinx.com/cgi-bin/docs/rdoc?v=latest;d=ug910-vivado-getting-started.pdfhttps://www.xilinx.com/cgi-bin/docs/rdoc?v=latest;d=ug900-vivado-logic-simulation.pdfhttps://japan.xilinx.com/cgi-bin/docs/rdoc?v=latest;d=ug900-vivado-logic-simulation.pdfhttps://www.xilinx.com/cgi-bin/docs/rdoc?v=latest;d=ug911-vivado-migration.pdfhttps://japan.xilinx.com/cgi-bin/docs/rdoc?v=latest;d=ug911-vivado-migration.pdfhttps://www.xilinx.com/cgi-bin/docs/rdoc?v=latest;d=ug908-vivado-programming-debugging.pdfhttps://japan.xilinx.com/cgi-bin/docs/rdoc?v=latest;d=ug908-vivado-programming-debugging.pdfhttps://www.xilinx.com/cgi-bin/docs/rdoc?v=latest;d=ug904-vivado-implementation.pdfhttps://japan.xilinx.com/cgi-bin/docs/rdoc?v=latest;d=ug904-vivado-implementation.pdfhttps://japan.xilinx.com/cgi-bin/docs/ndoc?t=application_notes;d=xapp894-d-phy-solutions.pdfhttps://japan.xilinx.com/cgi-bin/docs/ndoc?t=application_notes;d=j_xapp894-d-phy-solutions.pdfhttps://japan.xilinx.com/cgi-bin/docs/ipdoc?c=mipi_dphy;v=latest;d=j_pg202-mipi-dphy.pdfhttp://japan.xilinx.com/about/feedback.html?docType=Product_Guide&docId=PG232&Title=MIPI%20CSI-2%20Receiver%20%26%2312469%3B%26%2312502%3B%26%2312471%3B%26%2312473%3B%26%2312486%3B%26%2312512%3B%20v2.1%20%26%2335069%3B%26%2321697%3B%26%2312460%3B%26%2312452%3B%26%2312489%3B&releaseVersion=2.1&docPage=45


C:

: ( ) ( ) (1) (with all faults) ( ) ( ) (2) () ( () ) ( )

https://japan.xilinx.com/legal.htm#tos IP

https://japan.xilinx.com/legal.htm#tos

( XA ) ISO 26262 ( ) ( )

Copyright 2015-2016 Xilinx, Inc. Xilinx Xilinx Artix ISE Kintex Spartan Virtex Vivado Zynq

[email protected] [ ]

2016 11 30 2.1 [FIXED] [AUTO]

2016 10 5 2.1 MIPI D-PHY 3.0 7

2016 4 6 2.0 MIPI D-PHY 2.0 Vivado IDE RAW8

Video Format Bridge

2015 11 18 1.0

https://japan.xilinx.comhttps://japan.xilinx.com/legal.htm#toshttps://japan.xilinx.com/legal.htm#tosmailto:[email protected]://japan.xilinx.com/about/feedback.html?docType=Product_Guide&docId=PG232&Title=MIPI%20CSI-2%20Receiver%20%26%2312469%3B%26%2312502%3B%26%2312471%3B%26%2312473%3B%26%2312486%3B%26%2312512%3B%20v2.1%20%26%2335069%3B%26%2321697%3B%26%2312460%3B%26%2312452%3B%26%2312489%3B&releaseVersion=2.1&docPage=46

MIPI CSI-2 Receiver v2.1 IP 1: MIPI D-PHYMIPI CSI-2 RX ControllerAXI CrossbarVideo Format Bridgevideo_out Video Format Bridge

AXI IIC

2: MIPI CSI-2 RX Controller VC 1 (VC0 VC3) 2 (VC0 VC3)

AXI IIC MIPI D-PHY

3:

AXI IIC IP MIPI CSI-2 RX Controller MIPI D-PHY IP

4: [Configuration] [Shared Logic] [Pin Assignment]

I/O

A:

B:

Vivado Design Suite

AXI4-Lite AXI4-Stream

C: :

/ColorImageDict > /JPEG2000ColorACSImageDict > /JPEG2000ColorImageDict > /AntiAliasGrayImages false /CropGrayImages true /GrayImageMinResolution 150 /GrayImageMinResolutionPolicy /OK /DownsampleGrayImages true /GrayImageDownsampleType /Bicubic /GrayImageResolution 300 /GrayImageDepth -1 /GrayImageMinDownsampleDepth 2 /GrayImageDownsampleThreshold 1.50000 /EncodeGrayImages true /GrayImageFilter /DCTEncode /AutoFilterGrayImages true /GrayImageAutoFilterStrategy /JPEG /GrayACSImageDict > /GrayImageDict > /JPEG2000GrayACSImageDict > /JPEG2000GrayImageDict > /AntiAliasMonoImages false /CropMonoImages true /MonoImageMinResolution 1200 /MonoImageMinResolutionPolicy /OK /DownsampleMonoImages true /MonoImageDownsampleType /Bicubic /MonoImageResolution 1200 /MonoImageDepth -1 /MonoImageDownsampleThreshold 1.50000 /EncodeMonoImages true /MonoImageFilter /CCITTFaxEncode /MonoImageDict > /AllowPSXObjects false /CheckCompliance [ /None ] /PDFX1aCheck false /PDFX3Check false /PDFXCompliantPDFOnly false /PDFXNoTrimBoxError true /PDFXTrimBoxToMediaBoxOffset [ 0.00000 0.00000 0.00000 0.00000 ] /PDFXSetBleedBoxToMediaBox true /PDFXBleedBoxToTrimBoxOffset [ 0.00000 0.00000 0.00000 0.00000 ] /PDFXOutputIntentProfile () /PDFXOutputConditionIdentifier () /PDFXOutputCondition () /PDFXRegistryName () /PDFXTrapped /False

/CreateJDFFile false /Description >>> setdistillerparams> setpagedevice

Documents

MIPI CSI-2 Receiver - ザイリンクス - All Programmable CSI‐2 RX サブシステム v2.1 6 PG232 2016 年 11 月 30 日 japan.xilinx.com 第 1 章: 概要 • マルチレーンの相互運用性