Software and Hardware Realization of MISO W-CDMA High Speed
Downlink Transceiver
Student: Wei-Chi Lee
Advisor: Dr. Ta-Sung Lee
MISO W-CDMA
High Speed Downlink Transceiver
National Chiao Tung University in Partial Fulfillment of the
Requirements
for the Degree of Master of Science
in Communication Engineering
MISO W-CDMA
DSPMISO W-CDMA
FPGA
DSP
i
Software and Hardware Realization of MISO W-CDMA High Speed
Downlink Transceiver
Student: Wei-Chi Lee Advisor: Dr. Ta-Sung Lee
Institute of Communication Engineering
National Chiao Tung University
Abstract
With the growing of wireless communication technologies in recent
years, the
spectral spectrum has become an increasingly precious source.
Therefore, a major
issue of wireless communication technologies in the 3G (3rd
Generation) and B3G
(Beyond 3rd Generation) systems is to enhance the quality and
capacity of
communication systems. In particular, spectral efficiency must be
effectively
increased, while radio access technique can be improved via digital
signal
processing. In the 3G and B3G systems, the smart antenna technique
is one of the
most representative research topics. Without increasing the
bandwidth, a smart
antenna boosts transmission capacity through suppressing
interferences. On the
other hand, it also provides spatial diversity to mitigate channel
fading problems
and enhance signal quality and reliability. In this thesis, we
adopt the Aptix® MP3C
as our development platform, and realize software and hardware
architectures of an
MISO W-CDMA high speed downlink transceiver via of programmable
FPGAs
and DSPs on the platform. FPGA is a programmable logic device which
can be
ii
used to design digital logic circuits by hardware description
language and can
provide fast hardware verification based on its reconfigurability.
On the other hand,
DSP is a powerful processor with high speed floating-point or
fixed-point
operations, which is suitable for real-time signal processing. The
developed system
includes a time synchronizer, a spread/ despread circuit, a
space-time block
encoder/ decoder circuit, an auto frequency controller, and a
convolution encoder/
decoder circuit, giving a complete baseband circuit. Combining the
baseband
circuit with real measured channel data, we could increase the
accuracy and
reliability of the system. Finally, we introduce the concept of
software-defined
radio, with which the scalability and adaptivity of the system
could be improved by
parameter control of DSP programs and modulizing hardware circuits
of the
FPGA.
iii
Arithmetic Logic Unit (ALU):
Auto Frequency Control (AFC):
Code Division Multiple Access (CDMA):
Data Memory Controller (DMEMC):
Dedicated Physical Channel (DPCH):
Dedicated Physical Control Channel (DPCCH):
Dedicated Physical Data Channel (DPDCH):
Direct Memory Access Controller (DMA):
Doppler effect:
Feedback Information (FBI):
Finite Impulse Response (FIR):
Finite State Machine (FSM):
First In First Out (FIFO):
Hardware Description Language (HDL):
xiii
Logic Analyzer (LA):
Multichannel Buffered Serial Port (McBSP):
Multiplexer Type (MPX):
Processing Element (PE):
Radio Frequency (RF):
Random-Access Memory (RAM):
Read-Only Memory (ROM):
Root-Raised Cosine (RRC):
Soft-Defined Radio (SDR):
Spreading Factor (SF):
Synchronous DRAM (SDRAM):
antenna array:
auxiliary channel:
average power:
early-late code tracking loop:
encoding:
Access) GSM (Global System for Mobile
communications)(3G)
(smart antenna)
1
3GPP [2] FPGA DSP MISO
W-CDMA
VHDL (Very High Speed
integrated circuit hardware Description language) [3]-[5]
FPGA
(Field Programmable Gate Array) Aptix
DSP (Digital Signal Processor)
32
‘C6701 DSP EVM FPGA ( 3.12)
FPGA DSP FPGA
EXTINT0/1/2/3 DSP INT4-INT7 DSP
(board 1 ~ board 4) EMIF CE3
DSP FPGA
DSP
3.13 STRBN0/1/2/3 RD/WR0/1/2/3
FPGA
DSP
STRBN0/1/2/3 RD/WR0/1/2/3
DSP
FPGA
‘C6701 DSP
1. tclkDSP clock DSP 132 MHz tclk=1/132
MHz
3. t2STRBN0/1/2/3
3.5 USB 2.0
USB 2.0 CYPRESS CY7C68013 ( 3.15 3.16)
24 MHz 8051 4 Kbytes FIFO
480 Mb/s FIFO USB 2.0 C6701 EVM
3.17 USB 2.0 USB 2.0 Aptix MP3C ‘C6701
EVM PC USB FIFO DSPUSB 2.0
DSP PC USB FPGA DSP
(buffer) USB 2.0
USB
(image)(voice)
4. (Interrupt)(poll)(mouse)
USB 2.0 C6701 EVM 3.12 Board 1 USB
2.0 I/O USB2.0
34
16 C6701 EVM 32
C6701 EVM (Least Significant Bit, LSB)
16 USB2.0
PC USB 2.0 USB
NEC PCI
EZ USB Control Panel ( 3.18) EZ USB Control Panel
PC USB2.0 PC USB 2.0
endpoint 2 (pipe) PC USB 2.0
endpoint 6 Bulk
3.6 FPGA DSP
CPU
F ree ho le
FP IC
38
39
40
41
64K x 8 Internal Prog. RAM
On-chip Peripherals
64K x 8 Internal Data RAM
Byte Address 0000_0000
0180_0000
0140_0000
0100_0000
0200_0000
0300_0000
8000_0000
Range 0, 2, 3 Async (SRAM, ROM, etc) Sync (SBSRAM, SDRAM)
Range 1 Only Async SBSRAM Used by Boot Loader
Internal Block Prog = RAM or cache
Data = 8/16/32-bit R/W Mem-mapped Periph
= reserved
64K x 8 Internal Prog. RAM
On-chip Peripherals
64K x 8 Internal Data RAM
Byte Address 0000_0000
0180_0000
0140_0000
0100_0000
0200_0000
0300_0000
8000_0000
Range 0, 2, 3 Async (SRAM, ROM, etc) Sync (SBSRAM, SDRAM)
Range 1 Only Async SBSRAM Used by Boot Loader
Internal Block Prog = RAM or cache
Data = 8/16/32-bit R/W Mem-mapped Periph
= reserved
42
43
3.10 DSP EVM
44
Board 1
Board 2
Board 3
Board 4
OE0 OE1
STRBN0 RDY0 RD/WR0 EXTINT0 STRBN1 RDY1 RD/WR1 EXTINT1 STRBN2 RDY2
RD/WR2 EXTINT2 STRBN3 RDY3 RD/WR3 EXTINT3
C6701EVM
45
t1
HOLD =1
Not ready
t3 t4
t2 STRBN0/1/2/3
Data[31:0]
HOLD =1
Not ready
46
47
48
TTL
VOL VOH VIL VIH 0.4 Volt 2.4 Volt 0.8 Volt 2.0 Volt 5 Volt
3.2 TMS320C6701 DSP
SBSRAM SDRAM ASRAM
Description Address Range(Hex)
0000 0000–0003 FFFF Internal program RAM
64K Bytes 0040 0000–0003 FFFF
External memory SRAM CE0 256K Bytes
0100 0000–0101 FFFF External memory FLASH
CE1 128K Bytes
0140 0000–0141 FFFF Internal program RAM
64K Bytes External memory FLASH
CE1 128K Bytes 0180 0000-01FF FFFF DSP internal control register
0210 0000-0210 001C 32 UART (Only use low byte for each word) 0300
0000-0300 003F 32 All board disable 0300 0040-0300 007F 64 Board 1
active area. 0300 0080-0300 00BF 64 Board 2 active area. 0300
00C0-0300 0FFF Not use 0300 0100-0300 013F 64 Board 3 active area
0300 0140-0300 01FF Not use 0300 0200-0300 023F 64 Board 4 active
area
50
3.4 USB 2.0 16 16 0 ISO 10 OUT
16 16 0 ISO 10 IN
16 16 0 ISO 9 OUT
16 16 0 ISO 9 IN
256 16 0 ISO 8 OUT
256 16 0 ISO 8 IN
64 64 0 BULK 6 OUT
64 64 0 BULK 6 IN
64 64 0 BULK 4 OUT
64 64 0 BULK 4 IN
64 64 0 BULK 2 OUT
64 64 0 BULK 2 IN
64 16 0 INT 1 IN
64 64 64 CTL 0
Max Packet Size (bytes)
Endpoint
51
3.5 ALU 2 4 bitsAB 1 4 bits S2S1S0
Operation Inputs
Outputs F
Clear 000 0000 B−A 001 B−A A−B 010 A−B ADD 011 A ADD B XOR 100 A
XOR B OR 101 A OR B
AND 110 A AND B Preset 111 1111
52
FPGA DSP FPGA
Xilinx VIRTEXE-2000 VIRTEX-6000
DSP ’C6701 EVM 15.36MHz
DSP FPGA
1/2 1/3
DSP FPGA
(pipeline) IP
53
DPDCH DPCCH
SCH 64 PN
Kbps FPGA
IQ
DPDCH 0 1
2 2×
DPDCHC
DPDCH
DSP DSP
MISO W-CDMA 4.2
DSP
4.3
64 SCH SCH PN
SCH
4.6 SCH
t t
t 64
K
K 4.1
SCH( )K = − ∗
20
DSP
1,1 1,2 1,41
3,1 3,2 3,41
4,1 4,2 4,41
M m m m m m m
×
= ∈
1 41 1 2 41
k k k k k
M m m m
M M M R
n
n
FPGA
4.10 4.11 NLOS LOS DSP
NLOS
58
4.12
(Radio Frequency, RF)
4.13
FPGA RRC DSP
FPGA
sP1
0 0 1 1
2 (2 ) (2 ( )) (2 ( ))
i m n n
i m
i
A e e e
c
θ
(4.4)
59
* 1P P⋅ 2 2 sTπ ⋅ f 4.14 f
4.11
1 1 11 1 2 21 1 1 11 2 12
2 1 21 2 2 22 2 1 21 2 22
H H
H H
α α
α α
4.12 4.13
62
1 1 2 2 1
* * * * 1 1 2 2 3 3 4 4 1 2 1 1 2 4 3 3 4 2 1
1 1 2 2
* * 2 1 1 2
x r c
t t c
s c s c s c s c s c s c s c s c c
s s
( ) 12 12
( ) 1 21 1 2 21 * ** **( ) 2 1 22 1 1 22
i i
ix H s x H s= = i
3
i
, i i
s s
32 8 24 8
S2 S63 S64
64
Dk t
4 256×
127DS
127 128 127 128 0 3S126=D D A AS S 2 3
2 3 7S1=D D DS S S 7 6
0
1 2 1 2 6S0=D D DS S S
7 7DS
7 8 7 7 8 70D D DS S S
67
PE0 PE15PE0 PE15 ACS
64 ACS PM
(traceback enable)
CCD CCD
DSP
4.29
31.86 10−× 4.30
4.31
PCH CP2
SCH CS
RRCRRC t2
PCH CP2
SCH CS
RRCRRC t2
RRCRRC
69
Matched Filter
Matched Filter
Matched Filter
Matched Filter
70
Maximum value of match filter output Maximum value of match filter
output
4.5
O u tput
> M ax_V alue?
S et C oun t=0
C ount+ +
E nd
Y es
N o
Y es
N o
S tart
O u tput
> M ax_V alue?
S et C oun t=0
C ount+ +
E nd
Y es
N o
Y es
N o
71
Sk
S’k
maintain frame strobe
Sk
S’k
maintain frame strobe
4.10 DSP NLOS
900ns
FG2_MAIN_RST
75
+
77
H x
H x
H x
H x
4.21
00
10
00
01
01
11
10
11
00
10
00
01
01
11
10
11
81
S1 = 000001
S33 = 100001
S2 = 000010
S3 = 000011
R0 R1 R2 R3 R4 R5
S0 = 000000
S32 = 100000
S0 = 000000
S1 = 000001
S31 = 011111
S63 = 111111
S62 = 111110
S63 = 111111
S1 = 000001
S33 = 100001
S2 = 000010
S3 = 000011
R0 R1 R2 R3 R4 R5
S0 = 0 0 0 0 0 0
R0 R1 R2 R3 R4 R5
4.23 64 6 R0~R5
Compare Select 1PM +BM[ 1, or +32]k
t k i i Add
1PMi t+
1Di t+
2PM +BM[ 2, or +32]k t k i i
Compare Select 1PM +BM[ 1, or +32]k
t k i i Add
1PMi t+
1Di t+
2PM +BM[ 2, or +32]k t k i i
4.24
82
128 128 0 4S127=D A AS
…
128 128 0 4S127=D A AS
…
64
SettingSetting
DisplayDisplay
SettingSetting
DisplayDisplay
4.31 BER 1.13x10-
86
87
5,015 188,253
331 5,992
4,584 910,717
220 4,484
88
W-CDMA
QPSK QPSK
W-CDMA DPDCH
SCH DPCCH DSP FPGA
64 PN
DPCCH
DSPFPGAUSB
DSPC
FPGA
DSP
(H-ARQ)
90
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