A session with MODEL SIM simulator
A session with MODEL SIM simulatorThe MODELSIM simulator can be
either used as a standalone program or integrated into ALTERA or
XILINX synthesis environment. The synthesis environment provides
some convenient tool for VHDL program entry. To invoke MODELSIM,
double click the MODELSIM icon on the program window. The welcome
dialog has option and main project window appears simultaneously.
This is being given below
Figure 5.1 Welcome Dialog Box Figure 5.2 Main Project WindowThe
welcome dialog has options to create new project to create new
project, open a project, open documentation and proceed to
MODELSIM. Click on create new project option. The same can be done
by clicking proceed to Modelsim option and then to file> New>
projects from the Modelsim Main Window. This is shown below
Figure 5.3 Create Project window Enter project name and then the
project location. Lets put project name as half adder. The main
window appears as shown below
Figure 5.4 Model sim Editor WindowThen click on file > new
> source> vhdl to invoke the HDL editor as shown below
Figure 5.5 VHDL editor Window
Now the VHDL code is written in this editor.
Figure 5.6 VHDL Program of half adderThen click on file save
tool or select file> save from the menu. Give the file name with
extension .vhd and the press OK. Then compile the code for checking
any syntax error. The icon for the compile is below the file
option. When you click compile option, the flowing dialog box will
appear where sam is the file name which was last compiled.
Figure 5.7 Complier HDL source WindowThen select the compile
option. The result of the compilation appears on the main window as
shown below.
Figure 5.8 MODELSIM main WindowIf there is any error in the
code, then it will be shown in the above window with red color line
indicating error with remarks and error line.
Lets introduce error in the code where cout is assigned as cout
load design option in the main window, the following thing will
appear on the window.
Figure 5.10 Load Design WindowsIn this window all the entity
will be there. Select the entity which you have designed and the
click on the ADD button and then LOAD button. The following things
will appear on the main simulation window.
Figure 5.11 Simulate display WindowsThen go to View> signal.
This will launch a new waveform window as shown below, where the
entire signal is present.
Figure 5.12 Signal WindowsIn this window, a, b, c, d, m0, m1,
m2, m3 and m are the signal used in the entity declaration of the
program compiled. In the signal waveform window, go to Edit, the
following window will appear on the screen
Figure 5.13 Signal value forcing window There are so many
options available. If we want to give any signal as clock then
chose clock option. If we want to give some static values like 0, 1
or like vector types of input, then chose Force option. Then give
all the values of the input ports. Once all the value is given, go
to View option in the signal window and select wave> signals in
design.
Click on the signal in design option, this will display a
waveform window where all the signals will be there.
Figure 5.14 Waveform viewing windowNow click on the Run icon as
indicated in the waveform window. Now depending upon the values of
input signals on the port, in this case d, clk, reset, the output
will be generated depending upon the logic of the code. In the
above VHDL code for D filp is such that when reset=0 , then q
