© 2015 IEEE

Proceedings of the 1st Southern Power Electronics Conference (SPEC 2015), Fortaleza, Brazil, November 29-December 2, 2015

Modeling and Multi-Objective Optimization of 2.5D Inductor-Based Fully Integrated Voltage Regulatorsfor Microprocessor Applications

P. A. M. Bezerra,F. Krismer,T. A. Andersen,J. W. Kolar,A. Sridhar,T. Brunschwiler,T. Toifl,M. Jatlaoui,F. Voiron,Z. Pavlovic,N. Wang,N. Cordero,C. Rabot,C. O‘Mathuna

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978-1-4799-8779-5/15/$31.00 c©2015 IEEE

Modeling and Multi-Objective Optimization of 2.5D Inductor-Based FullyIntegrated Voltage Regulators for Microprocessor Applications

Pedro A. M. Bezerra1, Florian Krismer1, Toke M. Andersen2, Johann W. Kolar1, Arvind Sridhar3, ThomasBrunschwiler3, Thomas Toifl3, Mohamed Jatlaoui4, Frederic Voiron4, Zoran Pavlovic5, Ningning Wang5,

Nicolas Cordero5, Caroline Rabot5, Cian O’ Mathuna51Power Electronic Systems Laboratory (PES), ETH Zurich, Zurich, Switzerland

2Nordic Power Converter, Herlev, Denmark3IBM Research, Ruschlikon, Switzerland

4IPDiA, Caen, France5Tyndall National Institute, Cork, Ireland

e-mail: bezerra@lem.ee.ethz.ch, krismer@lem.ee.ethz.ch, toke@nopoc.com, kolar@lem.ee.ethz.ch, rvi@zurich.ibm.com,tbr@zurich.ibm.com, tto@zurich.ibm.com, mohamed.jatlaoui@ipdia.com, frederic.voiron@ipdia.com,

zoran.pavlovic@tyndall.ie, ning.wang@tyndall.ie, nicolas.cordero@tyndall.ie, caroline.rabot@tyndall.ie,cian.omathuna@tyndall.ie

Abstract – This work presents the modeling and themulti-objective optimization of a 2.5D inductor-basedFully Integrated Voltage Regulator (FIVR) with respect toefficiency η and/or chip area power density α , i.e. basedon the η-α-Pareto-front, for microprocessor applications.The Voltage Regulator consists of a four-phase interleavedbuck converter operated in Continuous Conduction Mode(CCM). The rated power of the considered converter is1W, and input and output voltages are constant andequal to Vin = 1.7V and Vout = 0.85V. The optimizationemploys analytical models for the switches, which resideon chip and are manufactured in a 32nm CMOS SOIprocess, and for the passive components, i.e. racetrackinductors with magnetic core material and deep-trenchcapacitors that are fabricated in a silicon interposer. Theoptimization procedure considers thermal aspects anddisregards solutions that lead to excessive componenttemperatures. According to the optimization results,either high efficiencies, greater than 90%, or high areapower densities, with chip power densities greater than20W/mm2 and interposer power densities higher than1.5W/mm2 are achievable. The optimized design point,selected from the η-α-Pareto-front, features an efficiencyof 90.1%, interposer power density of 0.309W/mm2, and achip power density of 27.4W/mm2.

Keywords – 2.5D Implementation, Buck Converter,Deep-Trench Capacitor, Racetrack Inductor,Optimization, Voltage Regulator.

I. INTRODUCTION

Datacenters and telecom systems contain a myriadof high performance multi-core microprocessors that arecharacterized by high current demands (> 100A [1]), alongwith precise and fast regulation requirements to allowfor energy savings using per-core Dynamic Voltage andFrequency Scaling (DVFS) [2]. This strategy requires realtime power management and Point of Load (PoL) powerconverters to provide granular voltage domains depending onthe load demand of each specific core or parts of a core.

Inductor-based Fully Integrated Voltage Regulators (FIVRs)have been largely used to implement the PoL converters in theaforementioned applications due to their high efficiencies andaccurate voltage regulation capabilities.

On-chip Voltage Regulator Modules (VRMs) are found inthe literature in different levels of integration and this workdistinguishes between 3D [3], 2D [4], and 2.5D structures [5],[6]. 3D structures employ at least two different activesemiconductor dies: one for the microprocessor and one forthe active power semiconductor components of the VRMs [3].The dies form a chip stack with Through Silicon Vias (TSVs)as vertical interconnects. In 2D integrated structures [4],all power components are integrated onto the microprocessor(load) die, which means that only one active semiconductordie is required. 2.5D VRMs differ from 2D and 3D structuresin having their power components split, usually the switcheson the microprocessor die, and passives off-chip, either ina laminate [5] or in an interposer [6]. Compared to 2Dintegration, the 2.5D integration features passive componentswith lower losses at same footprint size of the passivecomponents and allows for minimal loss of precious activesilicon area [5]. In addition, the use of the highly efficientsub-nanometer transistors of the microprocessor die for theVRMs, cf. Figure 1(a), allows for operation with switchingfrequencies greater than 100 MHz.

[6] presents a 2.5D buck converter implemented in 45nmSOI technology using racetrack coupled inductors and deep-trench capacitors that is operated with switching frequenciesup to 300 MHz. There, a peak efficiency of η ≈ 75% at apower density of α ≈ 1.5W/mm2 is achieved. In [5], Intelpresents the VRMs of its Haswell microprocessor with a peakefficiency of 90% and a vague estimation of the power density,determined from published data, of α ≈ 1W/mm2. Intelultilizes Fin-FET transistors assembled in 22nm and air-coreinductors built-in the package are utilized.

The aim of this work is to identify the design parametersand trade-offs for high conversion efficiencies, i.e. greaterthan 90%, and high power densities, i.e. chip power densitygreater than 20W/mm2 and interposer power density greaterthan 1.5W/mm2, for a 2.5D implementation of an integratedbuck converter, which is beyond the current state-of-the-

Vout

Cout

RCoRout

L1 RL1

Vin/2

LevelShifter

DigitalDelay

L1 RL1Vin/2

LevelShifter

DigitalDelay

0.20.30.4

1.151.201.25

iout

0

0.20.30.4

Ts/2 Ts(c)(b)(a)

∆IL1,pp

iL1

∆Iout,pp

D1

ioutiL1

ϕ

iL1iL4 iL2 iL3

Iout,pk

Iout,val

IL,pk

IL,val

[A]

[A]

[A]Interposer

Chip

Power Switches in32 nm CMOS SOIand Load

Cin

RCi

iph,tot

vclk,4

vclk,1

Vin

iL1,exp

Inductors +Deep TrenchCapacitors

TP2

TP1

TN1

TN2

Fig. 1. (a) 2.5D FIVR with both, the active components and the load, being realized in the same die, i.e. the chip; the passive componentsare built into a separate silicon interposer; (b) four-phase interleaved buck converter with stacked transistors, to allow for operation with inputvoltages of up to twice the breakdown voltage of one 32 nm single transistor; (c) general waveforms of iout, iL1,2,3,4, and iL1 of the ideal four-phase buck converter for interleaved operation. The waveforms are generated for L1,2,3,4 =L=15nH, Vin=1.7V, Vout=0.85V, fs=100MHz,and ϕ =90. The waveform iL1,exp is generated with RPMOS,on=40mΩ, RNMOS,on=50mΩ, and RL=3Ω.

art presented in the literature. In order to achieve theseperformance figures, a multi-objective optimization, based onthe calculation of the η-α-Pareto-front, is proposed to find theoptimum design parameters for a 2.5D inductor-type FIVR,i.e. the four-phase interleaved buck converter, depicted inFigure 1(b), for a given set of specifications and for theavailable component technologies. The investigated converteremploys power switches implemented in the IBM’s 32nmSOI process, high quality microfabricated racetrack inductors(manufactured by Tyndall) and high capacitance density deep-trench capacitors (manufactured by IPDiA) and, thus, takesadvantage of cutting edge technologies in order to push theFIVRs’ limits with regard to efficiency and power density.This work provides the components’ dimensions resultingfrom the optimization algorithm and the loss breakdownfor the optimized design. Section II summarizes the mainconverter specifications. Section III describes inductor-based converter topologies suitable for the studied applicationand the main waveforms of the four-phase interleaved buckconverter operated in Continuous Conduction Mode (CCM).Section IV describes the component models used to calculatelosses and chip size areas for the power switches, theinductors, and the capacitors. A focus is given to detailthe swithing process, which comprehension is necessary togenerate the MOSFETs’ switching loss models. The η-α-Pareto-optimization procedure is explained in Section V.Finally, Section VI discusses the calculated results for thefour-phase converter using racetrack inductors with magneticmaterial, which demonstrate the feasibility of designs withefficiencies greater than 90%, chip power densities of morethan 20W/mm2, and interposer power densities greater than1.5W/mm2.

II. CONVERTER SPECIFICATIONS

The rated power of the considered converter is 1W. Theinput and output voltage specifications are based on typicalPoL VRMs in the industry that are designed to powermicroprocessors at dc voltages in the range of 0.6V to 1.2Vdepending on the workload [1]. Based on this, nominal inputand output voltages of Vin = 1.7V and Vout = 0.85V arespecified. A maximum output voltage ripple of 0.5% of Vout isassumed for dimensioning of the output capacitors.

III. SUITABLE CONVERTER TOPOLOGIES

In the standard single-phase buck converter, the transistorshave to be able to block the full input voltage. In theconsidered application, the input voltage Vin = 1.7V isgreater than the 32 nm transistors’ drain-to-source break-downvoltage of Vds,max ≈ 1.2V. A possible approach to deal withthe high input voltage employs series stacked transistors inreplacement of the single high-side and low-side FETs asdepicted in Figure 1(b) and implemented in [4] for a single-phase converter. This solution only marginally increases theconverter area, in particular in comparison to a multilevelapproach employing flying capacitor converters, since thereis no need for additional passive components. The interleavedoperation of multiple buck converters, i.e. parallel connectionaccording to Figure 1(b) with gate signals phase-shifted byϕ = 2π/Nph (cf. Figure 1(c)) [7], where Nph is the number ofconverter phases, allows for a reduction of the output currentripple [8]. This paper investigates a four-phase interleavedbuck converter with two stacked transistors to compose thehigh-side and low-side switches. As in [7], the equations forthe switches’ and inductors’ instantaneous, mean, and rmscurrents equation consider piecewise linear current behavior,i.e. the implications of conduction, copper, and core losses onthe current waveforms are neglected.

IV. COMPONENT MODELS

In order to perform the converter optimization, the maindesign parameters, i.e. inductance, output capacitance, andthe corresponding losses and chip and interposer areas of theconverter elements, are derived as functions of the converteroperating conditions. This section outlines analytical modelsof the power switches manufactured in the 32 nm SOI process,the racetrack inductor with core material, and the deep trench-capacitors.

A. Power semiconductorsThe FETs’ conduction and switching losses are considered

to be dependent on their channel widths1 (TwP and TwN),instantaneous drain currents, and junction temperatures (Tj).

1Only the channel widths of the thin-oxide transistors are considered, sincethe transistor lengths are fixed by design rules in this technology.

L RL

2∙RPMOS,on

DTs > t > 0

Vin

Vout

L RL

2∙RNMOS,on

Vout

Ts > t > DTs(a)R

PM

OS,o

n [m

Ω]

120

0 150 300 450 600

95

70

45

20

Id [mA](b)

TwP=5 mm

10 mm15 mm20 mm25 mm

Tj=85°C

Fig. 2. (a) Phase equivalent circuits to calculate the switches’conduction losses. (b) Dependence of RPMOS,on on the channel widthfor various drain current values.

Switching losses are also very dependent on the duration ofthe dead-time intervals (td,1 and td,2) that are used to avoidshort circuits in the half-bridges during switching and allowfor soft-switching.

According to the equivalent circuits depicted Figure 2(a),the calculation of the conduction losses of the transistorsrequires their on-state resistances to be known: except forthe small time intervals during switching, the buck converterresides in one of these two states. The values of the on-state resistances for p- and n-channel MOSFETs (PMOSand NMOS) have been determined by means of Cadencesimulations. The obtained results reveal little dependency ofthe on-state resistances on the drain currents, cf. Figure 2(b)for Ron,PMOS, (the figure depicts the interpolated values alongwith the marked basic values). The on-state resistances,however, greatly depend on the transistor channel widths, i.e. agreat value of the transistor channel width enables a low valueof the on-state channel resistance.

The total conduction losses of the multi-phase buckconverter are calculated for the same channel widths for thestacked transistors of the same type, i.e. Tw,TP1 =Tw,TP2 = TwPand Tw,TN1 =Tw,TN2 = TwN, which results in

Pcond = 2Nph(RPMOS,on · I2

PMOS,rms +RNMOS,on · I2NMOS,rms

),

(1)where IPMOS,rms and INMOS,rms are the rms currents through thePMOS and NMOS switches.

Besides conduction losses, the switching losses amountto a significant part of the total losses of on-chip voltageregulators. Switching losses may be determined withanalytical models [3], simulation results [9], or measurementresults [10]. This work estimates the switching losses witha multi-variable interpolation algorithm that is parameterizedwith data obtained from a discrete number of Cadencesimulations for one converter half-bridge, using the testconfiguration depicted in Figure 3(a). In [11], a good matchon the converter efficiency and power density is obtainedcomparing experimental results with Cadence simulations.

During a switching process, a significant amount ofenergy may be transferred from one switch to another,especially when the Zero Voltage Switching (ZVS) conditionis fulfilled [10]. Therefore, the drain currents iD,TP1 , iD,TP2 ,iD,TN1 , and iD,TN2 and the blocking voltages vSD,TP1 , vSD,TP2 ,vDS,TN1 , and vDS,TN2 of the respective half-bridge need tobe observed simultaneously in order to calculate the totaldissipated energy. The energies dissipated by each switch of

the half-bridge are calculated with

ETPk,sw =∫ tend

tbegin

vSD,TPk iD,TPk dt, k = 1,2, (2)

for PMOS and

ETNk,sw =∫ tend

tbegin

vDS,TNk iD,TNk dt, k = 1,2, (3)

for NMOS; the time instants tbegin and tend correspond to thebeginning and the end of the switching process. If the result ofthe integration is positive, the corresponding switch dissipatesor stores energy. If the result of the integration is negative,the corresponding switch releases stored energy. The totalswitching loss energy generated by the half-bridge in oneswitching event is

Esw = ETN1,sw +ETN2,sw +ETP1,sw +ETP2,sw. (4)

Three different switching situations can occur in theinvestigated buck converter with synchronous rectification,which, with respect to its microprocessor application, is onlyoperated with unidirectional energy flow (from the supply tothe load):• case 1: positive inductor current (Isw > 0 in Figure 3(a))

and vx switches from Vin to 0;• case 2: positive or zero inductor current (Isw ≥ 0 in

Figure 3(a)) and vx switches from 0 to Vin;• case 3: negative current (Isw < 0 in Figure 3(a)) and vx

switches from 0 to Vin.In cases 1 and 3 the conditions to achieve ZVS are fulfilled,and it depends on the respective dead-time durations, whetherlossless switching operations are achieved. Case 2 alwaysleads to hard switching. Since this work considers peak-to-average (PAR) [12] ratios of the inductor current in the rangefrom 1 to 2, only cases 1 and 2 occur.

Figure 3(b) shows the simplified waveforms of theCadence simulations used to extract the switching lossenergies of the half-bridge configuration depicted inFigure 3(a). The required instantaneous switching current isset to a constant value Isw during the simulation. At t = t1athe switching event of case 1 occurs with the theoreticalcondition for ZVS fulfilled. At t = t2a the switching event ofcase 2 occurs with the condition for hard switching fulfilled.Figures 3(c) and (d) illustrate the main transient waveformsduring t1a ≤ t ≤ t1d and t2a ≤ t ≤ t2d, respectively. Thetransient processes during switching are detailed below.

1) t1a ≤ t ≤ t1d and case 1: Before t = t1a both PMOStransistors are in their on-states and conduct the switchingcurrent Isw; both NMOS transistors are turned off. Att = t1a, TP2 is commanded to switch off and its source-to-drain voltage vSD,TP2 increases. The increasing voltagevSD,TP2 decreases the gate to source voltage of TP1 and, asa consequence, the turn-off of TP1 occurs immediately afterthe turn off of TP2. Since the rise of vSD,TP1 is delayedwith respect to vSD,TP2 , the converter input voltage is notequally shared between TP1 and TP2. Due to the increasingvalues of vSD,TP1 and vSD,TP2 and the constant input voltageVin, the voltage between output and minus nodes of the half

Isw

Vmid=Vin/2

RG,P

iD,TN1

iD,PT1

iD,TP2

vSD,TP1

vSD,TP2

vGS,TP1

vGS,TP2

vGS,TN2

vGS,TN1

vG,N

vG,N

vG,P

t1a

td,1

t1d t2a t2c t2d

t2dt2a t2b t2c

t

t

t

vG,P

RG,N

vDS,TN2

vDS,TN1

iD,TN2

vx

Cin

Cmid

Vin

0time [ps]

50 100 150 200 2500time [ps]

80 160 240 320 400

(b)

(a)

(c) (d)

td,2

on

vx

Isw

off

-0.5

0

0.5

1

1.52

-0.8

0

0.8

1.6

2.43.2

-0.6

0

0.6

1.2

1.82.4

Vol

tage

[V

],

Curr

ent

[A] an

d P

ower

[W

]

-0.5

0

0.5

1

1.52

-0.8

0

0.8

1.6

2.43.2

-1.5

-1

-0.5

0

0.51

Vol

tage

[V

],

Curr

ent

[A] an

d P

ower

[W

]

vx

pTN1+pTN2

vSD,TP1

iD,TP2

vSD,TP2

vDS,TN1

vDS,TN2

iD,TP1

pTP1+pTP2

iD,TN2

iD,TP2

iD,TN1

t1dt1a t1b t1c

pTP1+pTP2

iD,TN1

iD,TP1vSD,TP1

vSD,TP2

vDS,TN1

iD,TN2

vDS,TP2vDS,TN2

pTN1+pTN2

vG,P vG,P

vG,N vG,N

vx

Fig. 3. (a) Test configuration of a single converter phase used to obtain the switches’ switching loss parameters by means of Cadencesimulations. (b) Simplified representation of the gate signals used in the simulations to extract the loss parameters of the considered switchingcases 1 and 2 , which occur during t1a < t < t1d and t2a < t < t2d, respectively. (c) Converter waveforms that describe the ZVS event of case 1(Isw = 500mA). (d) Converter waveforms that describe the hard-switching event of case 2 (Isw = 500mA). The waveforms generated forVin = 1.7V, TwP = TwN = 12mm, RG,P = RG,N = 240mΩ, td,1 = 200ps, td,2 = 100ps. During changes of gate to source voltages, significantgate currents arise. For this reason, iD,TP1 6= iD,TP2 and iD,TN1 6= iD,TP2 are observed during the respective time intervals.

bridge, vx, decreases and eventually becomes negative whenthe body diodes of the NMOS switches start to conduct.Since the gate of TN1 is clamped to Vin/2, the decrease ofvx turns on TN1. During t1a ≤ t ≤ t1b the waveform pTP1 +pTP2 is most of the time positive and the waveform pTN1 +pTN2 is negative meaning that the PMOS transistors consumeenergy (switching losses, energy stored in the effective outputcapacitances) and the NMOS transistors release the energystored in their effective output capacitances. The total energylost during this time interval is obtained by integrating theinstantaneous NMOS and PMOS power curves, which, in thedepicted case, leads to almost no losses during t1a ≤ t ≤ t1b(ZVS). At t = t1b, vx reaches its minimum value, whichremains constant during t1b≤ t ≤ t1c, when the channel of TN1and the body diode of TN2 are conducting the full Isw, whichleads to increased conduction losses during this time interval.At t = t1c, TN2 is turned on and the output current Isw starts toalso flow through the channel of TN2.

2) t2a ≤ t ≤ t2d and case 2: Before t = t2a both NMOStransistors are in their on-states and conduct the switchingcurrent Isw; both PMOS transistors are turned off. At t = t2a,TN2 is commanded to switch off forcing its body diode toconduct. At t = t2b, vx reaches its minimum value, whichremains constant during t2b≤ t ≤ t2c, when the channel of TN1and the body diode of TN2 are conducting the full Isw, whichleads to increased conduction losses during this time interval.At t = t2c, TP2 is commanded to switch on and its source-to-drain voltage vDS,TP2 starts to decrease. Since TN1 is in the on-state and the body diode of TN2 is subject to reverse recovery(this diode has been conducting the switching current Isw), vx

does not change immediately and this leads to an unbalancingof the source-to-drain voltages of TP2 and TP1. After thebody diode of TN2 is recovered, vDS,TN2 starts to increase and,as a consequence, vx starts to increase with nearly constantslope until it reaches Vin at t = t2d. Since the gate of TN1is clamped to Vin/2, the increase of vx decreases the gate-to-source voltage of TN1, turning it off with the same voltageslope, which results in an approximate voltage sharing of vxbetween TN1 and TN2. During the time interval t2c ≤ t ≤ t2d,the reverse recovery current and the additional current flowingthrough the gate of TN1 increases the instantaneous lossesof all transistors (especially those of TP1 due to the delayedturn-off). During the entire switching process, t2a ≤ t ≤ t2dthe waveforms pTP1 + pTP2 and pTN1 + pTN2 are almost onlypositive, meaning that both, NMOS and PMOS switches,dissipate energy.

The obtained results of Figure 4(a) show that the energylosses of the switching transition of case 2 always increasewith the increasing of the switching currents, while the energylosses of case 1 present a minimum when the dead-timeinterval td,1 is just enough to charge and discharge the effectiveoutput capacitance of the PMOS and NMOS, not allowing thebody diode of TN2 to conduct. The total switching losses ofthe multi-phase buck converter are calculated also consideringTw,TP1 =Tw,TP2 = TwP and Tw,TN1 =Tw,TN2 = TwN, which resultsin

Psw = Nph(Esw,case1(IL,pk)+Esw,case2(IL,val)

)fs, (5)

The gate charge of the power switches also contribute toa significant part of the total power semiconductor losses.

Esw

[p

J]

100

0 150 300 450 600

75

50

25

0

Qg,N

MO

S [p

C]

30

22.5

15

7.5

0

Isw [mA]0 150 300 450 600

Isw [mA]

Tj=85°C

Esw,case2

Esw,case1TwN=5 mm

10 mm

15 mm

20 mm

25 mm

Tj=85°C

Fig. 4. (a) Total energy losses of case 1 and case 2 (Esw,case1 andEsw,case2) switching events for various drain current values. Plotsgenerated using Tw,TP1 = Tw,TP2 = 12mm and td,1 = td,2 = 120ps(b) Dependence of Qg,NMOS on the channel width for various draincurrent values.

Results of Figure 4(b) show almost no dependence ofQg,NMOS on the switching currents. The gate charges,however, greatly depend on the transistor channel widths. Thegate charge losses are calculated with

Pg = NphVgs(Qg,TP2(IL,val)+Qg,TN2(IL,val))

+Qg,mid(IL,val, IL,pk) fs, (6)

where Qg,TP2 and Qg,TN2 are the charge sourced by the gatesupplies to completely turn off the PMOS and completely turnon the NMOS, respectively, Qg,mid is the sourced/absorbedcharge by Vmid in one switching period, and Vgs = 0.85V isthe maximum value of the transistors gate voltage.

B. Power inductorsIn this work, the converter optimization is performed

for racetrack inductors using the same analytical equations,materials, and technology limitations as in [12], wherethe models have been verified with good accuracy againstmeasurements from real inductors. The calculation of thecopper losses of the inductors considers dc and ac windinglosses, which are estimated using the methodology and (23)−(26) of [12]. The utilized core material is Ni45Fe55, whichis considered to be linear and anisotropic with a relativepermeability µc = 280. The calculation of the total corelosses considers hysteresis losses and eddy current losses. Thehysteresis losses are calculated using (30) of [12] and thecoefficients Kh =300 and b=1.73. The eddy currents in thecore cause frequency dependent losses that are calculated with(31) of [12].

C. Output capacitorsThe Passive Integration Connective Substrate (PICS)

silicon based capacitor technology [13], developed by IPDIA,is employed in the proposed design. This technology is acombination of deep-trench and high temperature dielectricin Metal-Insulator-Metal (MIM) that allows for very highcapacitance densities of up to 250nF/mm2, with lowEquivalent Series Resistances (ESR < 150mΩ for C > 50nF)and low Equivalent Series Inductance (ESL ≈ 5− 10pH)in the switching frequency range of 10MHz to 150MHz.To obtain this low parasitic values, the capacitor designuses a large number of elementary capacitive cells, that areinterconnected onto a parallel interconnection network [13].For this specific implementation it is shown that the ESRis proportional to the inverse of the number of elementary

cells, and as such can be adjusted by design. Theinterconnection network is optimized with respect to ESL,featuring interleaved structures that prevent local currentloops, such as to increase the capacitor self-resonancefrequency. In this work the ESR is modeled for five differenttypes of capacitors, based on experimental data provided byIPDiA in the form f (C) = k110k2C. The calculation of theESL assumes that the capacitor self-resonance is at fress=2 fs.

V. MULTI-OBJECTIVE CONVERTER OPTIMIZATIONAND RESULTS

Figure 5(a) illustrates the flowchart of the implementedoptimization procedure. The optimization algorithm startswith the definition of the converter specifications, summarizedin Section II. Next, the design space X = x1,x2, ...,xp isdefined, where xi is shown in Figure 5(a) and the parameterdefinitions, range of sweeps, and step sizes are shown inTable I. The geometrical parameters of the racetrack inductorwith core material can be identified in Figure 4 of [12].

TABLE IBuck converter variables’ ranges and step sizes of the

explored design space.

Parameters Range Step size UnitPAR [1.2...2 ] 0.4 –Number of turns, N [1...5 ] 1 –Winding width, tw [10...1200 ] 10 or 500 µmWinding spacing, ts [10...50 ] 20 µmWinding thickness, tt [10...50 ] 20 µmCore length, cl [1...10 ] 3 mmCore thickness, ct [1...10 ] 3 µmNMOS channel width, TwN [5...15 ] 5 mmPMOS channel width, TwP [5...15 ] 5 mmDead-time, td,1 [20...120 ] 50 psDead-time, td,2 [20...70 ] 50 psOutput capacitance, Cout [0.1...500 ] 10.2 nF

The switches’ loss parameters are extracted for themaximum temperature of 85 C [11]. The output capacitoris optimized to require the minimum area possible and stillfulfil the maximum output voltage ripple criterion. Theoptimization algorithm outputs the total converter efficiencies,the design parameters of all power components, and thecalculated main parameters related to the converters’ operatingconditions, e.g. fs, D, and ∆ILpp, for all designs in theconsidered design space. Designs with switches’ loss densitygreater than 10W/mm2 and/or inductor peak flux densitiesabove the saturation limit of Bsat = 1.6T are excluded. Forthe given application, it is required to achieve 90% efficiencywith maximal power density possible allowed by the employedtechnologies. Figure 5(b) depicts the optimization results andhighlights the selected design with Peak-to-Average inductorcurrent Ratio PAR=1.2, fs=70MHz, L=51nH, C=10.3nF,TwP=15mm, TwN=10mm, td,1 = 120ps and td,2 = 70ps. Thisdesign features η=90.1% and α=0.306W/mm2 (chip powerdensity is αPMIC=27.4W/mm2 and interposer power densityis αinter=0.309W/mm2).

Set converter specifications: Vout, Vin, Pout, ∆Vo,max

Generate the Pareto-front;selection of the final design

Initialize the analytical inductor and switches models with xi

Perform the inductor dc calculationsand determine switches’ Rds,on

Calculate the converter main currents, voltages, D, and fs values

Calculate the efficiency ρi and the power density αi

i = i+1

Calculate inductors’loss and area

Switches’ optimization and calc. loss and area

Capacitor optimizationand calc. losses and area

i = p ?

Set converter design space X=x1,x2,...,xp where xi = [ PARi, Ni, tw,i, ts,i, tt,i, cl,i, ct,i, TwP,i, TwN,i]

i =1

no

yes

inductorcopper losses

18%

capacitorlosses<1%

conductionlosses32%

switchinglosses15%

losses breakdowngate charge

losses6%

inductorcore losses

30%

frequency colormap - all plots [MHz]

400 300 200 100 0

(a) (b)

PMIC

effici

ency

(η)

[%

]

power density (α) [W/mm2]

four-phase buck

0.1 1 30.3

100

70

95

90

85

80

75PAR=2 1.6 1.2 ef

fici

ency

(η i

nte

r) [%

]

power density (αinter) [W/mm2]0.1 1 30.3

100

70

95

90

85

80

75

interposer

PAR=2 1.6 1.2

effici

ency

(η P

MIC

) [%

]

100

70

95

90

85

80

75

power density (αPMIC) [W/mm2]

10020 40

PAR=1.2

1.6

2

Fig. 5. Multi-objective optimization of the four-phase buck converter. (a) Flowchart of the optimization algorithm; (b) Plots of the η −α

Pareto-fronts that result for the Power Management IC (PMIC), the interposer, and the complete four-phase buck converter; losses breakdowncalculated for the selected Pareto-optimal design, showing that the inductor losses and the semiconductor losses of this design are ≈ 48% and≈ 53% of the total losses, respectively. The Pareto-fronts show that either high efficiencies or high power densities are achievable.

VI. CONCLUSIONS

This work details the design procedure and the multi-objective Pareto-optimization of a 2.5D four-phase interleavedand inductor-based FIVR. For this purpose analyticalmodels for 32nm CMOS SOI power switches, racetrackinductors with core material, and deep-trench capacitors aresummarized. The results demonstrate that optimal designsachieve efficiencies greater than 90% or power densitiesgreater than 1.5W/mm2, but not simultaneously. The selecteddesign achieves an efficiency of 90.1%, an interposer powerdensity of 0.309W/mm2, and a chip power density of27.4W/mm2.

ACKNOWLEDGEMENTSPart of this work was carried out within the European

CarrICool Project under the Seventh Framework Programfor Research and Technological Development (FP7-ICT-619488).

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